CN114550651B

CN114550651B - Gate drive circuit, drive method of gate drive circuit and display panel

Info

Publication number: CN114550651B
Application number: CN202210447430.2A
Authority: CN
Inventors: 陶治橙; 袁海江
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2022-04-27
Filing date: 2022-04-27
Publication date: 2022-08-05
Anticipated expiration: 2042-04-27
Also published as: CN114550651A; US11798490B1; US20230351971A1

Abstract

The application discloses a grid driving circuit, a driving method of the grid driving circuit and a display panel, wherein the grid driving circuit comprises a grid starting signal selection circuit, at least two grid driving units and at least two grid starting signal lines, the grid driving units are driven in a one-to-one correspondence mode with display areas, and the grid starting signal lines are connected with the grid driving units in a one-to-one correspondence mode; and after receiving the gate initial signal, the gate initial signal selection circuit outputs the gate initial signal to a corresponding gate initial signal output end to drive a corresponding display area. Through the design, the grid driving unit drives the scanning lines in the display panel separately, and all the scanning lines in the whole display panel do not need to be scanned line by line under special conditions such as screen clock display function, fingerprint identification pictures and the like, so that the power consumption is saved.

Description

Gate drive circuit, drive method of gate drive circuit and display panel

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a gate driving circuit, a driving method of the gate driving circuit, and a display panel.

Background

At present, Display devices have been widely used in various electronic products as Display components of electronic devices, and no matter a Liquid Crystal Display (LCD) panel or an Organic Light-Emitting Display (OLED) panel, the Display devices need to scan gates row by row through a gate driving circuit.

In some specific display pictures (such as a screen clock display function, a fingerprint identification picture and the like), only a small part of pictures are displayed, and other areas are completely black, so that the power consumption cannot be saved if the conventional mode is adopted for line-by-line scanning.

Disclosure of Invention

The application aims to provide a grid driving circuit, a driving method of the grid driving circuit and a display panel, which can save power consumption in some specific display pictures.

The application discloses a grid drive circuit for driving scanning lines in a display panel, along data line direction in the display panel, the display panel is divided into at least two display areas, the grid drive circuit comprises a grid starting signal selection circuit, at least two grid drive units and at least two grid starting signal lines, each grid drive unit drives the corresponding display area, the grid starting signal lines are connected with the grid drive units in a one-to-one correspondence manner, the grid starting signal selection circuit comprises a grid starting signal input end and at least two grid starting signal output ends, the grid starting signal input end receives a grid starting signal, the grid starting signal output ends are connected with the grid starting signal lines in a one-to-one correspondence manner, and the grid starting signal is output; and after receiving the gate starting signal, the gate starting signal selection circuit outputs the gate starting signal to a corresponding gate starting signal output end to drive a corresponding display area.

Optionally, the gate start signal selection circuit includes at least two selection units, one end of each selection unit is connected to the gate start signal input end, and the other end of each selection unit is connected to the gate start signal output end in a one-to-one correspondence manner; the selection unit comprises at least one first switch and/or at least one second switch, the first switch is an N-type triode or a P-type triode, the second switch is an N-type triode or a P-type triode, the first switch receives a first time sequence signal, and the second switch receives a second time sequence signal; and the grid starting signal selection circuit controls the corresponding selection unit to output the grid starting signal according to the first time sequence signal and the second time sequence signal received by the selection unit.

Optionally, an emitter or a collector of the first switch is connected to the gate start signal input terminal, a base of the first switch receives a first timing signal through a first signal line, the collector or the emitter of the first switch is connected to a collector or an emitter of the second switch, the base of the second switch receives a second timing signal through a second signal line, and the emitter or the collector of the second switch is connected to the gate start signal output terminal.

Optionally, the first switches in different ones of the selection units receive the first timing signal through the same first signal line, and the second switches in different ones of the selection units receive the second timing signal through the same second signal line.

Optionally, the gate start signal selection circuit includes a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, the first selection unit is composed of two N-type triodes, and bases of the two N-type triodes respectively receive the first timing signal and the second timing signal; the second selection unit is composed of an N-type triode and a P-type triode, and the N-type triode and the P-type triode respectively receive a first time sequence signal and a second time sequence signal; the third selection unit is composed of two P-type triodes, and bases of the two P-type triodes respectively receive a first timing signal and a second timing signal; the fourth selection unit is composed of a P-type triode and an N-type triode, and bases of the P-type triode and the N-type triode respectively receive the first timing signal and the second timing signal;

when the first time sequence signal and the second time sequence signal are both high level signals, the grid starting signal is output to the corresponding grid driving unit through the first selection unit; when the first time sequence signal and the second time sequence signal are both low level signals, the gate start signal is output to the corresponding gate drive unit through the third selection unit; when the first timing signal is a high-level signal and the second timing signal is a low-level signal, the gate start signal is output to the corresponding gate driving unit through the second selection unit; and when the first timing signal is a low-level signal and the second timing signal is a high-level signal, the gate start signal is output to the corresponding gate driving unit through the fourth selection unit.

Optionally, the gate start signal selection circuit is disposed at two sides of the gate driving unit along a direction of the data line in the display panel.

Optionally, the gate start signal selection circuit is disposed at a side of the gate driving unit close to a data line of the display panel to receive a signal.

Optionally, along a data line direction in the display panel, an output port of the previous gate driving unit, which is connected to the last scan line corresponding to the display area, is communicated with an input port of the next gate driving unit.

The application also discloses a driving method of the gate driving circuit, which is used for driving the gate driving circuit and comprises the following steps:

a gate starting signal input end of a gate starting signal selection circuit in the gate driving circuit receives a gate starting signal;

the grid starting signal selection circuit outputs the grid starting signal to a corresponding grid starting signal output end; and

and a gate driving unit in the gate driving circuit receives a gate start signal through a gate start signal line and drives a corresponding display area.

The application also discloses a display panel, the display panel includes array substrate and gate drive circuit as above, the gate drive circuit with scanning line in the array substrate is connected.

This application is through dividing into two at least gate drive units with ordinary gate drive circuit, separately drive the scanning line in the display panel through two at least gate drive units, in some special circumstances such as screen clock display function, fingerprint identification picture, can only show the picture that needs show through combining grid initial signal selection circuit and gate drive unit, and other regions that do not need to show then do not have scanning signal to transmit to the scanning line in, do not need to carry out line by line scanning to all scanning lines in whole display panel, thereby the power consumption has been saved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

fig. 1 is a schematic view of a first display panel provided in the present application;

FIG. 2 is a schematic diagram of a second display panel provided in the present application;

FIG. 3 is a schematic diagram of a gate start signal selection circuit provided herein;

FIG. 4 is a schematic diagram of a third display panel provided herein;

fig. 5 is a flowchart of a driving method of a gate driving circuit provided in the present application.

10, a display panel; 20. an array substrate; 30. a display area; 31. scanning a line; 40. a source driver circuit; 100. a gate drive circuit; 110. a gate driving unit; 120. a gate start signal line; 130. a gate start signal selection circuit; 131. a gate start signal input terminal; 132. a gate start signal output terminal; 140. a selection unit; 141. a first switch; 142. a second switch; 143. a first selection unit; 144. a second selection unit; 145. a third selecting unit; 146. and a fourth selection unit.

Detailed Description

It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.

The present application is described in detail below with reference to the figures and alternative embodiments.

As shown in fig. 1, the present application provides a Display panel, and the Display panel 10 may be an Organic Light-Emitting Display panel (OLED) or a Liquid Crystal Display panel (LCD). The display panel 10 includes an array substrate 20, a gate driving circuit 100 and a source driving circuit 40, wherein the array substrate 20 is provided with a plurality of scan lines 31 arranged in parallel and a plurality of data lines arranged in parallel, the scan lines 31 and the data lines are arranged vertically, and the plurality of scan lines 31 and the plurality of data lines enclose a plurality of sub-pixels; the gate driving circuit 100 is located at one end of the scan line 31, connected to the scan line 31, and configured to provide a scan signal to the scan line 31; the source driving circuit 40 is located at one end of the data line, connected to the data line, and provides a data signal to the data line. The Gate driving circuit 100 may be formed On the Array substrate 20 to form a Gate Driver On Array (GOA) circuit; or may be formed outside the array substrate 20 and bonded to the array substrate 20 as an independent chip structure.

In the display panel 10, the display area is divided into at least two display regions 30 along the data line direction, that is, the scanning lines 31 are divided into at least two regions along the data line direction. Correspondingly, the conventional gate driving circuit 100 is divided into at least two gate driving units 110, i.e., the segmented gate driving circuit 100.

Specifically, the gate driving circuit 100 includes a gate start signal selection circuit 130, at least two gate driving units 110, and at least two gate start signal lines 120, where the gate driving units 110 are driven in a one-to-one correspondence with the display regions 30, the gate start signal lines 120 are connected to the gate driving units 110 in a one-to-one correspondence, the gate start signal selection circuit 130 includes a gate start signal input end 131 and at least two gate start signal output ends 132, the gate start signal input end 131 receives a gate start signal, and the gate start signal output ends 132 are connected to the gate start signal lines 120 in a one-to-one correspondence and output the gate start signal; after receiving the gate start signal, the gate start signal selection circuit 130 outputs the gate start signal to the corresponding gate start signal output end 132, so as to drive the corresponding display region 30.

In the embodiment of the present application, the conventional gate driving circuit is divided into at least two gate driving units 110, the scanning lines 31 in the display panel 10 are separately driven by the at least two gate driving units 110, under some special conditions such as a screen clock display function, a fingerprint identification picture, etc., only a picture to be displayed can be displayed by combining the gate start signal selection circuit 130 and the gate driving unit 110, and no scanning signal is transmitted to the scanning lines 31 in other areas not required to be displayed, and all the scanning lines 31 in the entire display panel 10 do not need to be scanned line by line, thereby implementing the sectional control of the display panel 10. For example, the screen-off clock display function of the display panel 10 displays only one region thereof under the condition of reducing the refresh rate, the resolution in the direction of the scanning line 31 is changed to a fraction of the original resolution, and the data line transmits data with a fraction of the normal resolution, thereby saving power consumption. In addition, the gate driving circuit 100 is improved on the display panel 10, and although a part of the circuit structure is newly added, the cost is basically unchanged and the yield is not affected.

The adjacent gate driving units 110 may not be connected, so that after a part of the gate driving units 110 receive the gate start signal, only the corresponding display regions 30 are independently driven, and the different gate driving units 110 do not interfere with each other, so that the scan lines 31 in the dark-state image are not driven.

Correspondingly, for example, the display area 30 is divided into a first display area 30, a second display area 30, a third display area 30 and a fourth display area 30 along the data line direction; correspondingly, the gate driving circuit 100 includes a first gate driving unit 110, a second gate driving unit 110, a third gate driving unit 110, and a fourth gate driving unit 110, so as to correspondingly drive the first display area 30, the second display area 30, the third display area 30, and the fourth display area 30 one by one. If only the second display area 30 is needed to display a picture, and the first display area 30, the third display area 30 and the fourth display area 30 do not display a picture, at this time, the gate start signal selection circuit 130 outputs the gate start signal to the second gate driving unit 110, the first row scanning line 31 to the last row scanning line 31 in the second display area 30 are sequentially scanned, and the scanning lines in the first display area 30, the third display area 30 and the fourth display area 30 are not scanned, so that the pixels can quickly respond, and the power consumption can be greatly reduced.

Of course, adjacent gate driving units 110 may be connected to each other, as shown in fig. 2, in this case, along the data line direction, the output port connected to the last scanning line 31 corresponding to the display region 30 in the previous gate driving unit 110 is communicated with the input port of the next gate driving unit 110.

For example, the display area 30 is divided into a first display area 30, a second display area 30, a third display area 30 and a fourth display area 30 along the data line direction, and correspondingly, the gate driving circuit 100 includes a first gate driving unit 110, a second gate driving unit 110, a third gate driving unit 110 and a fourth gate driving unit 110, so as to correspondingly drive the first display area 30, the second display area 30, the third display area 30 and the fourth display area 30 one to one.

If only the second display area 30 is needed to display the image, and the first display area 30, the third display area 30 and the fourth display area 30 do not display the image, at this time, the gate start signal selection circuit 130 outputs the gate start signal to the second gate driving unit 110, the first row scanning line 31 to the last row scanning line 31 in the second display area 30 are sequentially scanned, and then the scanning lines 31 in the third display area 30 and the fourth display area 30 start scanning; since the first, third, and

fourth display regions

30, 30 do not need to display a screen, the data lines do not transmit display data to the first, third, and fourth display regions 30, and the scan lines 31 are scanned but do not display a screen. Although this method increases power consumption, it is applicable to a case where a display screen is large, and it is also possible to reduce the refresh rate of the display panel 10 and overcome the problem of increased power consumption to some extent. If a full screen needs to be displayed, at this time, only the gate start signal needs to be output to the first gate driving unit 110, so that all the scanning lines 31 in the display panel 10 are scanned line by line. In this way, the gate driver circuit 100 can be applied not only to normal screen display but also to special screen display, and can reduce power consumption in a targeted manner.

As shown in fig. 1 and fig. 3, the gate start signal selection circuit 130 includes at least two selection units 140, one end of each selection unit 140 is connected to the gate start signal input end 131, and the other end is connected to the gate start signal output ends 132 in a one-to-one correspondence manner; the selection unit 140 includes at least one first switch 141 and at least one second switch 142, the first switch 141 is an N-type transistor or a P-type transistor, the second switch 142 is an N-type transistor or a P-type transistor, the first switch 141 receives a first timing signal (a 0), and the second switch 142 receives a second timing signal (a 1); the gate start signal selection circuit 130 controls the corresponding selection unit 140 to output the gate start signal according to the first timing signal (a 0) and the second timing signal (a 1) received by the selection unit 140.

In the embodiment of the present application, the selection unit 140 in the gate start signal selection circuit 130 is formed by transistors, and the voltage requirements for turning on different transistors are different, such as an N-type transistor (NPN) is turned on at a high level and turned off at a low level; a P-type triode (PNP) is turned on at low level and turned off at high level. The selection conditions of the different selection units 140 are different through the arrangement and combination of the different transistors, and the selection units 140 transmit the gate start signal to the corresponding gate driving units 110 only when the first timing signal (a 0) and the second timing signal (a 1) both satisfy the turn-on conditions for the transistors. The selection unit 140 in the embodiment of the present application has a simple structural design, occupies a small space, has various selection conditions, and has accurate signal judgment conditions, so that the selection unit is applicable to most display frames, and has a wide application prospect.

Generally, the transistor has three ports, i.e., an emitter, a collector and a base, in this embodiment, the emitter or the collector of the first switch 141 is connected to the gate start signal input terminal 131, the base of the first switch 141 receives the first timing signal (a 0) through a first signal line, the collector or the emitter of the first switch 141 is connected to the collector or the emitter of the second switch 142, the base of the second switch 142 receives the second timing signal (a 1) through a second signal line, and the emitter or the collector of the second switch 142 is connected to the gate start signal output terminal 132.

It should be noted that the embodiments of the present application are not limited to the number of the selection units 140 in the gate start signal selection circuit 130; although the larger the number of the selection units 140, the larger the number of the gate driving units 110 and the number of the display regions 30, the finer driving is easier to achieve, and the power consumption can be further reduced. However, the structure of the gate start signal selection circuit 130 is more complicated, the size is increased, and it is difficult to narrow the frame, and thus, the gate start signal selection circuit can be designed specifically according to actual conditions.

When there are only two gate driving units 110, there are only two selecting units 140, and the two selecting units 140 may be respectively composed of only one transistor of different types; alternatively, the two selection units 140 may both be composed of two identical or different transistors, as long as the signal transmission under different conditions can be realized, and the same idea is also applied to the principle when there are only two gate driving units 110.

When the gate start signal selection circuit 130 has four selection units 140, the four selection units 140 are respectively a first selection unit 143, a second selection unit 144, a third selection unit 145 and a fourth selection unit 146, the first selection unit 143 is formed by two N-type triodes, and bases of the two N-type triodes respectively receive a first timing signal (a 0) and a second timing signal (a 1); the second selection unit 144 is composed of an N-type transistor and a P-type transistor, which respectively receive the first timing signal (a 0) and the second timing signal (a 1); the third selection unit 145 is composed of two P-type triodes, and bases of the two P-type triodes respectively receive a first timing signal (a 0) and a second timing signal (a 1); the fourth selecting unit 146 is composed of a P-type triode and an N-type triode, the bases of which respectively receive the first timing signal (a 0) and the second timing signal (a 1); at this time, the first timing signal (a 0) and the second timing signal (a 1) are both high level signals or both low level signals, and of course, it is also possible if the first timing signal (a 0) and the second timing signal (a 1) are different level signals, which only results in more complicated design.

At this time, when the first timing signal (a 0) and the second timing signal (a 1) are at a high level, the two N-type transistors in the first selection unit 143 are turned on, and the gate start signal is transmitted to the corresponding gate driving unit 110 through the first selection unit 143; only one N-type transistor in the second selection unit 144 is turned on, the other P-type transistor is turned off, and the gate start signal cannot pass through the second selection unit 144; two P-type triodes in the third selection unit 145 are turned off, and the gate start signal cannot pass through the third selection unit 145; in the fourth selecting unit 146, only one N-type transistor is turned on, the other P-type transistor is turned off, and the gate start signal still cannot pass through the fourth selecting unit 146; therefore, after the gate driving circuit 100 receives the gate start signal, the gate start signal is filtered in the gate start signal selection circuit 130, and only the first selection unit 143 and only the gate driving unit 110 connected to the first selection unit 143 can drive the scan line 31 in the corresponding display region 30, so that the region displays the image.

When the first timing signal (a 0) and the second timing signal (a 1) are both high-level signals, a gate start signal is output to the corresponding gate driving unit 110 through the first selection unit 143; when the first timing signal (a 0) and the second timing signal (a 1) are both low-level signals, a gate start signal is output to the corresponding gate driving unit 110 through the third selecting unit 145; when the first timing signal (a 0) is a high level signal and the second timing signal (a 1) is a low level signal, the gate start signal is output to the corresponding gate driving unit 110 through the second selection unit 144; when the first timing signal (a 0) is a low level signal and the second timing signal (a 1) is a high level signal, the gate start signal is output to the corresponding gate driving unit 110 through the fourth selection unit 146.

When the number of the selection units 140 in the gate start signal selection circuit 130 exceeds four, the number of the triodes in each selection unit 140 may be further increased to increase the number of types of the permutation and combination; correspondingly, the number of timing signals is also increased so that the corresponding selection condition of each selection unit 140 is different.

In addition, the gate start signal selection circuit 130 may have selection units 140 of the same triode combination type in addition to selection units 140 of different triode combination types, so that two or more gate driving units 110 may be simultaneously controlled to drive the scan lines 31 in the corresponding display regions 30, so that two or more display regions 30 generate pictures. When a special picture only needs to be displayed at the top and the bottom of the display panel 10 or only needs to be displayed in the spaced display areas 30, the pictures can be displayed simultaneously in this way without scanning all the scanning lines 31, and therefore, the synchronization rate of the pictures can be improved, and the power consumption can be saved.

In a general display device, a timing control chip transmits signals to the gate driving circuit 100 and the source driving circuit 40 to control a screen display. For the embodiment of the present application, the first timing signal (a 0) and the second timing signal (a 1) are from a timing control chip, and the gate start signal selection circuit 130 is connected to the timing control chip through a first signal line to receive the first timing signal (a 0); and is connected to the timing control chip through a second signal line to receive a second timing signal (a 1). When the number of the selection units 140 in the gate start signal selection circuit 130 is large, if each selection unit 140 receives the timing signals through two signal lines, the number of the signal lines is too large, and the size of the frame is increased. Therefore, the embodiment of the present application may enable the first switch 141 in different ones of the selecting units 140 to receive the first timing signal through the same first signal line (a 0), and enable the second switch 142 in different ones of the selecting units 140 to receive the second timing signal through the same second signal line (a 1); then, the same first signal line is connected to the plurality of first switches 141 through a plurality of pins, and the same second signal line is connected to the plurality of second switches 142 through a plurality of pins, so that the number of the first signal line and the second signal line is reduced, and the reduction of the frame is facilitated.

As shown in fig. 4, the embodiment of the present application further discloses a specific position design of the gate driving circuit 100, and for the gate driving unit 110, a plurality of GOA units may be formed on the display panel 10; for the gate start signal selection circuit 130, two sides of the GOA unit, i.e. along the direction of the data lines in the display panel 10, can be arranged, and the gate start signal selection circuit 130 is arranged at two sides of the gate driving unit 110. Since there is still some space between the two sides of the GOA unit and the edge of the display panel 10, disposing the gate start signal selection circuit 130 at this position avoids increasing the frame of the display panel 10.

Further, the gate start signal selection circuit 130 is disposed at a side of the gate driving unit 110 near a data line receiving signal. Since the display panel 10 needs to be connected to the source driving circuit 40 along the data line direction, a larger space is reserved, and placing the gate start signal selection circuit 130 at this position can bring more design margin, so that even if the area occupied by the gate start signal selection circuit 130 is larger due to a larger number of selection units 140 in the gate start signal selection circuit 130, the requirement can be satisfied.

Correspondingly, as shown in fig. 5, the present application further discloses a driving method of a gate driving circuit, which is used for driving the gate driving circuit, and specifically includes the steps of:

s1: a gate starting signal input end of a gate starting signal selection circuit in the gate driving circuit receives a gate starting signal;

s2: the grid starting signal selection circuit outputs the grid starting signal to a corresponding grid starting signal output end;

s3: and a gate driving unit in the gate driving circuit receives a gate start signal through a gate start signal line and drives a corresponding display area.

The grid driving unit drives the scanning lines in the display panel separately through the driving method, and all the scanning lines in the whole display panel do not need to be scanned line by line under special conditions such as screen clock display function, fingerprint identification pictures and the like, so that the power consumption is saved.

It should be noted that, the limitations of each step in the present disclosure are not considered to limit the order of the steps without affecting the implementation of the specific embodiments, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all the steps should be considered as belonging to the protection scope of the present application.

The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.

Claims

1. A gate driving circuit for driving scan lines in a display panel, the display panel being divided into at least two display regions along a data line direction in the display panel, the gate driving circuit comprising:

at least two grid driving units, wherein each grid driving unit drives the corresponding display area;

at least two grid starting signal lines which are connected with the grid driving units in a one-to-one corresponding mode;

the grid starting signal selection circuit comprises a grid starting signal input end and at least two grid starting signal output ends, wherein the grid starting signal input end receives a grid starting signal, and the grid starting signal output ends are connected with the grid starting signal lines in a one-to-one corresponding mode and output the grid starting signal; after receiving the gate start signal, the gate start signal selection circuit outputs the gate start signal to a corresponding gate start signal output end to drive a corresponding display area;

the grid starting signal selection circuit at least comprises a first selection unit, a second selection unit, a third selection unit and a fourth selection unit, wherein one end of the first selection unit, one end of the second selection unit, one end of the third selection unit and one end of the fourth selection unit are respectively connected with the grid starting signal input end, and the other ends of the first selection unit, the second selection unit, the third selection unit and the fourth selection unit are respectively connected with the grid starting signal output end in a one-to-one correspondence manner;

the first selection unit is composed of two N-type triodes, and bases of the two N-type triodes respectively receive a first time sequence signal and a second time sequence signal; the second selection unit is composed of an N-type triode and a P-type triode, and the N-type triode and the P-type triode respectively receive a first time sequence signal and a second time sequence signal; the third selection unit is composed of two P-type triodes, and bases of the two P-type triodes respectively receive a first timing signal and a second timing signal; the fourth selection unit is composed of a P-type triode and an N-type triode, and bases of the P-type triode and the N-type triode respectively receive the first timing signal and the second timing signal;

when the first time sequence signal and the second time sequence signal are both high level signals, the grid starting signal is output to the corresponding grid driving unit through the first selection unit;

when the first time sequence signal and the second time sequence signal are both low level signals, the gate start signal is output to the corresponding gate drive unit through the third selection unit;

when the first timing signal is a high-level signal and the second timing signal is a low-level signal, the gate start signal is output to the corresponding gate driving unit through the second selection unit;

and when the first timing signal is a low-level signal and the second timing signal is a high-level signal, the gate start signal is output to the corresponding gate driving unit through the fourth selection unit.

2. The gate driving circuit of claim 1, wherein the first switches in different ones of the selection units receive a first timing signal through a same first signal line, and the second switches in different ones of the selection units receive a second timing signal through a same second signal line.

3. The gate driving circuit of claim 1, wherein the gate start signal selection circuit is disposed at both sides of the gate driving unit in a direction of a data line in the display panel.

4. A gate driving circuit as claimed in claim 3, wherein the gate start signal selection circuit is disposed at a side of the gate driving unit near a data line of the display panel receiving a signal.

5. The gate driving circuit according to claim 1, wherein an output port of a previous one of the gate driving units connected to a last scanning line corresponding to the display region is communicated with an input port of a next one of the gate driving units in a data line direction in the display panel.

6. A driving method of a gate driving circuit for driving the gate driving circuit according to any one of claims 1 to 5, comprising the steps of:

7. A display panel comprising an array substrate and the gate driver circuit according to any one of claims 1 to 5, the gate driver circuit being connected to a scan line in the array substrate.