CN103915348A - Method for manufacturing graphene nanowire device - Google Patents
Method for manufacturing graphene nanowire device Download PDFInfo
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- CN103915348A CN103915348A CN201410157130.6A CN201410157130A CN103915348A CN 103915348 A CN103915348 A CN 103915348A CN 201410157130 A CN201410157130 A CN 201410157130A CN 103915348 A CN103915348 A CN 103915348A
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 89
- 229910021389 graphene Inorganic materials 0.000 title claims abstract description 85
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000002070 nanowire Substances 0.000 title abstract description 9
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000006911 nucleation Effects 0.000 claims description 4
- 238000010899 nucleation Methods 0.000 claims description 4
- 239000011241 protective layer Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 239000003153 chemical reaction reagent Substances 0.000 claims description 3
- 239000002245 particle Substances 0.000 claims description 3
- 239000007792 gaseous phase Substances 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 238000000231 atomic layer deposition Methods 0.000 abstract description 4
- 229910052799 carbon Inorganic materials 0.000 abstract description 4
- 241001424392 Lucia limbaria Species 0.000 abstract 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 125000000524 functional group Chemical group 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- -1 this Chemical compound 0.000 description 2
- 230000005355 Hall effect Effects 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 150000001721 carbon Chemical group 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 210000002421 cell wall Anatomy 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003599 detergent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004557 single molecule detection Methods 0.000 description 1
- 239000011232 storage material Substances 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention belongs to the technical field of carbon-based integrated circuit manufacturing, and particularly discloses a method for manufacturing a graphene nanowire device. The method includes the steps of etching a thin and long nanometer groove in a silicon dioxide substrate, and depositing a plurality of discontinuous small copper blocks in the groove through a mask plate, enabling the small copper blocks to serve as graphene coring sites, growing a layer of graphene nanowires in the groove through low-pressure chemical vapor deposition, growing high-K dielectric in the groove through atomic layer deposition to cover the graphene nanowires to form high-K gate dielectric of the device, and then manufacturing electrodes of the source, the drain and the gate of the device to form the graphene nanowire device. The method is simple, convenient to use and reliable, the ultra-long nanowires can be manufactured, the energy gap of the graphene nanowires is large, and the high-K gate dielectric can be formed on graphene through atomic layer deposition. The method can serve as a basic method for manufacturing the graphene nanowire device.
Description
Technical field
The invention belongs to carbon back ic manufacturing technology field, be specifically related to a kind of method of preparing graphene nano line device.
Background technology
In field of semiconductor manufacture, along with device size is more and more nearer apart from its physics limit, rear mole of epoch are entered.And the discovery of Graphene (Graphene) brings hope.The cellular two dimensional crystal that Graphene (Graphene) is made up of individual layer hexagonal cellular carbon atom, is the one deck in graphite, Figure 1 shows that the basic structure schematic diagram of Graphene.Graphene has the carrier mobility high more than silicon, Graphene has under room temperature electron mobility 200 000 cm2 ∕ Vs at a high speed, quantum hall effect, high theoretical specific area 2600 m2/g, also has high heat conductance 3000 W/mK and an outstanding mechanical property (high-modulus 1060GPa, high strength 130GPa), be considered to have wide practical use at aspects such as the quantum devices such as single-molecule detection device, integrated circuit, field-effect transistor, functional composite material, energy storage material, catalyst carriers.Two-dimensional structure based on Graphene uniqueness and physical characteristic, Graphene is considered to be expected to continue in integrated circuit of future generation the important materials of Moore's Law.
But the energy gap of desirable Graphene is 0, it has metallic character, and the state in conducting all the time cannot turn-off without any processing Graphene, so just cannot make switching device.Want to open the forbidden band of Graphene, can apply electric field for the Graphene of zero energy gap, adulterate or be prepared into the processing such as graphene nano line.Wherein be prepared into graphene nano line and can finely open Graphene forbidden band, nano wire is longer, and the energy gap of Graphene can be larger, can effectively reduce the leakage current of graphene device, prepares good graphene device.
The present invention etches an elongated nanometer groove in a silicon dioxide substrates, directly in groove, grows graphene nano line, does not need like this other processing, does not need through steps such as over etchings, just can directly obtain graphene nano line.Separately because Graphene surface does not have dangling bonds, chemical property torpescence, make by Atomic layer deposition method directly on Graphene deposit high K dielectric very difficult.So the present invention utilizes the nanometer well width of etching little, cell wall has silicon dioxide dangling bonds, can utilize ald long high K dielectric in next life, the whole nanometer groove of final covering, high K dielectric medium just covers on Graphene like this, form graphene device high-K gate dielectric, do not need like this Graphene itself that functional group or dangling bonds are provided, next life long high-K gate dielectric.This method can be protected the performance of Graphene well, and the impact that Graphene is caused is little, does not damage the lattice structure of Graphene.This is a kind of effective and novel method, will further promote the development of carbon back integrated circuit.
Summary of the invention
The object of the invention is to propose the preparation method of the graphene nano line device that a kind of preparation technology is simple, device performance is good.
Promote the development of graphene device, this device just has very large Graphene energy gap, and leakage current is little, little to Graphene infringement while forming high-K gate dielectric, the fine performance that graphene nano line device is provided.
The method of preparing graphene nano line device that the present invention proposes, concrete steps comprise:
(1) utilize mask plate, adopt chemical gaseous phase depositing process deposit one deck silicon nitride in silicon dioxide substrates as etching protective layer, then in silicon dioxide substrates, to etch an elongated nanometer groove;
(2) the some discontinuous copper fritters of deposit in nanometer groove, as Graphene nucleation site;
(3) utilize low-pressure chemical vapor deposition at one deck graphene nano line of growing in the nanometer groove of above-mentioned processing;
(4) utilize ald at the high K dielectric of growing in the nanometer groove of above-mentioned processing, cover on graphene nano line, form the high-K gate dielectric of device;
(5) then make the source electrode of device, the electrode of drain and gate, form graphene nano line device.
Further, the described silicon dioxide substrates that provides, first will pass through polishing, and clean, and removes surperficial impurity, particle, residual reagent, makes substrate surface clean, smooth smooth, does not stain.After handling, just can be on sample etching nanometer groove.When etching nanometer groove, need to utilize mask plate and chemical vapour deposition (CVD) deposit one deck silicon nitride on sample as etching protective layer, then to etch an elongated nanometer groove, then get rid of silicon nitride, had after nanometer groove, can be in groove cement copper fritter, discontinuous, so just not conducting; Then utilize copper as Graphene nucleation site, due to copper fritter very dense, can grow the continuous graphene nano line of one deck.In nanometer groove, fill high K dielectric (as aluminium oxide) as long as finally utilize ald, high K dielectric just directly covers on Graphene as gate medium, do not damage like this electric property of Graphene, reduce the defect on Graphene, thereby maintain as far as possible the performance such as high mobility of ideal graphite alkene.Because nanometer groove can do longly as far as possible, can make like this Graphene energy gap large as far as possible, improve the turn-off performance of graphene device, leakage current is little.
The present invention can direct growth go out graphene nano line, the processing steps such as etching are avoided, simplify technique, and the damage of minimizing to Graphene performance, the shape of the graphene nano line of direct growth can be controlled, by the design of mask plate, can etch the nanometer groove of various shapes, thereby grow the graphene nano line of various shapes.In the time of growth high-K gate dielectric, do not need Graphene Shang You functional group or dangling bonds, thereby cause defectiveness on Graphene.The high K dielectric of growth is that physics covers up completely, does not bring variation by the mode of chemical bond to the structure of Graphene, and that like this electric property of Graphene is caused affects minimum, thereby prepares the graphene nano line device of function admirable.This method is simple and convenient, reduce processing step, and the impact that Graphene is caused is little, does not destroy the lattice structure of Graphene.The method can be used as prepares a kind of basic skills of graphene nano line device.
Brief description of the drawings
Fig. 1 is the basic structural representation of Graphene.
Fig. 2 to Fig. 5 is the graphene nano line device process schematic diagram of preparing provided by the invention.
Fig. 6 is operational flowchart of the present invention.
Embodiment
The present invention utilizes etching nanometer groove on substrate, thereby direct growth goes out needed overlength graphene nano line in groove.Then utilize the dangling bonds of the silicon dioxide of nanometer groove sidewall, use the method growth high K dielectric of ald, with high K dielectric filling nanometer groove, thereby high K dielectric physics is covered on Graphene, form the high-K gate dielectric of Graphene, reduce like this damage to Graphene.The following stated be to adopt the proposed by the invention embodiment for preparing graphene nano line device.
In the drawings, for convenience of description, structure size and ratio do not represent actual size.
First, provide silicon dioxide (SiO
2) film sample 101, sample is cleaned, remove some magazines at sample surfaces, particle, residual reagent etc., make very neat and tidy of Graphene silica sample.As shown in Figure 2.
Then carry out etching, first utilize mask plate and chemical vapour deposition (CVD) deposit one deck silicon nitride on sample as etching protective layer, then to etch the nanometer groove of an overlength, the length, width and height of groove are 5000 × 100 × 100nm
3, then get rid of silicon nitride, form nanometer groove 102, as shown in Figure 3.
Next, utilize the many copper fritters of method deposit in nanometer groove of physical vapour deposition (PVD) or ald, as Graphene nucleation site, copper fritter is discontinuous, is distributed in nanometer trench bottom, has so abundant copper sheet 103, and its vertical view as shown in Figure 4.
Next, sample is put into the reacting furnace of low-pressure chemical vapor deposition, opened reacting furnace.Pass into argon gas, dispose the air in reacting furnace, then pass into hydrogen 5sccm and 500sccm argon gas, heating reaction furnace, treats that temperature rise, to 1000 degree, closes argon gas, opens methane 10sccm, hydrogen 10sccm reaction 5 minutes.Cooling fast, finally treat that sample is cooled to normal temperature, take out sample.Grow graphene nano 104, as shown in Figure 5.
Next, fill nanometer groove by the means of ald, on graphene nano line, cover high K dielectric aluminium oxide.Concrete steps are, reaction temperature is set is 110 DEG C and heat reaction chamber, and sample is put into ALD reaction chamber, in the time that temperature reaches design temperature, selects trimethyl aluminium and water as reaction source, sets number reaction time, starts to carry out ald.After reaction finishes, close source, detergent line, takes out sample, forms high K dielectric aluminium oxide.The last electrode that just can prepare source electrode, drain and gate, forms device.
As mentioned above, in the situation that not departing from spirit and scope of the invention, can also form many embodiment that have very big difference.The invention is not restricted at the specific embodiment described in specification.
Claims (2)
1. prepare a method for graphene nano line device, it is characterized in that concrete steps are:
(1) utilize mask plate, adopt chemical gaseous phase depositing process deposit one deck silicon nitride in silicon dioxide substrates as etching protective layer, then in silicon dioxide substrates, to etch an elongated nanometer groove;
(2) the some discontinuous copper fritters of deposit in nanometer groove, as Graphene nucleation site;
(3) utilize low-pressure chemical vapor deposition at one deck graphene nano line of growing in the nanometer groove of above-mentioned processing;
(4) utilize ald at the high K dielectric of growing in the nanometer groove of above-mentioned processing, cover on graphene nano line, form the high-K gate dielectric of device;
(5) then make the source electrode of device, the electrode of drain and gate, form graphene nano line device.
2. method according to claim 1, is characterized in that described silicon dioxide liner basal surface first will pass through polishing, and cleans, and removes surperficial impurity, particle, residual reagent, makes substrate surface clean, smooth smooth, does not stain.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410157130.6A CN103915348B (en) | 2014-04-19 | 2014-04-19 | A kind of method preparing graphene nano line device |
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| CN103915348A true CN103915348A (en) | 2014-07-09 |
| CN103915348B CN103915348B (en) | 2016-09-28 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106531613A (en) * | 2016-04-22 | 2017-03-22 | 中国科学院微电子研究所 | Modifying and processing method and device for selected area on graphene surface |
| WO2018094806A1 (en) * | 2016-11-22 | 2018-05-31 | 武汉华星光电技术有限公司 | Manufacturing method of micro- or nano-structured anti-reflective coating, and display device |
| CN111129113A (en) * | 2019-12-24 | 2020-05-08 | 中国科学院上海微***与信息技术研究所 | Graphene nanoribbon device array and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102683217A (en) * | 2012-05-24 | 2012-09-19 | 中国科学院上海微***与信息技术研究所 | Preparation method of graphite-based double-gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) |
| US20130337618A1 (en) * | 2011-10-03 | 2013-12-19 | International Business Machines Corporation | Transistor device with reduced gate resistance |
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- 2014-04-19 CN CN201410157130.6A patent/CN103915348B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130337618A1 (en) * | 2011-10-03 | 2013-12-19 | International Business Machines Corporation | Transistor device with reduced gate resistance |
| CN102683217A (en) * | 2012-05-24 | 2012-09-19 | 中国科学院上海微***与信息技术研究所 | Preparation method of graphite-based double-gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) |
Non-Patent Citations (1)
| Title |
|---|
| 袁小亚: ""石墨烯的制备研究进展"", 《无机材料学报》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106531613A (en) * | 2016-04-22 | 2017-03-22 | 中国科学院微电子研究所 | Modifying and processing method and device for selected area on graphene surface |
| CN106531613B (en) * | 2016-04-22 | 2020-07-17 | 中国科学院微电子研究所 | Selective modification processing method and device for graphene surface |
| WO2018094806A1 (en) * | 2016-11-22 | 2018-05-31 | 武汉华星光电技术有限公司 | Manufacturing method of micro- or nano-structured anti-reflective coating, and display device |
| CN111129113A (en) * | 2019-12-24 | 2020-05-08 | 中国科学院上海微***与信息技术研究所 | Graphene nanoribbon device array and preparation method thereof |
| CN111129113B (en) * | 2019-12-24 | 2021-06-25 | 中国科学院上海微***与信息技术研究所 | Graphene nanoribbon device array and preparation method thereof |
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