CN103915341A - 晶体管及其形成方法 - Google Patents
晶体管及其形成方法 Download PDFInfo
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- CN103915341A CN103915341A CN201310006384.3A CN201310006384A CN103915341A CN 103915341 A CN103915341 A CN 103915341A CN 201310006384 A CN201310006384 A CN 201310006384A CN 103915341 A CN103915341 A CN 103915341A
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- Prior art keywords
- side wall
- silicon nitride
- nitride layer
- per minute
- semiconductor substrate
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- 238000000034 method Methods 0.000 title claims abstract description 69
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 153
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 152
- 239000004065 semiconductor Substances 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 239000002184 metal Substances 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 30
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 23
- 230000015572 biosynthetic process Effects 0.000 claims description 59
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 46
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 36
- 229910052799 carbon Inorganic materials 0.000 claims description 36
- 239000000126 substance Substances 0.000 claims description 31
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 23
- 238000006243 chemical reaction Methods 0.000 claims description 21
- 238000005137 deposition process Methods 0.000 claims description 21
- 229910052796 boron Inorganic materials 0.000 claims description 18
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 15
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 239
- 239000000463 material Substances 0.000 description 38
- 239000000243 solution Substances 0.000 description 26
- 150000002500 ions Chemical class 0.000 description 18
- 238000005516 engineering process Methods 0.000 description 17
- 238000000151 deposition Methods 0.000 description 16
- 230000008021 deposition Effects 0.000 description 15
- 125000006850 spacer group Chemical group 0.000 description 13
- 230000006835 compression Effects 0.000 description 10
- 238000007906 compression Methods 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 239000007789 gas Substances 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 238000000137 annealing Methods 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 5
- 239000002210 silicon-based material Substances 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 125000004122 cyclic group Chemical group 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- -1 boron ion Chemical class 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004219 SiNi Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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Abstract
一种晶体管及其形成方法,所述晶体管的形成方法包括:提供半导体衬底,所述半导体衬底内具有隔离结构,在所述隔离结构两侧的半导体衬底表面上具有栅极结构,所述栅极结构包括位于半导体衬底表面的栅介质层和位于所述栅介质层表面的栅极;在所述栅极结构两侧形成第一侧墙,所述第一侧墙为掺杂的氮化硅层;在所述第一侧墙表面形成第二侧墙,所述第二侧墙的刻蚀速率大于第一侧墙的刻蚀速率;在所述栅极结构两侧的半导体衬底内形成源极和漏极;在所述源极、漏极表面形成金属硅化物层;去除所述第二侧墙;在所述半导体衬底表面形成应力层。所述晶体管的形成方法能够降低晶体管栅极结构两侧的寄生电容,提高晶体管沟道区域受到的应力。
Description
技术领域
本发明涉及半导体技术领域,特别涉及一种晶体管及其形成方法。
背景技术
随着半导体制造技术的飞速发展,半导体器件为了达到更快的运算速度、更大的资料存储量以及更多的功能,半导体芯片向更高集成度方向发展。而半导体芯片的集成度越高,半导体器件的特征尺寸(CD,Critical Dimension)越小。目前,半导体器件的特征尺寸逐步缩小,在制造半导体器件时需要用到应力应变技术(stress strain technology),例如应力近接技术(stress proximatetechnology,SPT)。
图1至图2为现有技术中采用应力近接技术的晶体管的制造方法的剖面结构示意图。
请参考图1,提供基底10,在所述基底10表面形成栅极结构,所述栅极结构包括位于基底10表面的栅介质层11和位于所述栅介质层表面的栅极12。
对栅极结构两侧的基底10进行轻掺杂离子注入,在基底10中形成轻掺杂源区和轻掺杂漏区(图中未标号)。
在所述栅极12两侧依次形成氮化硅阻挡侧墙131、覆盖所述氮化硅阻挡侧墙的氧化硅侧墙132和覆盖所述氧化硅侧墙132的氮化硅侧墙133。所述氮化硅阻挡侧墙131可以限定源区、漏区和沟道区域之间的距离,防止短沟道效应;氮化硅侧墙133用于控制源漏上的金属硅化物层与栅极之间的距离;氧化硅侧墙132则作为后续去除所述氮化硅侧墙133的刻蚀阻挡层。
对栅极结构两侧的基底10进行重掺杂离子注入,形成源区141和漏区142,再在所述源区141、漏区142表面形成金属硅化物层15。
请参考图2,选择性去除所述氮化硅侧墙133(如图1所示),形成覆盖所述栅极结构以及氧化硅侧墙132的应力层16。去除所述氮化硅侧墙133可以减小应力层16与沟道区域之间的距离。
现有技术中,需要在栅极结构两侧形成三层侧墙,工艺步骤复杂,成本较高。并且在最后形成的应力层和栅极结构之间仍然具有氧化硅侧墙132和氮化硅阻挡侧墙131,所述氧化硅侧墙132仍旧会降低应力层16对沟道区域的应力效果。如果要去除所述氧化硅侧墙,还需要多一步刻蚀工艺,增加工艺步骤。并且所述栅极两侧的氮化硅阻挡侧墙131的介电常数较高,使得形成的晶体管的栅极结构周围的寄生电容较高,影响晶体管的性能。
更多关于晶体管的形成方法的技术,请参考专利公开号为US2007/0072402A1的美国专利。
发明内容
本发明解决的问题是提供一种晶体管及其形成方法,所述晶体管的形成方法可以提高所述晶体管沟道区域受到的应力大小,并且降低晶体管栅极结构周围的寄生电容。
为解决上述问题,本发明的技术方案提出了一种晶体管的形成方法,包括:提供半导体衬底,所述半导体衬底内具有隔离结构,在所述隔离结构两侧的半导体衬底表面上具有栅极结构,所述栅极结构包括位于半导体衬底表面的栅介质层和位于所述栅介质层表面的栅极;在所述栅极结构两侧形成第一侧墙,所述第一侧墙为掺杂的氮化硅层;在所述第一侧墙表面形成第二侧墙,所述第二侧墙覆盖第一侧墙,所述第二侧墙的刻蚀速率大于第一侧墙的刻蚀速率;在所述栅极结构两侧的半导体衬底内形成源极和漏极;在所述源极、漏极表面形成金属硅化物层;去除所述第二侧墙;在所述半导体衬底表面形成应力层,所述应力层覆盖半导体衬底表面、金属硅化物层表面、栅极的表面,以及第一侧墙的表面。
可选的,所述第一侧墙的掺杂元素为碳或硼,所述掺杂元素的摩尔浓度为3%~30%。
可选的,所述第二侧墙和第一侧墙的刻蚀选择比为4:1~27:1。
可选的,所述第一侧墙的形成工艺为化学气相沉积工艺或原子层沉积工艺,所述第二侧墙的形成工艺为化学气相沉积工艺或原子层沉积工艺。
可选的,所述第一侧墙的厚度范围为2纳米~10纳米,所述第一侧墙在磷酸溶液中的刻蚀速率小于5纳米每分钟。
可选的,所述第一侧墙的形成方法为:采用SiH2Cl2、NH3和C2H4作为反应气体,所述反应的温度范围为450℃~650℃,其中SiH2Cl2的流量为0.1标况升每分~5标况升每分,NH3的流量为0.2标况升每分~5标况升每分,C2H4的流量为0.1~5标况升每分,最终形成的第一侧墙内碳的浓度范围为1E21个原子每立方厘米~5E22个原子每立方厘米。
可选的,所述第一侧墙为多层堆叠结构,所述多层堆叠结构包括互相堆叠的氮化硅层和掺杂氮化硅层,所述第一侧墙内的氮化硅层和掺杂氮化硅层的厚度比为1:2~1:50。
可选的,所述第一侧墙的多层堆叠结构采用循环沉积工艺形成。
可选的,所述第一侧墙内的氮化硅层的形成方法为原子层沉积工艺,采用SiH2Cl2和NH3作为反应气体,其中SiH2Cl2的流量为0.2标况升每分~5标况升每分,NH3的流量为0.5标况升每分~10标况升每分,反应温度为450℃~650℃,反应压强为0.02托~1托;所述第一侧墙内的掺杂氮化硅层的形成方法为原子层沉积工艺,采用SiH2Cl2、NH3和C2H4作为反应气体,其中SiH2Cl2的流量为0.2标况升每分~5标况升每分,NH3的流量为0.5标况升每分~10标况升每分,C2H4的流量为0.2标况升每分~5标况升每分,反应温度为450℃~650℃,反应压强为0.02托~1托。
可选的,所述第二侧墙为氮化硅层。
可选的,所述第二侧墙为多层堆叠结构,所述多层堆叠结构包括互相堆叠的氮化硅层和掺杂氮化硅层,所述第二侧墙内的氮化硅层和掺杂氮化硅层的厚度比为2:1~50:1。
可选的,所述第二侧墙中掺杂氮化硅层的掺杂元素为碳或硼,第二侧墙中杂元素的摩尔浓度为0.5%~3%。
可选的,所述第二侧墙的多层堆叠结构采用循环沉积工艺形成。
可选的,去除所述第二侧墙的方法为:采用磷酸溶液作为刻蚀溶液,所述磷酸溶液的温度范围为120℃~165℃,刻蚀时间为1分钟~65分钟。
为解决上述问题,本发明还提供了一种采用上述方法形成的晶体管,所述晶体管包括:半导体衬底;位于所述半导体衬底上的隔离结构和栅极结构,所述栅极结构包括位于半导体衬底表面的栅介质层和位于所述栅介质层表面的栅极;位于所述栅极结构两侧的第一侧墙,所述第一侧墙为掺杂的氮化硅层;位于所述栅极结构两侧的半导体衬底内的源极和漏极;位于所述源极、漏极表面的金属硅化物层;位于半导体衬底表面的应力层,所述应力层覆盖所述源极、漏极、金属硅化物层、栅极以及第一侧墙的表面。
可选的,所述第一侧墙的掺杂元素为碳或硼,所述掺杂元素的摩尔浓度为3%~30%。
可选的,所述第一侧墙中掺杂元素的浓度范围为1E21个原子每立方厘米~5E22个原子每立方厘米。
可选的,所述第一侧墙的厚度范围为2纳米~10纳米。
可选的,所述第一侧墙在磷酸溶液中的刻蚀速率小于5纳米每分钟。
可选的,所述第一侧墙为多层堆叠结构,所述多层堆叠结构包括互相堆叠的氮化硅层和掺杂氮化硅层,其中,氮化硅层和掺杂氮化硅层的厚度比为1:2~1:50。
与现有技术相比,本发明具有以下优点:
本发明的技术方案,在晶体管的栅极结构侧壁形成第一侧墙之后,直接在所述第一侧墙表面形成第二侧墙,然后在形成源极、漏极以及源极、漏极表面的金属硅化物层之后去除所述第二侧墙,再在形成覆盖所述晶体管的应力层。由于第二侧墙的刻蚀速大于第一侧墙的刻蚀速率,所以第一侧墙既作为栅极结构的保护侧墙,又作为刻蚀第二侧墙的刻蚀阻挡层。与现有技术相比,晶体管的栅极结构与应力层之间只具有一层第一侧墙,所述应力层与沟道的距离较短,能够有效提高所述沟道区域受到的应力大小。
进一步的,所述第一侧墙的材料是掺杂的氮化硅层,所述第一侧墙在磷酸溶液中的刻蚀速率较低,并且所述刻蚀速率与掺杂浓度成反比,可以通过调节掺杂浓度调节刻蚀速率。与纯的氮化硅层相比,所述第一侧墙的介电常数下降,能够有效降低所述栅极结构周边的寄生电容值。并且所述第一侧墙采用掺杂的氮化硅层还可以阻挡第一侧墙下方的轻掺杂源漏扩展区的掺杂离子向外扩散,从而减少掺杂离子的损失,降低电阻率。
进一步的,所述第一侧墙可以是氮化硅层和掺杂氮化硅层的多层堆叠结构,可以通过调节掺杂氮化硅层和氮化硅层的厚度比例来调节所述第一侧墙内掺杂元素的浓度,从而调节第一侧墙的刻蚀速率以及第一侧墙的介电常数。
进一步的,所述第二侧墙的材料可以是氮化硅层和掺杂氮化硅层的多层堆叠结构,其中掺杂元素的浓度较低,使第二侧墙在磷酸溶液中的刻蚀速率较高。与纯的氮化硅层相比,所述掺低含量碳的氮化硅层可以阻止晶体管的轻掺杂源漏扩展区的掺杂离子,例如硼、磷等向外面扩散,从而减少掺杂离子的损失,降低电阻率。所述第二侧墙可以通过调节掺杂氮化硅层和氮化硅层的厚度比例来调节所述第二侧墙的刻蚀速率以及所述第二侧墙的对轻掺杂源漏扩展区内的掺杂离子的阻挡效果。
进一步的,由于只需要在栅极结构两侧形成两层侧墙,与现有技术形成三层侧墙相比,栅极结构两侧的侧墙厚度下降。在相邻栅极结构之间距离相同的情况下,由于侧墙厚度下降,使得形成侧墙之后的栅极结构之间的间距增加,降低了栅极结构两侧沟槽的深宽比,降低了在沟槽内进行外延沉积的难度,防止在沉积过程中产生空洞等缺陷,提高后续形成金属硅化物的工艺中沉积的金属层的质量,以及提高后续沉积形成的应力层的质量。
附图说明
图1至图2是本发明的现有技术中形成晶体管的剖面示意图;
图3至图9是本发明的实施例中晶体管的形成过程的剖面示意图。
具体实施方式
如背景技术中所述,现有技术中形成晶体管的方法需要在晶体管的栅极结构两侧形成三层侧墙,步骤复杂,并且工艺成本较高。并且所述氮化硅侧墙的介电常数较高,使得形成的晶体管的栅极结构周围的寄生电容较高,影响晶体管的性能。
本发明提出的晶体管的形成方法,在栅极结构两侧形成第一侧墙和第二侧墙,所述第一侧墙为掺杂的氮化硅层,再形成源极和漏极以及源极和漏极表面的金属硅化物层,然后去除第二侧墙,形成应力层。去除第二侧墙可以降低应力层与晶体管沟道区域之间的距离,提高所述应力层对晶体管的应力作用,并且所述第一侧墙的介电常数较底,能够降低晶体管栅极结构周围的寄生电容。
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施方式做详细的说明。所描述的实施例仅仅是本发明的可实施方式的一部分,而不是其全部。在详述本发明实施例时,为便于说明,示意图会不依一般比例作局部放大,而且所述示意图只是示例,其在此不应限制本发明的保护范围。此外,在实际制作中应包含长度、宽度及深度的三维空间尺寸。根据所述实施例,本领域的普通技术人员在无需创造性劳动的前提下可获得的所有其它实施方式,都属于本发明的保护范围。因此本发明不受下面公开的具体实施的限制。
请参考图3,提供半导体衬底100,所述半导体衬底100内具有隔离结构101,在所述隔离结构101两侧的半导体衬底100表面具有栅极结构200,所述栅极结构200包括位于半导体衬底表面的栅介质层201和位于所述栅介质层201表面的栅极202。
所述半导体衬底100的材料包括硅、锗、锗化硅、砷化镓等半导体材料,可以是体材料,也可以是复合结构如绝缘体上硅。本领域的技术人员可以根据半导体衬底100上形成的半导体器件选择所述半导体衬底100的类型,因此所述半导体衬底的类型不应限制本发明的保护范围。本发明的实施例中,所述半导体衬底100为硅衬底。
在本实施例中,所述半导体衬底100内的隔离结构101为浅沟槽隔离结构(STI,shallow trench isolation),但所述隔离结构101不限于浅沟槽隔离结构,也可以为本领域技术人员公知的其他隔离结构。所述隔离结构101的形成方法为:在所述半导体衬100内形成沟槽(未标示),然后通过热氧化法在沟槽内壁形成垫氧化层(图中未示出),然后再在所述沟槽内填充满二氧化硅,形成浅沟槽隔离结构101。
在所述隔离结构101两侧的半导体衬底100表面具有栅极结构200,所述栅极结构200包括位于半导体衬底表面的栅介质层201和位于所述栅介质层201表面的栅极202。所述栅介质层201的材料为氧化硅、氮氧化硅或高k介质材料以及其他本领域技术人员公知的材料。所述栅极202的材料为多晶硅、金属或者本领域技术人员公知的其他材料,其中金属可以为如Ti、Co、Ni、Al、W等。本实施例中,所述栅极202的材料为金属。在本发明的其他实施例中,所述栅极202和栅介质层201之间还可以形成有功函数调整层或扩散阻挡层。
在本发明的其他实施例中,还可以对栅极结构两侧的半导体衬底100内进行轻掺杂离子注入,形成轻掺杂源漏扩展区。
请参考图4,在所述栅极结构200两侧形成第一侧墙203,所述第一侧墙203覆盖栅极结构200的侧壁。
具体的,所述第一侧墙203的材料为掺杂的氮化硅层,所述第一侧墙203的厚度为2nm~10nm,所述第一侧墙203的掺杂元素可以是碳或硼,并且第一侧墙203内的掺杂元素的摩尔浓度为3%~30%。所述第一侧墙203的形成工艺为化学气相沉积或原子层沉积工艺。
本实施例中,所述第一侧墙203的材料为掺碳的氮化硅层,所述第一侧墙203采用的形成工艺为化学气相沉积工艺,包括:采用SiH2Cl2、NH3和C2H4作为反应气体,所述反应的温度范围为450℃~650℃,其中SiH2Cl2的流量为0.1标况升每分~5标况升每分,NH3的流量为0.2标况升每分~5标况升每分,C2H4的流量为0.1~5标况升每分,最终形成的第一侧墙203内碳的浓度范围为1E21个原子每立方厘米~5E22个原子每立方厘米。所述第一侧墙203与未掺杂的氮化硅层相比,在磷酸溶液或者氢氟酸溶液中的刻蚀速率较低,所述第一侧墙203在磷酸中的刻蚀速率小于10纳米每分钟,可以是0.1纳米每分钟~5纳米每分钟。
在本发明的其他实施例中,所述第一侧墙203还可以是多层堆叠结构,所述多层堆叠结构包括多层互相堆叠的氮化硅层和掺杂氮化硅层,所述掺杂氮化硅层的掺杂元素可以是碳或硼。所述第一侧墙203采用循环沉积工艺形成,依次形成氮化硅层、掺杂氮化硅层,并重复所述沉积形成多层堆叠结构。所述第一侧墙203内的氮化硅层和掺杂氮化硅层的厚度比为1:2~1:50。
在本发明的一个实施例中,所述第一侧墙203包括多层堆叠的氮化硅层和掺碳氮化硅层,所述第一侧墙203内的氮化硅层的形成工艺为原子层沉积工艺,包括:采用SiH2Cl2和NH3作为反应气体,其中SiH2Cl2的流量为0.2标况升每分~5标况升每分,NH3的流量为0.5标况升每分~10标况升每分,反应温度为450℃~650℃,反应压强为0.02托~1托。所述第一侧墙203内的掺碳氮化硅层的形成方法为原子层沉积工艺,采用SiH2Cl2、NH3和C2H4作为反应气体,其中SiH2Cl2的流量为0.2标况升每分~5标况升每分,NH3的流量为0.5标况升每分~10标况升每分,C2H4的流量为0.2标况升每分~5标况升每分,反应温度为450℃~650℃,反应压强为0.02托~1托。
在本发明的一个实施例中,所述第一侧墙203的厚度为5nm,首先在半导体衬底100表面、栅极结构200侧壁和顶部形成一层厚度为的氮化硅层,然后在氮化硅层表面形成一层厚度为掺碳氮化硅层,然后依次循环所述氮化硅层和掺碳氮化硅层的沉积,共循环10次,形成厚度为5nm第一侧墙材料层,然后刻蚀所述第一侧墙材料层,形成第一侧墙203。
在本发明的其他实施例中,也可以是先沉积形成的掺碳氮化硅层再形成的氮化硅层,然后依次循环沉积所述掺碳氮化硅层和氮化硅层的,共循环10次,形成厚度为5nm第一侧墙材料层,然后刻蚀所述第一侧墙材料层,形成第一侧墙203。
所述第一侧墙203内的氮化硅层和掺杂氮化硅层的厚度都很小,并且互相堆叠,相当于将掺杂氮化硅层均匀分散在氮化硅层中。可以通过控制沉积时间以及循环沉积的次数来调整其中氮化硅层与掺杂氮化硅层的厚度比例,从而调节第一侧墙203中掺杂元素的浓度,调整第一侧墙203的刻蚀速率和介电常数。而单层结构的掺杂的氮化硅层只能通过调整沉积反应物的浓度来调节掺杂元素的浓度,所以采用多层堆叠的结构对掺杂元素浓度调节的准确度更高更为方便。
所述第一侧墙203作为后续刻蚀第二侧墙的刻蚀阻挡层,并且第一侧墙203中由于掺杂了碳或硼等元素,与未掺杂的氮化硅层相比,介电常数明显下降,可以降低所述晶体管栅极结构周围的寄生电容。同时第一侧墙203还限定了源漏区域和沟道区域之间的距离,防止产生短沟道效应。如果在形成第一侧墙203之前对栅极结构200两侧的半导体衬底100进行了轻掺杂离子注入,形成了轻掺杂源漏扩展区,第一侧墙203位于所述轻掺杂源漏扩展区上方,与未掺杂的氮化硅层相比,所述第一侧墙203还可以阻挡第一侧墙203下方的轻掺杂源漏扩展区的掺杂离子,例如硼离子,向外扩散,从而减少掺杂离子的损失,降低源漏区域的电阻。
请参考图5,在所述第一侧墙203表面形成第二侧墙204,所述第二侧墙204覆盖所述第一侧墙203。
具体的,所述第二侧墙204的刻蚀速率大于第一侧墙203的刻蚀速率,第二侧墙204和第一侧墙203的刻蚀选择比为4~27。所述第二侧墙204的厚度为5nm~30nm。所述第二侧墙204的形成工艺包括化学气相沉积或原子层沉积工艺。
本实施例中,所述第二侧墙204的材料为氮化硅,形成方法包括:采用SiH2Cl2和NH3作为反应气体,其中SiH2Cl2的流量为0.2标况升每分~5标况升每分,NH3的流量为0.5标况升每分~10标况升每分,反应温度为450℃~650℃,反应压强为0.02托~1托。
在本发明的其他实施例中,所述第二侧墙204还可以是掺低含量杂质的氮化硅层,所述掺杂元素为碳或硼,掺杂元素的摩尔浓度为0.5%~3%。所述掺低含量杂质的氮化硅层在磷酸溶液中的刻蚀速率大于第一侧墙203在磷酸溶液中的刻蚀速率。所述低含量杂质的氮化硅层可以是多层堆叠结构,所述多层堆叠结构包括多层互相堆叠的氮化硅层和掺杂氮化硅层。
本发明的一个实施例中,所述第二侧墙204包括多层互相堆叠的氮化硅层和掺碳氮化硅层。所述第二侧墙204采用循环沉积工艺形成,依次形成氮化硅层、掺碳氮化硅层,并重复所述沉积形成多层堆叠结构。所述第二侧墙204内的氮化硅层和掺碳氮化硅层的厚度比为2:1~50:1。具体的,所述第二侧墙204内的氮化硅层的形成工艺为原子层沉积工艺,包括:采用SiH2Cl2和NH3作为反应气体,其中SiH2Cl2的流量为0.2标况升每分~5标况升每分,NH3的流量为0.5标况升每分~10标况升每分,反应温度为450℃~650℃,反应压强为0.02托~1托。所述第二侧墙204内的掺碳氮化硅层的形成方法为原子层沉积工艺,采用SiH2Cl2、NH3和C2H4作为反应气体,其中SiH2Cl2的流量为0.2标况升每分~5标况升每分,NH3的流量为0.5标况升每分~10标况升每分,C2H4的流量为0.2标况升每分~5标况升每分,反应温度为450℃~650℃,反应压强为0.02托~1托。
在本发明的一个实施例中,所述第二侧墙204的厚度为15nm,首先在半导体衬底100表面、第一侧墙203表面和栅极202顶部沉积一层厚度为的氮化硅层,然后在氮化硅层表面形成一层厚度为掺碳氮化硅层,然后依次循环所述氮化硅层和掺碳氮化硅层的沉积,共循环15次,形成厚度为15nm的第二侧墙材料层,然后刻蚀所述第二侧墙材料层,形成第二侧墙204。在本发明的其他实施例中,也可以是先沉积形成的掺碳氮化硅层,再形成的氮化硅层,然后依次循环沉积所述掺碳氮化硅层和氮化硅层的,共循环15次,形成厚度为15nm第二侧墙材料层,然后刻蚀所述第二侧墙材料层,形成第二侧墙204。
采用所述多层堆叠结构的第二侧墙204能够通过调整循环沉积的循环次数以及沉积的时间来调节其中氮化硅层与掺杂氮化硅层的厚度比例,从而调节其中掺杂元素的浓度,与单层结构的掺杂的氮化硅层相比,可以获得更低的掺杂浓度,使第二侧墙204在磷酸溶液中具有较高的刻蚀速率。并且还可以通过调节掺杂氮化硅层和氮化硅层的厚度比例来调节第二侧墙204对位于其下方的源漏扩展区域的掺杂离子的阻挡效果,防止源漏扩展区域的离子向外扩散。
所述第二侧墙204和第一侧墙203的刻蚀选择比为4~27,后续采用湿法刻蚀工艺去除第二侧墙204时,第一侧墙203的刻蚀速率小于第二侧墙204的刻蚀速率。所以在后续去除所述第二侧墙204的时候,所述第一侧墙203可以作为刻蚀阻挡层保护所述栅极结构200。
所述第二侧墙204,一方面用来定义后续形成源极和漏极的位置,另一方面,可以通过第二侧墙204的厚度来控制后续在源极和漏极表面形成的金属硅化物层与栅极之间的距离,防止栅极202和源漏表面的金属硅化物层之间产生漏电。与未掺杂的氮化硅层相比,第二侧墙204采用掺低含量杂质的氮化硅层可以阻止晶体管的轻掺杂源漏扩展区的掺杂离子,例如硼离子,向外扩散,从而减少掺杂离子的损失,降低电阻率。
在本发明的其他实施例中,也可以先在所述半导体衬底100表面、栅极结构200的表面形成第一侧墙材料层,然后形成覆盖所述第一侧墙材料层的第二侧墙材料层,再对所述第一侧墙材料层和第二侧墙材料层进行刻蚀,同时形成第一侧墙203和第二侧墙204。
请参考图6,在所述栅极结构200两侧的半导体衬底100内形成源极102和漏极103。
具体的,本实施例中,所述源极102和漏极103的形成方法为:以所述栅极结构200、第一侧墙203、第二侧墙204为掩膜,对所述第二侧墙204和隔离结构101之间暴露的半导体衬底100区域进行P型或N型离子注入,并进行退火处理,形成源极102和漏极103。
在本发明的其他实施例中,也可以在形成所述第一侧墙和第二侧墙之前,在所述栅极结构200两侧的有源区内进行轻掺杂离子注入,在形成所述第一侧墙203、第二侧墙204后,再在所述第一侧墙203、第二侧墙204两侧暴露出的半导体衬底100内进行重掺杂离子注入,形成源极和漏极,所述轻掺杂离子注入工艺可以降低MOS晶体管的热载流子注入效应和短沟道效应。该实施例中,第一侧墙203和第二侧墙204下方半导体衬底100内具有轻掺杂源漏扩展区域,后续形成的第一侧墙203和第二侧墙204可以阻止所述轻掺杂源漏扩展区域内的掺杂离子向外扩散。
在本发明的其他实施例中,还可以以所述栅极结构200、第一侧墙203、第二侧墙204为掩膜,对所述第二侧墙204和隔离结构101之间暴露出的半导体衬底100进行刻蚀,形成沟槽,并在沟槽内利用外延工艺填充满锗硅材料或碳化硅材料,形成源极102和漏极103。所述锗硅材料或碳化硅材料在外延工艺中原位掺杂有P型或N型杂质离子。在其他实施例中,也可以在形成所述锗硅材料或碳化硅材料后,利用离子注入工艺在所述锗硅材料或碳化硅材料中掺杂有杂质离子。利用所述锗硅材料或碳化硅材料形成源极和漏极会对MOS晶体管沟道区的晶格产生应力作用,有利于提高沟道区载流子的迁移速率,提高MOS晶体管的电学性能。
请参考图7,在所述源极102、漏极103表面形成金属硅化物层301。
本发明的实施例中,采用两步硅化的工艺。首先,采用蒸发或溅射工艺在源极102、漏极103、栅极202以及隔离结构表面形成Ni金属层,然后采用炉管或快速退火设备,在高纯的氮气环境中,低温快速退火,所述退火温度为250℃~350℃,例如退火温度为260℃,持续时间30秒,形成富镍相硅化物;随后,采用湿法刻蚀的方法,去除多余的Ni金属层;最后,采用高温快速退火,所述退火温度为380℃~550℃,例如退火温度为500℃,持续时间30秒,使富镍相硅化物发生相变,形成硅化物层301。
在本发明的其他实施例中,还可以采用一步硅化工艺:首先采用蒸发或者溅射工艺,在源极102、漏极103、栅极202以及隔离结构表面Ni金属层;采用炉管或者快速退火设备,在高纯度的氮气环境下高温快速退火,形成镍硅化物;最后,采用湿法刻蚀方法,去除多余的Ni,形成硅化物层301。
本发明的其他实施例中,所述金属层的材料还可以是包括Ni、Ta、Ti、W、Co、Pt或Pd中的一种或一种以上的金属,所述形成的金属硅化物层301的材料可以是SiNi、SiTa、SiTi或NiSiPt等本技术领域的技术人员公知的金属硅化物材料。形成所述金属硅化物层301可以降低所述源极102、漏极103表面的接触电阻。
由于本实施例中,采用的栅极材料为金属,所述在栅极202表面不会形成金属硅化物层;在本发明的其他实施例中,如果所述栅极202采用的材料是多晶硅,则在所述多晶硅栅极表面也会形成金属硅化物层。
请参考图8,去除所述第二侧墙204(请参考图7)。
本实施例中,采用湿法刻蚀工艺去除所述第二侧墙204。所述湿法刻蚀工艺的刻蚀溶液为磷酸溶液,所述磷酸溶液的温度范围为120℃~165℃,刻蚀时间为1min~65min。
表1为本实施例的第一侧墙203采用的掺杂的氮化硅层与和第二侧墙204采用的氮化硅层、和现有技术中采用的氧化硅层在49%氢氟酸以及磷酸溶液中的刻蚀速率表。
表1刻蚀速率表
薄膜类型 | 300:1的稀氢氟酸溶液 | 磷酸溶液 |
掺碳的氮化硅层 | 0.099纳米每分钟 | 0.2纳米每分钟 |
氮化硅层 | 0.38纳米每分钟 | 5.4纳米每分钟 |
氧化硅层 | 2.9纳米每分钟 | 0.15纳米每分钟 |
由表1中可以看出,所述第一侧墙203在磷酸溶液中的刻蚀速率为0.2纳米每分钟,而采用氮化硅形成的第二侧墙204在磷酸溶液中的刻蚀速率为5.4纳米每分钟,所述第二侧墙204和第一侧墙201相比有很高的刻蚀选择比,所以所述第一侧墙203可以作为刻蚀第二侧墙204的刻蚀阻挡层,保护栅极结构200。
去除所述第二侧墙204之后,在栅极结构200两侧只留下第一侧墙203,所述第一侧墙203为掺杂的氮化硅层,可以是单层结构也可以是氮化硅层和掺杂氮化硅层的堆叠结构,由于所述氮化硅层中掺杂了碳或硼等元素,能够降低所述第一侧墙203的介电常数,从而降低形成的晶体管的栅极结构周边的寄生电容大小。
请参考图9,在所述半导体衬底100表面形成应力层400,所述应力层400覆盖半导体衬底100表面、源极102、漏极103和金属硅化物层301、栅极202以及第一侧墙203的表面。
所述应力层400的形成工艺为热化学气相沉积或者等离子体化学气相沉积。如果所述形成的晶体管为NMOS晶体管,则所述应力层400的应力类型为张应力,所述张应力能够对NMOS晶体管的沟道区域提供张应力,提高所述NMOS晶体管的沟道区域内电子的迁移率,从而提高NMOS晶体管的性能。如果所述形成的晶体管为PMOS晶体管,则所述应力层400的应力类型为压应力,所述压应力能够对PMOS晶体管的沟道区域提供压应力,提高所述PMOS晶体管的沟道区域内空穴的迁移率,从而提高PMOS晶体管的性能。
具体的,如果形成CMOS晶体管,首先沉积一层高张应力的应力层,改善CMOS中NMOS的性能,然后通过反应离子刻蚀方法,去除所述PMOS上方的应力层,然后沉积具有压应力的应力层。这样,所述CMOS晶体管上的NMOS上方具有张应力的应力层,而PMOS的上方具有压应力的应力层,可以同时提高所述PMOS和NMOS的性能。
由于在形成所述应力层400之前,去除了第二侧墙204(请参考图7),降低了应力层400与晶体管的沟道区域的距离,从而提高了所述应力层400对晶体管的应力效果,可以进一步提高提高晶体管的性能。
后续可以在所述应力层400表面形成层间介质层(未示出),并且在所述介质层内刻蚀形成通孔,所述应力层还可以作为通孔刻蚀的阻挡层。
请继续参考图9,为本实施采用上述方法形成的晶体管的剖面结构示意图。
所述晶体管包括:半导体衬底100;位于所述半导体衬底100上的栅极结构200,所述栅极结构200包括位于半导体衬底100表面的栅介质层201和位于所述栅介质层201表面的栅极202;位于所述栅极结构200两侧的第一侧墙203,所述第一侧墙203覆盖栅极结构200的侧壁;位于所述栅极结构200两侧的半导体衬底100内的源极102和漏极103;位于所述源极102、漏极103表面的金属硅化物层301;位于半导体衬底100表面的应力层400,所述应力层400覆盖晶体管的源极102、漏极103和金属硅化物层301、栅极202以及第一侧墙203的表面。
具体的,本实施例中所述第一侧墙203的材料为掺杂的氮化硅层,所述第一侧墙的厚度为2nm~10nm,所述第一侧墙203的掺杂元素可以是碳或硼,并且所述掺杂元素的摩尔浓度为3%~30%。
本实施例中,所述第一侧墙203的材料为掺碳的氮化硅层,第一侧墙203内碳的浓度范围为1E21个原子每立方厘米~5E22个原子每立方厘米。所述第一侧墙203与氮化硅层相比,在磷酸溶液或者氢氟酸溶液中的刻蚀速率较低,所述第一侧墙在磷酸溶液中的刻蚀速率小于10纳米每分钟,可以是0.1纳米每分钟~5纳米每分钟。
在本发明的其他实施例中,所述第一侧墙203还可以是多层堆叠结构,所述多层堆叠结构包括多层互相堆叠的氮化硅层和掺杂氮化硅层,所述掺杂氮化硅层的掺杂元素可以是碳或硼等。所述第一侧墙203内的氮化硅层和掺杂氮化硅层的厚度比为1:2~1:50,掺杂元素的摩尔浓度为3%~3%。在本发明的一个实施例中,所述第一侧墙203包括多层堆叠的氮化硅层和掺碳氮化硅层。
所述第一侧墙203内的氮化硅层和掺杂氮化硅层的厚度都很小,并且互相堆叠,相当于将掺杂氮化硅层均匀分散在氮化硅层中。可以通过调整其中氮化硅层与掺杂氮化硅层的厚度比例来调节第一侧墙中掺杂元素的浓度,从而调节所述第一侧墙203的刻蚀速率和介电常数。而单层结构的掺杂的氮化硅层只能通过沉积反应物的浓度来调节掺杂元素的浓度,所以采用多层堆叠的结构对掺杂元素浓度调节的准确度更高,更为方便。
所述第一侧墙203作为后续刻蚀第二侧墙的刻蚀阻挡层,并且所述第一侧墙203中由于掺杂了碳或硼等元素,与未掺杂的氮化硅层相比,介电常数明显下降,可以降低所述晶体管栅极结构周围的寄生电容。如果在形成第一侧墙203之前对栅极结构两侧的半导体衬底进行了轻掺杂离子注入,形成了轻掺杂源漏扩展区,第一侧墙203位于所述轻掺杂源漏扩展区上方,与未掺杂的氮化硅层相比,第一侧墙203采用掺杂的氮化硅层还可以阻挡第一侧墙下方的轻掺杂源漏扩展区的掺杂离子,例如硼离子,向外扩散,从而减少掺杂离子的损失,降低源漏区域的电阻。
所述应力层400的应力类型可以是张应力,也可以是压应力。如果所述形成的晶体管为NMOS晶体管,则所述应力层400的应力类型为张应力,所述张应力能够对NMOS晶体管的沟道区域提供张应力,提高所述NMOS晶体管的沟道区域内电子的迁移率,从而提高NMOS晶体管的性能。如果所述形成的晶体管为PMOS晶体管,则所述应力层400的应力类型为压应力,所述压应力能够对PMOS晶体管的沟道区域提供压应力,提高所述PMOS晶体管的沟道区域内空穴的迁移率,从而提高PMOS晶体管的性能。如果形成的是CMOS晶体管,则所述CMOS晶体管的NMOS上方的应力层400具有张应力,而PMOS的上方的应力层400具有压应力,可以同时提高所述PMOS和NMOS的性能。
由于所述应力层400与晶体管的栅极结构200之间只具有第一侧墙203,与现有技术中具有多层侧墙相比,应力层与晶体管沟道区域的距离下降,从而提高了所述应力层400对晶体管的应力效果,进一步提高晶体管的性能。
本发明虽然已以较佳实施例公开如上,但其并不是用来限定本发明,任何本领域技术人员在不脱离本发明的精神和范围内,都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改,因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰,均属于本发明技术方案的保护范围。
Claims (20)
1.一种晶体管的形成方法,其特征在于,包括:
提供半导体衬底,所述半导体衬底内具有隔离结构,在所述隔离结构两侧的半导体衬底表面上具有栅极结构,所述栅极结构包括位于半导体衬底表面的栅介质层和位于所述栅介质层表面的栅极;
在所述栅极结构两侧形成第一侧墙,所述第一侧墙为掺杂的氮化硅层;
在所述第一侧墙表面形成第二侧墙,所述第二侧墙的刻蚀速率大于第一侧墙的刻蚀速率;
在所述栅极结构两侧的半导体衬底内形成源极和漏极;
在所述源极、漏极表面形成金属硅化物层;
在形成所述金属硅化物层之后,去除所述第二侧墙;
在所述半导体衬底表面形成应力层,所述应力层覆盖半导体衬底表面、金属硅化物层的表面,栅极表面以及第一侧墙的表面。
2.根据权利要求1所述的晶体管的形成方法,其特征在于,所述第一侧墙的掺杂元素为碳或硼,所述掺杂元素的摩尔浓度为3%~30%。
3.根据权利要求1所述的晶体管的形成方法,其特征在于,所述第二侧墙和第一侧墙的刻蚀选择比为4:1~27:1。
4.根据权利要求1所述的晶体管的形成方法,其特征在于,所述第一侧墙的厚度范围为2纳米~10纳米,所述第一侧墙在磷酸溶液中的刻蚀速率小于5纳米每分钟。
5.根据权利要求1所述的晶体管的形成方法,其特征在于,所述第一侧墙的形成工艺为化学气相沉积工艺或原子层沉积工艺,所述第二侧墙的形成工艺为化学气相沉积工艺或原子层沉积工艺。
6.根据权利要求1所述的晶体管的形成方法,其特征在于,所述第一侧墙的形成方法为:采用SiH2Cl2、NH3和C2H4作为反应气体,所述反应的温度范围为450℃~650℃,其中SiH2Cl2的流量为0.1标况升每分~5标况升每分,NH3的流量为0.2标况升每分~5标况升每分,C2H4的流量为0.1~5标况升每分,最终形成的第一侧墙内碳的浓度范围为1E21个原子每立方厘米~5E22个原子每立方厘米。
7.根据权利要求1所述的晶体管的形成方法,其特征在于,所述第一侧墙为多层堆叠结构,所述多层堆叠结构包括互相堆叠的氮化硅层和掺杂氮化硅层,所述第一侧墙内的氮化硅层和掺杂氮化硅层的厚度比为1:2~1:50。
8.根据权利要求7所述的晶体管的形成方法,其特征在于,所述第一侧墙的多层堆叠结构采用循环沉积工艺形成。
9.根据权利要求7所述的晶体管的形成方法,其特征在于,所述第一侧墙内的氮化硅层的形成方法为原子层沉积工艺,采用SiH2Cl2和NH3作为反应气体,其中SiH2Cl2的流量为0.2标况升每分~5标况升每分,NH3的流量为0.5标况升每分~10标况升每分,反应温度为450℃~650℃,反应压强为0.02托~1托;所述第一侧墙内的掺杂氮化硅层的形成方法为原子层沉积工艺,采用SiH2Cl2、NH3和C2H4作为反应气体,其中SiH2Cl2的流量为0.2标况升每分~5标况升每分,NH3的流量为0.5标况升每分~10标况升每分,C2H4的流量为0.2标况升每分~5标况升每分,反应温度为450℃~650℃,反应压强为0.02托~1托。
10.根据权利要求1所述的晶体管的形成方法,其特征在于,所述第二侧墙为氮化硅层。
11.根据权利要求1所述的晶体管的形成方法,其特征在于,所述第二侧墙为多层堆叠结构,所述多层堆叠结构包括互相堆叠的氮化硅层和掺杂氮化硅层,所述第二侧墙内的氮化硅层和掺杂氮化硅层的厚度比为2:1~50:1。
12.根据权利要求11所述的晶体管的形成方法,其特征在于,所述第二侧墙内的掺杂氮化硅层的掺杂元素为碳或硼,所述第二侧墙内掺杂元素的摩尔浓度为0.5%~3%。
13.根据权利要求11所述的晶体管的形成方法,其特征在于,所述第二侧墙的多层堆叠结构采用循环沉积工艺形成。
14.根据权利要求1所述的晶体管的形成方法,其特征在于,去除第二侧墙的方法为:采用磷酸溶液作为刻蚀溶液,所述磷酸溶液的温度范围为120℃~165℃,刻蚀时间为1分钟~65分钟。
15.一种晶体管,其特征在于,包括:
半导体衬底;
位于所述半导体衬底上的隔离结构和栅极结构,所述栅极结构包括位于半导体衬底表面的栅介质层和位于所述栅介质层表面的栅极;
位于所述栅极结构两侧的第一侧墙,所述第一侧墙为掺杂的氮化硅层;
位于所述栅极结构两侧的半导体衬底内的源极和漏极;
位于所述源极、漏极表面的金属硅化物层;
位于半导体衬底表面的应力层,所述应力层覆盖所述源极、漏极和金属硅化物层、栅极以及第一侧墙的表面。
16.根据权利要求15所述的晶体管,其特征在于,所述第一侧墙的掺杂元素为碳或硼,所述掺杂元素的摩尔浓度为3%~30%。
17.根据权利要求15所述的晶体管,其特征在于,所述第一侧墙中掺杂元素的浓度范围为1E21个原子每立方厘米~5E22个原子每立方厘米。
18.根据权利要求15所述的晶体管,其特征在于,所述第一侧墙的厚度范围为2纳米~10纳米。
19.根据权利要求15所述的晶体管,其特征在于,所述第一侧墙在磷酸溶液中的刻蚀速率小于5纳米每分钟。
20.根据权利要求15所述的晶体管,其特征在于,所述第一侧墙为多层堆叠结构,所述多层堆叠结构包括互相堆叠的氮化硅层和掺杂氮化硅层,其中,氮化硅层和掺杂氮化硅层的厚度比为1:2~1:50。
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