CN103906370A - Chip packaging structure, circuit board having embedded component and manufacturing method thereof - Google Patents
Chip packaging structure, circuit board having embedded component and manufacturing method thereof Download PDFInfo
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- CN103906370A CN103906370A CN201210577545.XA CN201210577545A CN103906370A CN 103906370 A CN103906370 A CN 103906370A CN 201210577545 A CN201210577545 A CN 201210577545A CN 103906370 A CN103906370 A CN 103906370A
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- wire layer
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 238000003466 welding Methods 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 25
- 210000005069 ears Anatomy 0.000 claims description 12
- 238000009713 electroplating Methods 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- -1 PI) Polymers 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229920000139 polyethylene terephthalate Polymers 0.000 description 4
- 239000005020 polyethylene terephthalate Substances 0.000 description 4
- 238000003825 pressing Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 3
- 239000011112 polyethylene naphthalate Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 239000003985 ceramic capacitor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- WGCNASOHLSPBMP-UHFFFAOYSA-N hydroxyacetaldehyde Natural products OCC=O WGCNASOHLSPBMP-UHFFFAOYSA-N 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000005026 oriented polypropylene Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention relates to a circuit board, comprising an embedment structure, first and second conducting circuit layers, a second dielectric layer and a third conducting circuit layer. The embedment structure comprises a first dielectric layer and an electronic component, wherein the first dielectric layer comprises first and second surfaces which are opposite to each other, the electronic component comprises a plurality of conductive connection terminals and a first surface embedded in the first dielectric layer, the electronic component is exposed on the surface of the first surface and is flush with the first surface, and the plurality of conductive connection terminals of the electronic component are exposed on the first surface. The first and the second conducting circuit layers are arranged on the first surface and the second surface respectively, wherein the first conducting circuit layer comprises a terminal connection circuit arranged on a surface where part of the conductive connection terminals of the electronic component is flush with the first surface. The second dielectric layer and the third conductive circuit layer are formed at one side of the first conductive circuit layer in sequence. The invention also relates to a manufacturing method of the circuit board and a chip packaging structure.
Description
Technical field
The present invention relates to circuit board making field, relate in particular to a kind of circuit board with embedded element, adopt chip-packaging structure of this circuit board and preparation method thereof.
Background technology
Printed circuit board (PCB) is widely used because having packaging density advantages of higher.Refer to document Takahashi about the application of circuit board, A. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab, High density multilayer printed circuit board for HITAC M-880, IEEE Trans. on Components, Packaging, and Manufacturing Technology, 1992,15 (4): 1418-1425.
The electronic component of the printed circuit board (PCB) of prior art is arranged at the outside of circuit board mostly, like this increased the overall volume of printed circuit board (PCB); In addition, in the time that printed circuit board (PCB) need to arrange more electronic component, because the surface area of printed circuit board (PCB) is limited, the magnitude setting of electronic component is also greatly limited.This electronic component can be active or passive device, as resistance, electric capacity etc.
Summary of the invention
Therefore, be necessary to provide the more rational chip-packaging structure of a kind of small volume and design, there is circuit board of embedded element and preparation method thereof.
A kind of making has the method for the circuit board of embedded element, comprise step: provide embedded structure, this embedded structure comprises the first dielectric layer and electronic component, this first dielectric layer comprises relative first surface and second surface, this electronic component comprises multiple conduction splicing ears, this electronic component is embedded in the surface that the first surface of this first dielectric layer and this electronic component be exposed to this first surface and flushes with this first surface, and multiple conduction splicing ears of this electronic component are exposed to this first surface; In this first dielectric layer, form multiple through holes that run through this first surface and second surface; Form respectively the first conducting wire layer and the second conducting wire layer by electroplating technology at this first surface and second surface, and in the plurality of through hole, forming the conductive through hole of electrical connection this first conducting wire layer and the second conducting wire layer, this first conducting wire floor comprises and is arranged at the lip-deep terminal connecting line road that the partially conductive splicing ear of this electronic component flushes with this first surface; And form successively the second dielectric layer and the 3rd conducting wire layer in this first conducting wire layer one side, thereby form the circuit board with embedded element.
There is a circuit board for embedded element, comprise embedded structure, the first conducting wire layer, the second conducting wire layer, the second dielectric layer and the 3rd conducting wire layer.This embedded structure comprises the first dielectric layer and electronic component, this first dielectric layer comprises relative first surface and second surface, this electronic component comprises multiple conduction splicing ears, this electronic component is embedded in the surface that the first surface of this first dielectric layer and this electronic component be exposed to this first surface and flushes with this first surface, and multiple conduction splicing ears of this electronic component are exposed to this first surface.This first conducting wire layer and the second conducting wire layer are arranged at respectively this first surface and second surface, and this first conducting wire floor comprises and is arranged at the lip-deep terminal connecting line road that the partially conductive splicing ear of this electronic component flushes with this first surface.This second dielectric layer and the 3rd conducting wire layer are formed at this first conducting wire layer one side successively.
A kind of chip-packaging structure, comprises circuit board and the chip with embedded element as above.This circuit board with embedded element further comprises the 3rd dielectric layer, the 4th conducting wire layer, the first welding resisting layer and the second welding resisting layer.The 3rd dielectric layer and the 4th conducting wire layer are formed at this second conducting wire layer one side successively, this first welding resisting layer and the second welding resisting layer are formed at respectively on the 3rd conducting wire layer and the 4th conducting wire layer, this the first welding resisting layer part covers the 3rd conducting wire layer, the 3rd conducting wire layer that is exposed to this first welding resisting layer forms the first electric connection pad, this the second welding resisting layer part covers the 4th conducting wire layer, and the 4th conducting wire layer that is exposed to this second welding resisting layer forms the second electric connection pad.This chip package has on the circuit board of embedded element and is electrically connected with this first electric connection pad in this.
With respect to prior art, circuit board inside inserted by electronic component by the circuit board with embedded element of the present embodiment, and the quantity of the element that can arrange on circuit board increases, and increased elasticity to the design of circuit board.In addition, the circuit board with embedded element in the present embodiment can be applicable to HDI high-density lamination plate.
Accompanying drawing explanation
Fig. 1 be two dielectric layers providing of the embodiment of the present invention, two electronic components and relatively both sides there is respectively the profile of the loading plate of release layer.
Fig. 2 is the cutaway view of sandwich construction that the dielectric layer in Fig. 1, electronic component and loading plate are formed after according to the sequential cascade of dielectric layer, electronic component, loading plate, electronic component and dielectric layer.
Fig. 3 is the cutaway view that electronic component that the loading plate in the sandwich construction of Fig. 2 is separated to rear formation embeds the structure in dielectric layer.
Fig. 4 offers the cutaway view after through hole in the dielectric layer in Fig. 3.
Fig. 5 is that the relative both sides of the dielectric layer in Fig. 4 form respectively conducting wire layer and in through hole, form electric conducting material to form the cutaway view after conductive through hole.
Fig. 6 is that two conducting wire layer sides in Fig. 5 form respectively the cutaway view after dielectric layer and conducting wire layer successively.
Fig. 7 forms respectively the cutaway view that forms the circuit board with embedded element after welding resisting layer on the outermost conducting wire layer in Fig. 6.
Fig. 8 is cutaway view after a side of the circuit board of Fig. 7 forms solder projection.
Fig. 9 is the cutaway view of the chip-packaging structure that forms after packaged chip on the circuit board with embedded element of Fig. 8.
Main element symbol description
| The first |
11 |
| |
12 |
| Loading |
14 |
| |
13 |
| |
121 |
| |
112 |
| |
114 |
| Embedded |
10 |
| Through hole | 115 |
| The first conducting |
15 |
| The second conducting |
16 |
| Conductive through |
17 |
| Terminal connecting |
151 |
| The second |
18 |
| The 3rd conducting |
19 |
| The 3rd |
20 |
| The 4th conducting |
21 |
| |
22 |
| The first |
23 |
| The second |
24 |
| The first |
25 |
| The second |
26 |
| There is the circuit board of embedded element | 30 |
| First |
27 |
| Second |
28 |
| |
29 |
| Chip | 40 |
| Chip-packaging structure | 50 |
| Soldered ball | 34 |
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Refer to Fig. 1 to Fig. 9 embodiment of the present invention a kind of method of making chip-packaging structure is provided, comprise the steps:
Step 1: refer to Fig. 1 and Fig. 2, two the first dielectric layers 11, two electronic components 12 and loading plates 14 are provided, relative both sides at this loading plate 14 arrange respectively release layer 13, and stack gradually and one step press the first dielectric layer 11, electronic component 12, loading plate 14, electronic component 12,11 one-tenth of the first dielectric layers as a whole.
The material of these two the first dielectric layers 11 can be polyimides (Polyimide, PI), polyethylene terephthalate glycol (Polyethylene Terephthalate, or PEN (Polyethylene naphthalate PET), PEN), PP (Prepreg) or ABF (Ajinomoto Build-up film) etc., be preferably PP or ABF, each the first dielectric layer 11 includes relative first surface 112 and second surface 114.This electronic component 12 can be active or passive device, and as resistance, electric capacity etc., in the present embodiment, this electronic component 12 is ceramic capacitor, comprises two conductions splicing ear 121, the i.e. electrodes of ceramic capacitor.This loading plate 14 is for supporting and carry these two the first dielectric layers 11 and two electronic components 12 in pressing process, and the material of this loading plate 14 can be PI, glass layer compress or metal as copper etc.This release layer 13 is processed formation for plastic film being done to plasma treatment or being coated with fluorine, or be coated with silicon (silicone) mould release in film material on as the top layer of PET, PE, OPP and form, this release layer 13 is for facilitating mutually peeling off of these two the first dielectric layers 11 and electronic component 12 and loading plate 14 at subsequent step.
Be understandable that, the quantity of this conduction splicing ear 121 also can, more than two, be not limited to the present embodiment.
This first dielectric layer 11 of pressing, electronic component 12, loading plate 14, electronic component 12, the first dielectric layer 11 can carry out in pressing machine.After pressing, two electronic components 12 are fitted in respectively the surface of adjacent release layer 13; The first surface 112 of two the first dielectric layers 11 is relative with corresponding release layer 13 and under pressure force effect, fit in respectively the surface of corresponding release layer 13, and each electronic component 12 is embedded in the first surface 112 of the first corresponding dielectric layer 11, the surface that each electronic component 12 is adjacent to corresponding release layer 13 flushes with the first surface 112 of the first corresponding dielectric layer 11, and two conduction splicing ears 121 of each electronic component 12 are exposed to first surface 112, and the thickness of each the first dielectric layer 11 is greater than the thickness of corresponding electronic component 12.
Step 2: refer to Fig. 3, utilize stripping technique that this loading plate 14 and two release layers 13 are removed, obtain two embedded structures 10 that comprise the first dielectric layer 11 and be embedded in the electronic component 12 in this first dielectric layer 11.
Because release layer 13 is all set between this loading plate 14 and the first dielectric layer 11 and electronic component 12, utilize the rippability of release layer 13, can easily this loading plate 14 and release layer 13 be peeled off to removal, thereby the structure of loading plate 14 relative both sides is separated from each other, form two embedded structures 10.
Two embedded structure 10 structures are identical, below describe with one of them.This embedded structure 10 comprises the first dielectric layer 11 and is embedded in the electronic component 12 of the first surface 112 of this first dielectric layer 11, the surface that this electronic component 12 is exposed to this first surface 112 flushes with this first surface 112, and two conduction splicing ears 121 of electronic component 12 are exposed to this first surface 112.
Step 3: refer to Fig. 4, form the multiple through holes 115 that run through this first surface 112 and second surface 114 on this dielectric layer.The method that forms the plurality of through hole 115 can be laser pit or machine drilling.
Step 4: refer to Fig. 5, form the first conducting wire layer 15 by electric plating method on this first surface 112 and the surface that this electronic component 12 is exposed to this first surface 112, form the second conducting wire layer 16 at this second surface 114, and at the interior conductive through hole 17 that this first conducting wire layer 15 and the second conducting wire layer 16 are conducted that forms respectively of the plurality of through hole 115.
The method that forms the first conducting wire layer 15, the second conducting wire layer 16 and conductive through hole 17 by electric plating method specifically comprises the steps:
First, embedded structure 10 is cleaned, residual waste residue etc. when removing its surface blot and carrying out step 3 pit or bore process, makes the surface of embedded structure 10 and the inwall of through hole 115 clean, is beneficial to the carrying out of subsequent step.
Secondly, be exposed to the surface of first surface 112 and the inwall of through hole 115 formation conducting film (not shown) by the method for electroless copper at first surface 112 and second surface 114, this electronic component 12 of this first dielectric layer 11.Be appreciated that the technique that forms this conducting film can also, for black hole metallization processes, shadow technique etc., not be limited with the present embodiment.
Again, provide the photoresist layer (not shown) of patterning, make the region of pre-formed the first conducting wire layer 15, the second conducting wire layer 16 and conductive through hole 17 be exposed to this photoresist layer, other region is blocked by this photoresist layer.
Further, the embedded structure 10 that has formed conducting film and photoresist layer is inserted to electroplating bath and connecting electrode is electroplated, on the conducting film that is exposed to this photoresist layer, form copper electroplating layer.In electroplating process, copper electroplating layer fills up this through hole 115, forms this conductive through hole 17.
Finally, remove this photoresist layer, and etching is removed the conducting film being blocked by this photoresist layer, formation the first conducting wire layer 15, the second conducting wire layer 16 and conductive through hole 17.
This first conducting wire floor 15 comprises two terminal connecting line roads 151, and these two electrode connecting line roads 151 are formed at respectively these two conduction splicing ear 121 surfaces at least partly, to be electrically connected respectively these two conduction splicing ears 121.
Be understandable that, one of them conduction splicing ear 121 also can not be electrically connected with the first conducting wire layer 15, but be electrically connected with the second conducting wire layer 16 by conductive blind hole (not shown), another conduction splicing ear 121 is still electrically connected with the first conducting wire floor 15 by terminal connecting line road 151, be that partially conductive splicing ear 121 is electrically connected with the first conducting wire layer 15, remainder conduction splicing ear 121 is electrically connected with the second conducting wire layer 16 by conductive blind hole, is not limited with the present embodiment.The manufacture method of this conductive blind hole is as follows: be also communicated with the wherein blind hole of a conduction splicing ear 121 in the interior formation of this first dielectric layer 11 through this second surface 114, make corresponding conduction splicing ear 121 be exposed to this second surface 114 from this blind hole, form the first conducting wire layer 15, the second conducting wire layer 16 and conductive through hole 17 by electroplating technology in, in this blind hole, form the conductive blind hole that this second conducting wire layer 16 is electrically connected with corresponding conduction splicing ear 121.
Step 5: refer to Fig. 6, form successively the second dielectric layer 18 and the 3rd conducting wire layer 19 in these the first conducting wire layer 15 1 sides, and form successively the 3rd dielectric layer 20 and the 4th conducting wire layer 21 in these the second conducting wire layer 16 1 sides.
This second dielectric layer 18 and the 3rd conducting wire layer 19 and the 3rd dielectric layer 20 and the 4th conducting wire layer 21 can be made formation by Layer increasing method respectively.Between the 3rd conducting wire layer 19 and this first conducting wire layer 15, and can be electrically connected by the conductive hole 22 being formed in this second dielectric layer 18 and the 3rd dielectric layer 20 respectively between the 4th conducting wire layer 21 and this second conducting wire layer 16.
Step 6: refer to Fig. 7, on the 3rd conducting wire layer 19, part covers the first welding resisting layer 23, and part covers the second welding resisting layer 24 on the 4th conducting wire layer 21, the 3rd conducting wire layer 19 that is exposed to this first welding resisting layer 23 forms multiple the first electric connection pads 25, the 4th conducting wire layer 21 that is exposed to this second welding resisting layer 24 forms multiple the second electric connection pads 26, thereby forms the circuit board 30 with embedded element.
In the present embodiment, this first electric connection pad 25 and the second electric connection pad 26 are respectively array and arrange, this first electric connection pad 25 is for being electrically connected with chip (as the chip 40 of Fig. 9), and this second electric connection pad 26 is for being electrically connected as circuit board etc. with other electronic equipment.
Be appreciated that, between the 3rd conducting wire layer 19 and this first conducting wire layer 15 and between the 4th conducting wire layer 21 and this second conducting wire layer 16, more dielectric layer and conducting wire layer can be further set respectively, to form the circuit board with more conducting wires layer.In addition, this quantity with electronic component 12 in the circuit board 30 of embedded element also can be for multiple, and with the present embodiment is not limited.
As shown in Figure 7, the circuit board with embedded element 30 of the present embodiment comprises embedded structure 10, the first conducting wire layer 15, the second conducting wire layer 16, the second dielectric layer 18, the 3rd conducting wire layer 19, the 3rd dielectric layer 20, the 4th conducting wire layer 21, the first welding resisting layer 23 and the second welding resisting layer 24.This first conducting wire layer 15 is formed at the first surface 112 of this first dielectric layer 11 and this electronic component 12 and is exposed to the surface of this first surface 112, the second conducting wire layer 16 is formed at the second surface of the first dielectric layer 11, this the first conducting wire floor 15 comprises two terminal connecting line roads 151, these two terminal connecting line roads 151 are formed at respectively these two conduction splicing ear 121 surfaces at least partly, to be electrically connected respectively these two conduction splicing ears 121.In this first dielectric layer 11, be formed with the conductive through hole 17 of this first conducting wire layer 15 of electrical connection and the second conducting wire layer 16.This second dielectric layer 18 and the 3rd conducting wire layer 19 are formed at this first conducting wire layer 15 1 sides successively, the 3rd dielectric layer 20 and the 4th conducting wire layer 21 are formed at this second conducting wire layer 16 1 sides successively, between the 3rd conducting wire layer 19 and this first conducting wire layer 15, and be electrically connected by the conductive hole 22 being formed in this second dielectric layer 18 and the 3rd dielectric layer 20 respectively between the 4th conducting wire layer 21 and this second conducting wire layer 16.This first welding resisting layer 23 is formed on the 3rd conducting wire layer 19 and part covers the 3rd conducting wire layer 19, and the 3rd conducting wire layer 19 that is exposed to this first welding resisting layer 23 forms multiple the first electric connection pads 25; This second welding resisting layer 24 is formed on the 4th conducting wire layer 21 and part covers the 4th conducting wire layer 21, and the 4th conducting wire layer 21 that is exposed to this second welding resisting layer 24 forms multiple the second electric connection pads 26.
Step 7: refer to Fig. 8, this first electric connection pad 25 and the second electric connection pad 26 are carried out to surface gold-plating, form respectively first surface processing layer 27 and second surface processing layer 28 at this first electric connection pad 25 and the second electric connection pad 26, and form solder projection 29 on these first surface processing layer 27 surfaces.
This first surface processing layer 27 and second surface processing layer 28 for the protection of this first electric connection pad 25 and the second electric connection pad 26 to prevent its oxidation.The plurality of first surface processing layer 27 and second surface processing layer 28 conduct with corresponding the first electric connection pad 25 and the second electric connection pad 26 respectively.Be appreciated that the method that forms this first surface processing layer 27 and second surface processing layer 28 also can be substituted by plating nickel gold, change nickel and soak gold, nickel plating porpezite, zinc-plated etc., is not limited with the present embodiment.
In the present embodiment, can multiple solder projections 29 be formed at respectively by the mode of electroplating or print to the surface of the first surface processing layer 27 on the plurality of the first electric connection pad 25, and the plurality of solder projection 29 protrudes from the surface of this first welding resisting layer 23.This solder projection 29 can be column, spherical etc., is column in the present embodiment, and its material is generally mainly tin.Be understandable that, this first surface processing layer 27 and second surface processing layer 28 also can omit, and now this solder projection 29 is directly formed at the surface of this first electric connection pad 25.
Step 8: refer to Fig. 9, chip 40 is provided, and chip 40 is electrically connected on to the plurality of the first electric connection pad 25 and is packaged in the circuit board 30 that this has embedded element, form chip-packaging structure 50.
In the present embodiment, this chip 40 is chip package (flip-chip) chip, this chip 40 has respectively and the plurality of the first electric connection pad 25 multiple contact tab (not shown) one to one, and this contact tab is generally also made up of scolder, and its material is mainly tin.The plurality of contact tab can be adopted with the following method with the connection of corresponding solder projection 29: first, chip 40 is arranged on the circuit board 30 with embedded element, and the plurality of contact tab is contacted with corresponding solder projection 29 respectively; Then, by this chip 40 together with thering is the circuit board 30 of embedded element through Overwelding and rewelding furnace, make to form after contact tab and solder projection 29 adhere soldered ball 34 cooling curing, thereby make contact tab and solder projection 29 interconnect and conduct.Be understandable that, this chip 40 can be also wire bonding (wire bonding, WB) chip, can adopt known method for packing to be packaged in the circuit board 30 that this has embedded element, is not limited with the present embodiment.
As shown in Figure 9, the chip-packaging structure 50 of the present embodiment comprises the chip 40 that has the circuit board 30 of embedded element and be packaged in this circuit board 30 with embedded element.This chip 40 is electrically connected with the circuit board 30 with embedded element by the multiple soldered balls 34 that are formed between this first electric connection pad 25 and this chip 40, one end of each soldered ball 34 is welded in this first electric connection pad 25, the relative other end is connected in this chip 40, the general main tin that comprises of material of this soldered ball 34.
With respect to prior art, circuit board inside inserted by electronic component 12 by the circuit board with embedded element 30 of the present embodiment, and the quantity of the element that can arrange on circuit board increases, and increased elasticity to the design of circuit board.In addition, the circuit board with embedded element 30 in the present embodiment can be applicable to HDI high-density lamination plate.
Be understandable that, for the person of ordinary skill of the art, can make other various corresponding changes and distortion by technical conceive according to the present invention, and all these change the protection range that all should belong to the claims in the present invention with distortion.
Claims (12)
1. making has a method for the circuit board of embedded element, comprises step:
Embedded structure is provided, this embedded structure comprises the first dielectric layer and electronic component, this first dielectric layer comprises relative first surface and second surface, this electronic component comprises multiple conduction splicing ears, this electronic component is embedded in the surface that the first surface of this first dielectric layer and this electronic component be exposed to this first surface and flushes with this first surface, and multiple conduction splicing ears of this electronic component are exposed to this first surface;
In this first dielectric layer, form multiple through holes that run through this first surface and second surface;
Form respectively the first conducting wire layer and the second conducting wire layer by electroplating technology at this first surface and second surface, and in the plurality of through hole, forming the conductive through hole of electrical connection this first conducting wire layer and the second conducting wire layer, this first conducting wire floor comprises and is arranged at the lip-deep terminal connecting line road that the partially conductive splicing ear of this electronic component flushes with this first surface; And
Form successively the second dielectric layer and the 3rd conducting wire layer in this first conducting wire layer one side, thereby form the circuit board with embedded element.
2. making as claimed in claim 1 has the method for the circuit board of embedded element, it is characterized in that, this first conducting wire floor further comprises the lip-deep terminal connecting line road that the other parts conduction splicing ear in the multiple conducting terminals that are arranged at this electronic component flushes with this first surface.
3. making as claimed in claim 1 has the method for the circuit board of embedded element, it is characterized in that, by electroplating technology in the time that this first surface and second surface form respectively the first conducting wire layer and the second conducting wire layer, in this first dielectric layer, form with the other parts in multiple conducting terminals of this electronic component and conduct electricity the conductive blind hole that splicing ear and this second conducting wire layer be electrically connected.
4. making as claimed in claim 1 has the method for the circuit board of embedded element, it is characterized in that, the manufacture method of this embedded structure comprises step: two the first dielectric layers, two electronic components and loading plate are provided, relative both sides at this loading plate arrange respectively release layer, and stack gradually and one step press the first dielectric layer, electronic component, loading plate, electronic component, the first dielectric layer become as a whole; And
Utilize stripping technique that this loading plate and two release layers are removed, obtain two embedded structures that comprise the first dielectric layer and be embedded in the electronic component in this first dielectric layer.
5. making as claimed in claim 1 has the method for the circuit board of embedded element, it is characterized in that, further comprise step: form successively the 3rd dielectric layer and the 4th conducting wire layer in this second conducting wire layer one side, and form respectively the first welding resisting layer and the second welding resisting layer on the 3rd conducting wire layer and the 4th conducting wire layer, this the first welding resisting layer part covers the 3rd conducting wire layer, the 3rd conducting wire layer that is exposed to this first welding resisting layer forms the first electric connection pad, this the second welding resisting layer part covers the 4th conducting wire layer, the 4th conducting wire layer that is exposed to this second welding resisting layer forms the second electric connection pad.
6. a circuit board with embedded element, comprising:
Embedded structure, this embedded structure comprises the first dielectric layer and electronic component, this first dielectric layer comprises relative first surface and second surface, this electronic component comprises multiple conduction splicing ears, this electronic component is embedded in the surface that the first surface of this first dielectric layer and this electronic component be exposed to this first surface and flushes with this first surface, and multiple conduction splicing ears of this electronic component are exposed to this first surface;
The first conducting wire layer and the second conducting wire layer, be arranged at respectively this first surface and second surface, and this first conducting wire floor comprises and is arranged at the lip-deep terminal connecting line road that the partially conductive splicing ear of this electronic component flushes with this first surface; And
The second dielectric layer and the 3rd conducting wire layer, be formed at this first conducting wire layer one side successively.
7. the circuit board with embedded element as claimed in claim 6, is characterized in that, this first conducting wire floor further comprises and is arranged at the lip-deep terminal connecting line road that the other parts conductions splicing ear of this electronic component flushes with this first surface.
8. the circuit board with embedded element as claimed in claim 6, is characterized in that, has the conductive blind hole being electrically connected with other parts conduction splicing ear in multiple conducting terminals of this electronic component and this second conducting wire layer in this first dielectric layer.
9. the circuit board with embedded element as claimed in claim 6, it is characterized in that, this circuit board with embedded element further comprises the 3rd dielectric layer, the 4th conducting wire layer, the first welding resisting layer and the second welding resisting layer, the 3rd dielectric layer and the 4th conducting wire layer are formed at this second conducting wire layer one side successively, this first welding resisting layer and the second welding resisting layer are formed at respectively on the 3rd conducting wire layer and the 4th conducting wire layer, this the first welding resisting layer part covers the 3rd conducting wire layer, the 3rd conducting wire layer that is exposed to this first welding resisting layer forms the first electric connection pad, this the second welding resisting layer part covers the 4th conducting wire layer, the 4th conducting wire layer that is exposed to this second welding resisting layer forms the second electric connection pad.
10. a chip-packaging structure, comprises circuit board and the chip with embedded element as claimed in claim 9, and this chip package has on the circuit board of embedded element and is electrically connected with this first electric connection pad in this.
11. chip-packaging structures as claimed in claim 10, is characterized in that, this first conducting wire floor further comprises and is arranged at the lip-deep terminal connecting line road that the other parts conductions splicing ear of this electronic component flushes with this first surface.
12. chip-packaging structures as claimed in claim 10, is characterized in that, have the conductive blind hole being electrically connected with other parts conduction splicing ear in multiple conducting terminals of this electronic component and this second conducting wire layer in this first dielectric layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210577545.XA CN103906370B (en) | 2012-12-27 | 2012-12-27 | Chip packaging structure, circuit board having embedded component and manufacturing method thereof |
| TW102101268A TWI466611B (en) | 2012-12-27 | 2013-01-14 | Printed circuit board having buried component, method for manufacturing same and chip package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210577545.XA CN103906370B (en) | 2012-12-27 | 2012-12-27 | Chip packaging structure, circuit board having embedded component and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
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| CN103906370A true CN103906370A (en) | 2014-07-02 |
| CN103906370B CN103906370B (en) | 2017-01-11 |
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| CN201210577545.XA Active CN103906370B (en) | 2012-12-27 | 2012-12-27 | Chip packaging structure, circuit board having embedded component and manufacturing method thereof |
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| Country | Link |
|---|---|
| CN (1) | CN103906370B (en) |
| TW (1) | TWI466611B (en) |
Cited By (4)
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| CN105448856A (en) * | 2014-09-01 | 2016-03-30 | 宏启胜精密电子(秦皇岛)有限公司 | Chip package structure, method of making same and chip package substrate |
| CN105514053A (en) * | 2014-09-05 | 2016-04-20 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN111354687A (en) * | 2018-12-21 | 2020-06-30 | 深南电路股份有限公司 | Packaging structure and preparation method thereof |
| WO2023272642A1 (en) * | 2021-06-30 | 2023-01-05 | 深南电路股份有限公司 | Electronic component package, electronic component, voltage regulator module, and voltage stabilizing device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI571185B (en) * | 2014-10-15 | 2017-02-11 | 矽品精密工業股份有限公司 | Electronic package and method of manufacture |
| TWI762777B (en) * | 2019-03-27 | 2022-05-01 | 恆勁科技股份有限公司 | Semiconductor package substrate and manufacturing method thereof and electronic package and manufacturing method thereof |
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| CN101594740A (en) * | 2008-05-27 | 2009-12-02 | 华通电脑股份有限公司 | Be embedded into the circuit board and the method thereof of electronic device |
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| TWI263313B (en) * | 2005-08-15 | 2006-10-01 | Phoenix Prec Technology Corp | Stack structure of semiconductor component embedded in supporting board |
| TWI365689B (en) * | 2007-12-19 | 2012-06-01 | Unimicron Technology Corp | Embedded circuit board and manufacturing method thereof |
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| CN1518080A (en) * | 2003-01-23 | 2004-08-04 | 新光电气工业株式会社 | Electronic element packaging structure and its manufacturing method |
| CN101594740A (en) * | 2008-05-27 | 2009-12-02 | 华通电脑股份有限公司 | Be embedded into the circuit board and the method thereof of electronic device |
| US20100187003A1 (en) * | 2009-01-23 | 2010-07-29 | Unimicron Technology Corporation | Circuit board structure and fabrication method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448856A (en) * | 2014-09-01 | 2016-03-30 | 宏启胜精密电子(秦皇岛)有限公司 | Chip package structure, method of making same and chip package substrate |
| CN105448856B (en) * | 2014-09-01 | 2018-04-06 | 碁鼎科技秦皇岛有限公司 | Chip-packaging structure, preparation method and chip package base plate |
| CN105514053A (en) * | 2014-09-05 | 2016-04-20 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN111354687A (en) * | 2018-12-21 | 2020-06-30 | 深南电路股份有限公司 | Packaging structure and preparation method thereof |
| CN111354687B (en) * | 2018-12-21 | 2023-12-15 | 深南电路股份有限公司 | Packaging structure and preparation method thereof |
| WO2023272642A1 (en) * | 2021-06-30 | 2023-01-05 | 深南电路股份有限公司 | Electronic component package, electronic component, voltage regulator module, and voltage stabilizing device |
| US11737212B2 (en) | 2021-06-30 | 2023-08-22 | Shennan Circuits Co., Ltd. | Electronic component package, electronic assembly, voltage regulation module, and voltage regulator member |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103906370B (en) | 2017-01-11 |
| TW201427523A (en) | 2014-07-01 |
| TWI466611B (en) | 2014-12-21 |
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