CN103904122B - Fin-type semiconductor structure and forming method thereof - Google Patents
Fin-type semiconductor structure and forming method thereof Download PDFInfo
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- CN103904122B CN103904122B CN201410135448.4A CN201410135448A CN103904122B CN 103904122 B CN103904122 B CN 103904122B CN 201410135448 A CN201410135448 A CN 201410135448A CN 103904122 B CN103904122 B CN 103904122B
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- 239000000463 material Substances 0.000 claims description 77
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 62
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- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 229910052681 coesite Inorganic materials 0.000 claims description 10
- 229910052906 cristobalite Inorganic materials 0.000 claims description 10
- 229910052682 stishovite Inorganic materials 0.000 claims description 10
- 229910052905 tridymite Inorganic materials 0.000 claims description 10
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 6
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- 230000003628 erosive effect Effects 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a fin-type semiconductor structure capable of effectively controlling leakage current between a source area and a leakage area and improving grid control capacity. The fin-type semiconductor structure comprises a fin-type substrate with a lower substrate and a fin part, the source area, the leakage area, a grid structure, narrow trench isolation parts and an isolation part, wherein the source area and the leakage area are formed on the fin part, the grid structure is formed between the source area and the leakage area and crosses over the fin part, the narrow trench isolation parts are formed on the two sides of the fin part and located below the grid structure, and the isolation area is formed in the fin part. The isolation area can be basically located below the source area, and/or basically located below the leakage area, and and/or basically located below the grid structure. The invention further provides a method for forming the semiconductor structure.
Description
Technical field
The present invention relates to quasiconductor design and its manufacturing technology field, it particularly relates to a kind of fin semiconductor structure
And forming method thereof.
Background technology
FinFET is referred to as fin field-effect transistor (Fin Field-Effect TransistorFinFET), is a kind of new
CMOS (CMOS) transistor.Fin is the meaning of fin, and FinFET names shape and the fish according to transistor
Fin similarity, other similar titles include Tri-gate MOS etc..
FinFET is derived from the field-effect transistor (Field-Effect TransistorFET) of current traditional standard
One innovative design.The gate that control electric current passes through in conventional transistor structures can only connecing in the side control circuit of gate
Through and off are opened, and belong to the framework of plane.In the framework of FinFET, forked 3D framework of the gate into class assembling manch can be in circuit
Both sides control circuit connecting and disconnecting.Compare with conventional transistor, this design can improve circuit control can also be big
The lock that width shortens transistor is long.
However, the characteristics of routine FinFET is due to substrat structure itself, there is leakage current between its source region drain region can pass through
The problem of substrate conduction, as lock length is shorter, produces larger leakage current sometimes.In addition, there is also between source and drain and substrate
The higher problem of electric capacity.
It is therefore desirable to propose a kind of leakage current that can reduce between source-drain area, further improve grid control ability
Fin field-effect transistor.
The content of the invention
The present invention is in order at least solve one of above-mentioned technological deficiency, it is proposed that a kind of fin semiconductor structure and
The method for manufacturing this semiconductor structure.The fin semiconductor structure that the present invention is provided further can be reduced between source-drain area
Leakage current, and strengthen the control ability of grid, effectively improve the performance of semiconductor device, extend the life-span.
Semiconductor structure proposed by the present invention includes：Fin substrate with lower substrate and fin portion, is formed in fin
Source region and drain region in portion, is formed in across the grid structure in fin portion between the source region and drain region, under grid structure
The fin portion of side is raceway groove, is formed in fin portion both sides and the shallow trench isolation below grid structure, and is formed
Isolation area in the fin portion.The fin portion（110）The section at two ends is rectangle, or the fin portion（210）
The section at two ends is triangle.The top surface in fin portion is round and smooth curved surface, and the width of top surface is 1-10 nanometers.The structure is also wrapped
Include the side wall positioned at the both sides of the grid structure.
Wherein, isolation area can be generally within source region below；And/or generally within drain region below；And/or generally within grid
Below the structure of pole.For example, isolation area is only positioned in the fin portion below drain region；Isolation area is located at below drain region and grid structure
In fin portion；Isolation area is located at the lower section of grid structure, the equal length with grid structure, or isolation section length and is less than grid
The length of structure.There may be the shorter short isolation area of multiple length in fin portion.The length of the short isolation area is less than fin
4 times of portion's width.
The material of the isolation area is SiO2And/or HfO2, thickness is 5-20nm.
The semiconductor structure also includes the sacrificial region being formed in fin portion, and the isolation area is formed in the sacrificial region
In, the sacrificial region is exposed from the both sides in fin portion.The sacrificial region is through the sacrifice layer in fin portion, or the sacrificial region
It is one or more sacrificial blocks, its thickness 5-50nm.
The fin portion also includes upper fin portion, sacrificial region and lower fin portion.The upper fin portion is the base with fillet
This cuboid or cylinder.It is SiGe, the material in upper fin portion that the material in the lower fin portion is Si, the material of sacrificial region
It is Si；Or the material in the lower fin portion is Si, the material of sacrificial region is SiGe, and the material in upper fin portion is Ge contents than sacrificial
The SiGe in domestic animal area low 10%.Particularly, the material of the sacrificial region is the SiGe of Ge contents 40%, and the material in the upper fin portion is
The SiGe of Ge contents 30%.
When the material in the upper fin portion is Si, the surface in fin portion also has SiGe epitaxial layers, outside SiGe epitaxial layers
Also there is Si epitaxial layers；When the material in the upper fin portion is SiGe, the surface in fin portion has Si epitaxial layers.As the Si
When the thickness of epitaxial layer is less than 5 nanometers, this structure is adapted to make POMS devices.
In addition, upper surface of the upper surface of institute's shallow trench isolation less than isolation area.The both sides of the isolation area have switchback
Area, the switchback area relative to the two sides indentation of fin portion distance less than fin portion width a quarter.Switchback area and fin
The position of piece portion contact can have round and smooth curved surface.The grid structure covers the surface in switchback area, and into fin portion
Side surrounds.
Present invention also offers a kind of integrated chip, this integrated chip is integrated with the fin half of invention offer
Conductor structure and without isolation area fin semiconductor structure.It is described to include without isolation area fin semiconductor structure：With lower substrate
With the fin substrate in fin portion, the source region being formed in fin portion and drain region, be formed between the source region and drain region across
Grid structure in fin portion, the fin portion below grid structure is raceway groove, and the shallow ridges for being formed in fin portion both sides
Road isolates.My the isolation area fin semiconductor structure includes being formed and the sacrificial region in fin portion that the sacrificial region is from fin
Expose the both sides in portion.
Another aspect of the present invention also proposes a kind of forming method of fin type semiconductor device, and methods described includes：
Step A, one substrate of offer, form the fin substrate with lower substrate and fin portion, and the fin portion is comprising sacrificial
Domestic animal area；
Step B, etched portions or whole sacrificial regions are to form cavity, and fill insulant forms isolation in the cavities
Area；
Insulant is continued to fill up, shallow trench isolation is formed；
Carry out that chemical machinery is flat, expose the upper surface in fin portion, etch shallow trench isolation, expose fin portion；
Step C, the pseudo- grid structure being developed across in fin portion simultaneously form side wall in pseudo- grid structure both sides, in pseudo- grid structure
Source region and drain region are formed in the fin portion of both sides；
Step D, pseudo- grid structure is substituted using grid alternative techniques form metal-gate structures.
Step A includes：One substrate is provided, there is in substrate sacrificial region, the sacrificial region is through whole substrate
Sacrifice layer；Etching barrier layer is formed on substrate, mask is formed on etching barrier layer, etch the etching barrier layer to expose
Section substrate, forms fin portion to stop the etching substrate with etching barrier layer, fin portion have upper fin portion, sacrifice layer and
Lower fin portion.
Or, step A includes：One substrate is provided, ion implanting is carried out to the substrate and is formed sacrificial region, it is described sacrificial
Domestic animal area is one or more sacrificial blocks；Etching barrier layer is formed on substrate, mask is formed on etching barrier layer, etching is described
Etching barrier layer forms fin portion to stop the etching substrate with etching barrier layer with expose portion substrate, and fin portion has
Upper fin portion, sacrificial block and lower fin portion.
The thickness of the sacrificial region is 5-50nm.
Step A also includes：Etching forms fin portion, the fin portion（110）The section at two ends is rectangle or the fin
Piece portion（210）The section at two ends is triangle.Mask of the width for 1-10nm, control fin portion top are formed on etching barrier layer
The width in face.
The material in the lower fin portion can be Si, the material of sacrificial region be SiGe, the material in upper fin portion be Si；Or
Person, the material in lower fin portion be Si, the material of sacrificial region be SiGe, the material in upper fin portion be that Ge contents are lower than sacrificial region by 10%
SiGe；Particularly, the material of the sacrificial region is the SiGe of Ge contents 40%, and the material in upper fin portion is Ge contents 30%
SiGe。
Step B also includes：Etch cavity uses multiple dry method and/or wet-mixed to etch, and plasma etching, etching
The last time etching of cavity is wet etching.The height of cavity etching is 5-20nm.
Diverse location in fin portion can form one or more cavitys of different length.For example, it is in place in drain region institute
Put etching in the fin portion of lower section and form cavity；Shape is etched in the fin portion below drain region and part of grid pole structure position
Into cavity；All or part of portion sacrificial region below etching grid structure position, forms cavity；Etching forms multiple shorter
Short cavity.Particularly, 4 times less than fin portion width of the short cavity length that etching is formed.
After step B also includes having etched cavity, the edge at edge and fin portion top to cavity carries out round and smooth place
Reason.The method of the round and smooth process adopts the annealing of isotropic etching or lower more than 700 degrees Celsius of hydrogen environment.It is described
Insulant can be SiO2And/or HfO2。
After etches sacrificial area forms cavity, in one layer of SiGe epitaxial layer of surface epitaxial growth of fin portion and cavity, then
SiGe epitaxial layers Epitaxial growth forms one layer of Si epitaxial layer, or, after etches sacrificial area forms cavity, in fin portion and cavity
One layer of Si epitaxial layer of surface epitaxial growth.
Shown step B also includes：Before fill insulant, thermal oxidation is carried out to fin portion, in fin portion table
Face forms SiO2, reduce or closed cavity.Etching shallow trench isolation, exposes the top of isolation area.
Before step C is carried out, switchback process is carried out to isolation area, form switchback area.When isolation area material is SiO2When,
Switchback process is carried out with Fluohydric acid. wet etching.The switchback area of formation is less than fin relative to the distance of fin portion two sides indentation
The a quarter of portion's width.The step C-shaped into pseudo- grid structure can cover the surface in switchback area, and wrap on the inside of fin portion
Enclose.
In addition, when the substrate for providing has greater depth, the present invention also provides a kind of forming method, and step includes：
Step A, one long substrate of offer, are pre-designed quantity, the position of construction featuress, length and the isolation area of individual devices
Put and size；
The fin substrate of step B, formation with lower substrate and fin portion, the fin portion includes sacrificial region；
Step C, etched portions or whole sacrificial regions are to form cavity, and fill insulant forms isolation in the cavities
Area；
Insulant is continued to fill up, shallow trench isolation is formed；
Carry out that chemical machinery is flat, expose the upper surface in fin portion, etch shallow trench isolation, expose fin portion；
Step D, fin substrate and shallow trench isolation are blocked by the device length being pre-designed；
Step E, the pseudo- grid structure being developed across in fin portion simultaneously form side wall in pseudo- grid structure both sides, in pseudo- grid structure
Source region and drain region are formed in the fin portion of both sides；
Step F, pseudo- grid structure is substituted using grid alternative techniques form metal-gate structures.
By fin semiconductor structure proposed by the present invention, can further reduce the leakage current in fin quasiconductor, increase
The control ability of strong grid, raising sensitivity.Device performance is significantly improved, and service life extends.Device of the present invention
Forming method change it is various, disclosure satisfy that the manufacture of the different various devices of performance requirement, and be easy to produce in enormous quantities.
Description of the drawings
Of the invention above-mentioned and/or additional aspect and advantage will become from the following description of the accompanying drawings of embodiments
It is substantially and easy to understand, wherein：
Fig. 1 to Figure 11 is the intermediate steps schematic diagram of fin type semiconductor device manufacture method according to embodiments of the present invention.
Figure 11 is the structural representation of the semiconductor device formed in the embodiment of the present invention.
Figure 12 is the structural representation of another kind of fin substrate in the embodiment of the present invention.
Figure 13 is the structural representation of another kind of cavity formation layout in the embodiment of the present invention.
Figure 14 is the structural representation in switchback area in the embodiment of the present invention.
Figure 15 is the structural representation for forming SiGe layer and Si layers in the embodiment of the present invention in fin portion and cavity surface.
Specific embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein from start to finish
Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached
The embodiment of figure description is exemplary, is only used for explaining the present invention, and is not construed as limiting the claims.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.For letter
Change disclosure of the invention, hereinafter the part and setting of specific examples are described.Their purpose does not simultaneously lie in restriction originally
Invention, only as an example.Additionally, the present invention can in different examples repeat reference numerals and/or letter.This repetition be for
Simplify and clearly purpose, itself do not indicate the relation between discussed various embodiments and/or setting.Additionally, this
The example of the bright various specific technique for providing and material, but those of ordinary skill in the art can be appreciated that other techniques
Applicable property and/or other materials use.
Definition is made to the direction of device of the present invention before explanation embodiment, fin portion is made from the direction of substrate upper process
For z directions, vertical with z directions and parallel to fin portion top direction is x directions, is y side perpendicular to the direction in x, z direction
To.
Embodiment one
The present invention proposes a kind of semiconductor structure and its manufacture method, as shown in figures 1-15, is the middle spacer step of the method
Rapid schematic diagram.Hereinafter, by with reference to these accompanying drawings being described in detail to each step of the embodiment of the present invention.
Step A：One substrate 100 comprising sacrificial region is provided, is formed with lower substrate 180 and fin over the substrate
The fin substrate 100 in portion 110, the sacrificial region 113 in fin portion, with reference to shown in Fig. 6.
In the technique of preparing substrate, as shown in Figure 1, there is provided a substrate 100, substrate 100 include the first substrate 101, its
Material can be silicon, then use epitaxial growth（epitaxy）Method one layer of sacrificial region 113 is formed on the first substrate 101,
In the present embodiment, the sacrificial region 113 is the sacrifice layer 113 through whole substrate.The material of sacrifice layer 113 is preferably SiGe, n
Type adulterates（n-type doped）Silicon etc., thickness is preferably 5-50nm.Then at continued growth on sacrifice layer 113, such as extension life
Long second substrate 102, second substrate 102 become the upper fin portion in the fin portion 110 formed in subsequent process steps
114 basis, is consequently formed the substrate 100 comprising sacrificial region 113.Especially, the material of the sacrifice layer 113 can be that Ge contains
The SiGe of amount 40%, the material of the second substrate 102 can be Si, or second substrate 102 is that Ge contents are more lower slightly than sacrifice layer
SiGe, the preferably SiGe of Ge contents lower than sacrifice layer more than 10%.It is different according to requirement of the device for being formed to performance, can
To form the second substrate 102 using different materials.For example：For NMOS, the second substrate 102 is chosen as silicon；For PMOS
For, the second substrate 102 is preferably SiGe, and wherein Ge contents can be 30%.The knot that this second substrate is formed by sige material
Structure can improve the mobility of carrier hole in PMOS device, improve the performance of raceway groove, strengthen grid-control.
After forming the substrate 100 comprising sacrifice layer, that is, need to process fin portion, as shown in Fig. 2 in the table of substrate 100
Face forms etching barrier layer 900.Etching barrier layer 900 can have multiple choices, in the present embodiment, specifically, can deposit
One layer of oxide skin(coating) 901, such as 10-200nm, one layer of nitride layer 902 of formation on oxide skin(coating) 901, such as 10-200nm,
Form etching barrier layer 900.With reference to Fig. 3, the mask of one fixed width in the y-direction is formed on etching barrier layer 900 with protection portion
Point etching barrier layer 900, the one fixed width determined by the top surface width in the y-direction in fin portion, such as preferably 1-10
Nanometer, then carries out selective etch to nitride layer 902 and 901 etching barrier layer 900 of oxide skin(coating), forms as shown in Figure 4
Structure, the upper surface of expose portion substrate 100.
Then, using etching barrier layer 900 as stop, substrate 100 is performed etching, forms fin portion 110, such as Fig. 5 institutes
Show.Fin portion 110 has upper fin portion 114, the sacrifice layer 113 through fin portion and lower fin portion 112, as shown in Figure 6.Its
In, the second substrate 102 forms upper fin portion 114, and the first substrate of part 101 forms lower fin portion 112.Lower substrate 180 and fin
Piece portion 110 constitutes fin substrate 100.The shape in fin portion 110 can be selected as needed, and by etching technics and parameter
It is controlled, it is rectangular fin portion 110 that can for example form two end sections, as shown in Figure 6.Two end sections can also be formed
For the fin portion 210 of triangle, as shown in figure 12.
According to being located at, whether the first substrate 101 is identical with the material of the second substrate 102, and the material in upper fin portion 114 is with
The material in fin portion 112 can be material Si, or, the material in upper fin portion 114 can be preferably Ge contents 30%
SiGe, the material in lower fin portion 112 is Si.According to the difference of device performance requirements to be formed, other materials shape can be used
Into upper fin portion 114 and lower fin portion 112, those skilled in the art can carry out the selection and change of these materials as needed
Change, these are within protection scope of the present invention.
Then, into step B：Etched portions sacrifice layer 113 is to form cavity 200, and in cavity 200 fills insulation material
Material, forms isolation area 300 and shallow trench isolation 105.
First, uniformly coat photoresist on 110 surface of fin portion, and with mask block sacrifice layer 113 to be retained and
Fin portion 110, exposure need the sacrifice layer 113 to form cavity 200.It is exposed to being exposed portion of photoresist, washes exposure off
After the photoresist of light, the sacrifice layer 113 that the portion is exposed is etched.Formed between upper fin portion 114 and lower fin portion 112 and passed through
The cavity 200 in y-axis direction is worn, as shown in Figure 7.The height in a z-direction of the cavity 200 can be 5-50nm.Due to sacrificing
The material of layer 113 is made up of SiGe, and if cavity 200 is too high, that is, sacrifice layer 113 is too thick, can be in SiGe sacrifice
The defects such as dislocation are produced in layer 113（defect）, the defect is likely to extend, and into channel region above, makes the property of device
Can be deteriorated.So, cavity 200 it is highly preferred for 5-20 nanometers.
Multiple dry method and/or wet-mixed can be used during etch cavity 200 to etch, including plasma etching.Wherein, do
Method etching can preferably control the shape and size of cavity, form relatively small cavity 200.Particularly, in order to reduce quarter
Erosion reduces surface defect to surface damage, and the last time etching technics of etch cavity 200 should be wet etching.
After the completion of cavity 200 is etched, the photoresist on 110 surface of fin portion is removed.
In addition, the example of cavity 200 is formed as another kind of etching, diverse location that can be in the x-direction forms different length
One or more cavitys 200 of degree, as shown in figure 13, form the first cavity 2001 and the second cavity 2002.The number of cavity 200
Amount, position, size can be selected to the difference of performance requirement according to the device is formed.When cavity 200 is only positioned at source region
6002 or drain region 6001 below fin portion inside when, device has preferable isolation effect, does not form the device of 200 side of cavity
The heat conductivity and mechanical strength of part structure is more preferable, because upper fin portion 114 is connected with lower fin portion 112 by sacrifice layer 113,
Sacrifice layer 113, such as SiGe, heat conductivity than the isolation area 300 filled in cavity, such as silicon oxide, heat conductivity it is good；And it
Mechanical strength than there is the structure to form cavity 200 and then backfill isolation area 300 high because sacrifice layer 113 and upper fin portion 114
One integrally formed with lower fin portion 112, between be tightly combined.For example when in order to obtain more high mechanical properties and more preferable heat conduction
Property device when can form the shorter cavity 200 of relative length in the x-direction, and when needing to obtain the preferable device of isolation effect
When multiple cavitys 200 can be formed in sacrifice layer.In order to maintain the mechanical strength of device, member-retaining portion sacrifice layer 113 is must
Want.The device long for grid length, for example pseudo- grid structure length is more than 120 nanometers in the x-direction, if cavity 200 is along x side
To if wide, the mechanical performance of device can decline.Can pass through to form the shorter short sky of 1 or multiple width in the x-direction
Chamber 200, to realize reducing the leakage current between source and drain, while maintaining the purpose of good mechanical performance and intensity.Short cavity 200
Length in the x-direction should be less than 4 times of the width in the y-direction of fin portion 110.
Cavity position in the devices is different, can produce different impacts to the performance of device, including it is following some：
1. etch in the fin portion below 6001 position of drain region and form cavity 200.In this configuration, source region
6002 and pseudo- grid structure below fin portion yet suffer from sacrifice layer 113, the upper fin portion 114 of the connection of sacrifice layer 113 and lower fin
Piece portion 112.The structure has preferable heat conductivity and more high mechanical properties.Simultaneously as isolate between drain region 6001 and substrate,
Reduce the section leakage current in drain region 6001.
2. etch in the fin portion below the pseudo- grid structure position in drain region 6001 and part and form cavity 200.It is this
Structure can reduce the parasitic capacitance between grid and fin substrate below, while reducing the section leakage current in drain region 6001.
3. the sacrificial region below pseudo- grid structure position is etched, cavity 200 is formed.Cavity length in the x direction can
With the length equal to pseudo- grid structure.When grid structure length in the x-direction is longer, cavity length in the x-direction is less than grid
The length of structure.This structure has an excellent short-channel effect, and can effectively reduce source region 6002 and drain region 6001 it
Between by the leakage current below pseudo- grid structure.
4. the device longer for grid length in the x direction, is preferably formed as one or more in relatively short short in x directions
Cavity 200.This structure can be in the case where isolation effect be improved, it is ensured that the mechanical stability of device, improves yields.
After having etched cavity 200, selectively, to cavity 200 edge and the edge of fin portion top surface 111 is carried out
It is round and smooth（rounding）Process, the method for round and smooth process can adopt isotropic etching or hydrogen environment lower 700 degrees Celsius
The methods such as annealing above.The step makes the top 111 in fin portion 114 have round and smooth surface, as shown in Figure 7.Upper fin
The lower surface in portion 114 can also be processed into smooth curved surface.The effect of round and smooth process is that it can reduce the internal field of device
Intensity, strengthens the reliability of device.
Particularly, when the cross sectional shape at 110 two ends of fin portion is basic cuboid, by cavity 200
Edge carries out round and smooth process, and the upper fin portion 114 can form basic cuboid-type structure or cylinder with fillet
Structure.If the degree of round and smooth process is less, upper fin portion 114 forms the basic cuboid-type structure with fillet, if
The degree of round and smooth process is larger, then go up fin portion 114 and form substantially cylindrical structure.
After again, the cavity 200 is filled with insulant, form isolation area 300.Insulant can be SiO2、HfO2
Deng.After filling up cavity 200, insulant should be continued to fill up to form shallow trench isolation (STI) 105, as shown in Figure 8.Shallow channel
The upper surface of isolation 105 is higher than the top 111 in fin portion.Afterwards, chemical-mechanical planarization is carried out, exposes the upper table in fin portion
Face.Again shallow trench isolation is performed etching, exposure fin portion 110, upper surface location of the etching stopping in isolation area 300.Can be with
Part isolation area 300 is exposed, as shown in Figure 9.
Particularly, before fill insulant, thermal oxidation can be carried out to fin portion 110.The surface meeting of fin portion
Because thermal oxidation forms SiO2, so as to reduce even closed cavity 200.After thermal oxidation, should be into remaining cavity
With fill insulant in fin portion 110, complete isolation area 300 and shallow trench isolation 105 are formed.On thermal oxide can be caused
The lower surface in fin portion has good surface quality, so as to not interfere with the mobility of carrier inside fin.
After forming complete isolation area 300 and shallow trench isolation 105, the isolation area 300 in the y-direction should be from fin portion
110 both sides are exposed, as shown in Figure 9.Hereafter, switchback process can be carried out to isolation area 300.When isolation area is silicon dioxide material
When material, wet etching is carried out with Fluohydric acid., etched portions isolation area 300 forms switchback in isolation area both sides in the y-direction
Area 301 (undercut), as shown in figure 14.Switchback area 301 is should be less than relative to the distance of fin portion two sides indentation in the y-direction
The a quarter of the width in the y-direction of fin portion 110, can so maintain the mechanical stability of fin.When isolation area 300 is located at grid
During 400 lower section of structure of pole, if there is switchback area 301, then grid structure 400 can cover the surface in switchback area 301, and edge
Y directions are surrounded on the inside of fin portion, the part surface of 114 lower end of fin portion in covering.This structure can effectively strengthen grid-control
Intensity, greatly improves device performance.
For the consideration of optimized device performance, selectively, can be after etching sacrificial layer forms cavity 200, in fin
By being epitaxially-formed SiGe layer and Si layers in piece portion 110.For example, when the material in upper fin portion 114 is Si, can be in fin
200 surface epitaxial growth SiGe epitaxial layers of piece portion 110 and cavity, can also be formed outside Si in SiGe epitaxial layers Epitaxial growth again
Prolong layer, as shown in figure 15.When the material in upper fin portion 114 is SiGe, can be in 200 surface extension of fin portion 110 and cavity
Growth forms Si epitaxial layers（Not shown in figure）.If the thickness of above-mentioned Si epitaxial layers is less than 5 nanometers, it is more suitable for making PMOS
Semiconductor device.The Si epitaxial layers of thinner thickness can form pressure to fin portion on the SiGe epitaxial layers of lower section or SiGe should
Power, so as to improve the hole mobility of SiGe, it is possible to increase the performance of raceway groove in PMOS device.If the thickness of Si epitaxial layers compared with
Thickness, then be more suitable for making nmos device, and Si epitaxial layers have more preferable surface state, and electronics therein is the current-carrying in nmos device
Son.For preferred CMOS embodiments, preferred fin is silicon, relative SiGe for sacrifice layer when with good Etch selectivity.Can
So that after the formation of the cavity, selectivity sequentially carries out the epitaxial growth of SiGe and silicon in the region of PMOS fins.These optimizations
Embodiment, those of ordinary skill in the art can be selected as needed and be changed, and these are without departing from the guarantor of the present invention
Shield scope.
Then, into step C：The pseudo- grid structure in fin portion 110 is developed across, the fin portion below pseudo- grid structure is
Raceway groove 106, forms source region and drain region in the y-direction in the fin portion 110 of pseudo- 400 both sides of grid structure.
In the present embodiment, can in fin portion 110 other high K dielectric materials such as deposit hafnium oxides, nitride, shallow
The pseudo- grid in fin portion are developed across above channel isolation 105.The unnecessary high K dielectric material of etching, forms pseudo- grid structure
400, as shown in Figure 10.
Then, side wall 500 is formed, the cvd nitride thing in fin portion 110 and pseudo- grid structure 400 forms nitride layer.Carve
Nitride layer in erosion fin portion 110 and at the top of pseudo- grid structure 400, so as in pseudo- 400 both sides of grid structure, fin portion in the x-direction
Side wall 500 is formed on 110, as shown in figure 11.
Ion implanting is carried out in the fin portion of last 400 both sides of grid structure pseudo- in the x-direction, so as to form source region 6002 and leakage
Area 6001, as shown in figure 11.Additionally, before source region and drain region is formed, can also include carrying out ion implanting, so as to form source
The step of leakage expansion area.
Step D：Pseudo- grid structure is substituted using grid alternative techniques and forms grid structure.
Particularly, in order to be easy to mass production in the factory, general substrate 100 in the x direction all can be with than larger
Length, that is, long substrate is provided.It is advantageous to, can be with pre-designed individual devices construction featuress, length in the x direction
And the quantity of isolation area 300, position, size, the work of step A and step B is first completed on the substrate 100 with greater depth
Sequence, afterwards according to the device length being pre-designed, by the device for having formed isolation area 300 and shallow trench isolation 105 in the x-direction
Block, form single device.Carry out the processing of step C, D afterwards again.Step is blocked with phase the step of forming cavity, isolation area
It is mutually independent.
Additionally, it is contemplated that in actual production, the performance requirement of various semiconductor device itself is simultaneously differed, and some devices are not
Needs form isolation area in fin portion.Such as ESD device, if there is isolation area in fin portion, can affect device on the contrary
Performance.So, not all device is required for forming isolation area.But, on the production line of mass for convenience feed and
Processing, all includes sacrificial region in all of substrate.And it is different according to type of device to be produced in process, decision is
It is no to form isolation area in the devices.That is, may only be had using the semiconductor device structure that the method for the present invention is processed and be sacrificed
Area, but there is no isolation area.Sacrificial region in fin portion all retains, and is formed without isolation area fin semiconductor structure.
Embodiment two
It is illustrated in terms of first embodiment being different from regard to second embodiment only below.The part not described should be recognized
It is to employ identical step, method or technique to carry out with first embodiment, therefore will not be described here.
Step A：One substrate 100 comprising sacrificial region 113 is provided, is formed with lower substrate 180 on the substrate 100
With the fin substrate 100 in fin portion 110, the sacrificial region 113 is in fin portion.
Different from first embodiment, in the present embodiment, the sacrificial region 113 is not through the sacrifice layer in fin portion, and
Show as one or more sacrificial blocks 113.
The mode for forming sacrificial block 113 can be completed in the technique of preparing substrate 100, in the present embodiment, there is provided one
Substrate 100, needs position to be protected to form mask on 100 surface of substrate, needs the position to form sacrificial block 113 so as to expose,
Carry out ion implanting, preferably N-shaped doping, such as P or As.There is certain density region so as to be formed in substrate 100, i.e.,
Form sacrificial region 113.Substrate is performed etching, fin portion 110 is formed, the sacrificial region is or many in the substrate of distribution
The sacrificial block 113 in individual region.The sacrificial region is the one or several regions in fin portion 110.
Step B：Etched portions or whole sacrificial region forming cavity, and fill insulant in the cavities, formed every
From area and shallow trench isolation.
According to requirement etched portions of the device to performance or whole sacrificial blocks 113 is formed, can be to 200 side of cavity of formation
Edge carries out round and smooth process, can be with fin portion 110 and 200 surface epitaxial growth SiGe epitaxial layers of cavity and/or Si epitaxial layers.
The cavity 200 is filled with silicon dioxide or other insulant, isolation area 300 and shallow trench isolation 105 is formed.
Step C, it is developed across the pseudo- grid structure 400 in fin portion above shallow trench isolation 105, below pseudo- grid structure
Fin portion be raceway groove 106, source region 6002 and drain region 6001 are formed in the fin portion of pseudo- 400 both sides of grid structure.
Step D, pseudo- grid structure is substituted using grid alternative techniques form grid structure.
Embodiment three
Additionally, the invention allows for a kind of fin type semiconductor device structure, with reference to Figure 11, the device has：Including
The fin substrate 100 in lower substrate 180 and fin portion 110, the source region 6002 and drain region 6001 in fin portion 110, source region 6002
Across the grid structure 400 in fin portion 110 and drain region 6001 between, the fin portion below grid structure is raceway groove, along y side
Shallow trench isolation 105 to 110 both sides of fin portion and below grid structure 400, in the x-direction both sides of grid structure 400
Side wall 500, and the isolation area 300 between raceway groove and lower substrate being formed in the fin portion 110.Fin portion
110 can include upper fin portion 114, sacrificial region 113 and lower fin portion 112.110 top surface width of the fin portion is preferably 1-
10nm, the section at its fin portion two ends can be rectangle, as shown in fig. 6, or be triangle, as shown in figure 12, top surface can
Being round and smooth curved surface.Two end sections have more preferable mechanical stability for the fin portion of triangle, and two end sections are rectangular
After the fin portion of shape forms device, grid-control is more preferable.
Particularly, when 110 two ends cross sectional shape of the fin portion is cuboid, the upper fin portion 114 can be
Cuboid-type structure with fillet or cylindrical structural.If the degree of round and smooth process is less, upper fin portion 114 is formed
Basic cuboid-type structure with fillet, if the degree of round and smooth process is larger, upper fin portion 114 forms substantially cylindrical
Structure.
The isolation area it is highly preferred for 5-20nm, the material of isolation area can be SiO2And/or HfO2.The shallow ridges
The upper surface of road isolation 105 can be less than the upper surface of isolation area 300.The upper surface of shallow trench isolation 105 is less than isolation area 300
During upper surface, grid structure can be made more to cover upper fin portion in the z-direction, this feature can reduce leakage current, strengthen and drive
Streaming current simultaneously strengthens grid-control.
Expose both sides of the sacrificial region 113 in the y-direction from fin portion 110.The isolation area 300 is formed in the sacrificial region
In 113.The sacrificial region 113 can be through the sacrifice layer in fin portion 110 or one or more sacrificial blocks.
The material in lower fin portion 112 can be Si, and the material of sacrificial region 113 is SiGe, and the material in upper fin portion 114 is
Si.Or, the material in lower fin portion 112 can be Si, and the material of sacrificial region 113 is SiGe, and the material in upper fin portion 114 is Ge
SiGe of the content than sacrificial region 113 low 10%.Particularly, the material of sacrificial region 113 can be the SiGe of Ge contents 40%, upper fin
The material in portion 114 is the SiGe of Ge contents 30%.This upper fin portion can make PMOS devices by the structure that sige material is formed
Part, SiGe can improve the mobility of carrier hole in PMOS device, improve the performance of raceway groove, strengthen grid-control.
In addition, when the material in upper fin portion 114 is Si, the surface in fin portion 110 can have SiGe epitaxial layers,
There can also be one layer of Si epitaxial layer outside SiGe epitaxial layers.Or, when the material in upper fin portion 114 is SiGe, fin portion 110
Surface can have Si epitaxial layers.If the thickness of above-mentioned Si epitaxial layers is less than 5 nanometers, it is more suitable for making PMOS quasiconductors
Device.The Si epitaxial layers of thinner thickness can form compressive stress to fin portion on the SiGe epitaxial layers of lower section or SiGe, so as to
Improve the hole mobility of SiGe, it is possible to increase the performance of raceway groove in PMOS device.If the thickness of Si epitaxial layers is thicker, more
It is adapted to make nmos device, Si epitaxial layers have more preferable surface state, and electronics therein is the carrier in nmos device.
Particularly, can there are multiple isolation areas 300 in device on diverse location in the x-direction.The isolation area 300
Below source region 6002；And/or generally within drain region 6001 below；And/or generally within grid structure 400 below.
The quantity of isolation area 300, position, size can be selected to the difference of performance requirement according to the device is formed.
When isolation area 300 is only positioned at the inside in the fin portion 110 below source region 6002 or drain region 6001, isolation area 300
Isolation effect preferably, the mechanical strength and heat conductivity for not forming the device architecture of 300 side of isolation area is more preferable.Because upper fin
Portion 114 is connected with lower fin portion 112 by sacrifice layer, and the heat conductivity of sacrifice layer 113 is better than the heat conductivity of isolation area 300, and
And which is tightly combined between upper fin portion 114 and lower fin portion 112, high mechanical strength.When the length in the x-direction of isolation area 300
When relatively short, the heat conductivity and mechanical strength of device is more preferable.When there is multiple isolation areas 300 in sacrifice layer 113, device
Isolation effect is more preferable.When length is more than 120 nanometers to grid in the x-direction, there are one or more in sacrifice layer 113 in the x-direction
The shorter short isolation area 300 of length, this structure can reduce the leakage current between source and drain, and maintain good mechanical strength.
The length in the x-direction of short isolation area 300 should be less than 4 times of the length in the y-direction of fin portion 110.
The position in the devices of isolation area 300 is different, can produce different impacts to the performance of device, including following several
Point：
1. isolation area 300 is existed only in below drain region 6001.In this configuration, source region 6002 and grid structure 400
Sacrifice layer 113, the upper fin portion 114 of the connection of sacrifice layer 113 and lower fin portion 112 are yet suffered from the fin portion 110 of lower section.The knot
Structure has preferable heat conductivity and more high mechanical properties.Simultaneously as isolating between drain region 6001 and lower substrate 180, reduce
The section leakage current in drain region 6001.
2. isolation area 300 is present in below drain region 6001 and part of grid pole structure 400.This structure can reduce grid knot
Parasitic capacitance between structure 400 and lower fin portion 112, while reducing the section leakage current in drain region 6001.
3. isolation area 300 is present in the lower section of grid structure 400, and isolation area length in the x direction can be tied with grid
The equal length in the x-direction of structure 400.When grid structure length in the x-direction is longer, isolation area length in the x-direction is less than
The length of grid structure.This structure has excellent short-channel effect, and can effectively reduce source region 6002 and drain region
By the leakage current below grid structure 400 between 6001.
4. the device longer for grid structural length in the x direction, has in fin portion in the x-direction that length is relatively
Little multiple short isolation area 300.This structure can be in the case where isolation effect be strengthened, it is ensured that the mechanical stability of device,
Improve yields.
In addition, the both sides in the y-direction of isolation area 300 have switchback area 301, switchback area 301 is in the y-direction relative to fin portion
The distance of two sides indentation should be less than a quarter of the width in the y-direction of fin portion 110.Switchback area 301 is connect with lower fin portion 112
Tactile position has round and smooth curved surface, as shown in figure 14.When isolation area 300 be located at 400 lower section of grid structure when, if there is return
Area 301 is cut, then grid structure 400 can cover the surface in switchback area 301, and surround on the inside of fin portion in the y-direction, cover
The part surface of upper 114 lower end of fin portion.This structure can effectively strengthen grid-control intensity, greatly improve device performance.
In addition, combine be actually needed and working condition, present invention also offers a kind of integrated chip.This chip is by partly leading
Body device is integrated to form.The fin with isolation area that integrated semiconductor device in the chips is formed in including the present embodiment half
Conductor structure, and without isolation area fin semiconductor structure.It is described without in isolation area fin semiconductor structure and the present embodiment
Fin semiconductor structure is manufactured in identical production line, so can wherein have sacrificial region.But the property according to needed for device
The difference of energy, does not form isolation area in the fin semiconductor structure of part, as described without isolation area fin semiconductor structure.
Below embodiments in accordance with the present invention invention has been described.The range of application of the present invention is not limited to
The technique of the specific embodiment described in description, mechanism, manufacture, material composition, means, method and step.From the present invention's
Disclosure, will readily appreciate that as one of ordinary skill in the art, at present existing or will develop later
Technique, mechanism, manufacture, material composition, means, method or the step for going out, wherein their execution are corresponding real with present invention description
The function that example is substantially the same or the result that acquisition is substantially the same are applied, they can be applied according to the present invention.Therefore, originally
Invention claims are intended to for these techniques, mechanism, manufacture, material composition, means, method or step to be included in its protection
In the range of.
Claims (59)
1. a kind of fin semiconductor structure, it is characterised in that include：
Fin substrate with lower substrate and fin portion；
The source region being formed in fin portion and drain region；
It is formed between the source region and drain region across the grid structure in fin portion, the fin portion below grid structure is ditch
Road；
It is formed in the shallow trench isolation of fin portion both sides；And
The isolation area below the grid structure, between raceway groove and lower substrate being formed in the fin portion；
Upper surface of the upper surface of the shallow trench isolation less than the isolation area, the both sides of the isolation area have switchback area,
The grid structure is covered in the surface in the switchback area.
2. semiconductor structure according to claim 1, it is characterised in that the section at fin portion (110) two ends is length
It is square；Or
The section at fin portion (210) two ends is triangle.
3. semiconductor structure according to claim 1, it is characterised in that the top surface in the fin portion is round and smooth curved surface.
4. semiconductor structure according to claim 1, it is characterised in that the width of fin portion top surface is received for 1-10
Rice.
5. semiconductor structure according to claim 1, it is characterised in that the structure is also included positioned at the grid structure
Both sides side wall.
6. semiconductor structure according to claim 1, it is characterised in that semiconductor structure is also included below source region；
And/or the isolation area below drain region.
7. semiconductor structure according to claim 1, it is characterised in that the isolation area is located under drain region and grid structure
In the fin portion of side.
8. semiconductor structure according to claim 1, it is characterised in that the isolation area is located at the lower section of grid structure,
With the equal length of grid structure.
9. semiconductor structure according to claim 1, it is characterised in that the isolation area is located at the lower section of grid structure,
Length of the isolation section length less than grid structure.
10. semiconductor structure according to claim 1, it is characterised in that there are multiple short isolation in the fin portion
Area.
11. semiconductor structures according to claim 1, it is characterised in that the material of the isolation area is SiO2And/or
HfO2。
12. semiconductor structures according to claim 1, it is characterised in that the thickness of the isolation area is 5-20nm.
13. semiconductor structures according to claim 10, it is characterised in that the length of the short isolation area is less than fin portion
4 times of width.
14. semiconductor structures according to claim 1, it is characterised in that including the sacrificial region being formed in fin portion, institute
State isolation area to be formed in the sacrificial region, the sacrificial region is exposed from the both sides in fin portion.
15. semiconductor structures according to claim 14, it is characterised in that the sacrificial region is through the sacrifice in fin portion
Layer.
16. semiconductor structures according to claim 14, it is characterised in that the sacrificial region is one or more sacrifices
Block.
17. semiconductor structures according to claim 14, it is characterised in that the thickness of the sacrificial region is 5-50nm.
18. semiconductor structures according to claim 1, it is characterised in that the fin portion includes fin portion, sacrificial region
With lower fin portion.
19. semiconductor structures according to claim 18, it is characterised in that the upper fin portion is with the basic of fillet
Cuboid or cylinder.
20. semiconductor structures according to claim 18, it is characterised in that the material in the lower fin portion is Si, sacrifices
It is Si that the material in area is SiGe, the material in upper fin portion.
21. semiconductor structures according to claim 18, it is characterised in that the material in the lower fin portion is Si, sacrifice
The material in area is SiGe, and the material in upper fin portion is the SiGe of Ge contents lower than sacrificial region 10%.
22. semiconductor structures according to claim 18, it is characterised in that the material of the sacrificial region is Ge contents 40%
SiGe, the material in the upper fin portion is the SiGe of Ge contents 30%.
23. semiconductor structures according to claim 20, it is characterised in that when the material in the upper fin portion is Si, fin
The surface in piece portion has a SiGe epitaxial layers.
24. semiconductor structures according to claim 23, it is characterised in that outside the SiGe epitaxial layers, also with one
Si epitaxial layers.
25. semiconductor structures according to claim 21, it is characterised in that when the material in the upper fin portion is SiGe,
The surface in fin portion has Si epitaxial layers.
26. semiconductor structures according to claim 24 or 25, it is characterised in that the thickness of the Si epitaxial layers is less than 5
Nanometer.
27. semiconductor structures according to claim 26, it is characterised in that this structure is adapted to make PMOS device.
28. semiconductor structures according to claim 1, it is characterised in that the switchback area is relative to fin portion two sides
A quarter of the distance of indentation less than fin portion width.
29. semiconductor structures according to claim 1, it is characterised in that the position that the switchback area is contacted with lower fin portion
Put with round and smooth curved surface.
30. semiconductor structures according to claim 1, it is characterised in that the grid structure covers the surface in switchback area,
And surround on the inside of fin portion.
A kind of 31. integrated chips, it is characterised in that the integrated chip it is integrated including：
Fin semiconductor structure described in claim 1；
Without isolation area fin semiconductor structure.
32. integrated chips according to claim 31, it is characterised in that described without isolation area fin semiconductor structure bag
Include：
Fin substrate with lower substrate and fin portion；
The source region being formed in fin portion and drain region；
It is formed between the source region and drain region across the grid structure in fin portion, the fin portion below grid structure is ditch
Road；
It is formed in the shallow trench isolation of fin portion both sides.
33. integrated chips according to claim 31, it is characterised in that described to include without isolation area fin semiconductor structure
The sacrificial region being formed in fin portion, the sacrificial region are exposed from the both sides in fin portion.
A kind of 34. methods for forming fin semiconductor structure, it is characterised in that comprise the following steps：
Step A, one substrate of offer, form the fin substrate with lower substrate and fin portion, and the fin portion includes sacrificial region；
Some or all of sacrificial region below step B, etching grid structure position is to form cavity, and fills out in the cavities
Fill insulant and form isolation area；
Insulant is continued to fill up, shallow trench isolation is formed；
Carry out that chemical machinery is flat, expose the upper surface in fin portion, etch shallow trench isolation, expose fin portion and isolation area
Top, carry out switchback process to isolation area, form switchback area；
Step C, the pseudo- grid structure being developed across above isolation area in fin portion simultaneously form side wall in pseudo- grid structure both sides,
Source region and drain region are formed in the fin portion of pseudo- grid structure both sides；
Step D, pseudo- grid structure is substituted using grid alternative techniques form metal-gate structures, metal-gate structures are covered in the table in switchback area
Face.
35. methods according to claim 34, it is characterised in that step A includes：One substrate is provided, is had in substrate
There is sacrificial region, the sacrificial region is the sacrifice layer through whole substrate；Etching barrier layer is formed on substrate, in etching barrier layer
Upper formation mask, etches the etching barrier layer with expose portion substrate, etches the substrate and forms fin portion, and fin portion has
Upper fin portion, sacrifice layer and lower fin portion.
36. methods according to claim 34, it is characterised in that step A includes：A substrate is provided, to the lining
Bottom carries out ion implanting and forms sacrificial region, and the sacrificial region is one or more sacrificial blocks；Etching barrier layer is formed on substrate,
Mask is formed on etching barrier layer, the etching barrier layer is etched with expose portion substrate, etch the substrate and form fin
Portion, fin portion have upper fin portion, sacrificial block and lower fin portion.
37. methods according to claim 34, it is characterised in that the thickness of the sacrificial region is 5-50nm.
38. methods according to claim 35 or 36, it is characterised in that step A includes：Etching forms fin portion,
The section at fin portion (110) two ends is triangle for the section at rectangle or the fin portion (210) two ends.
39. methods according to claim 35 or 36, it is characterised in that step A includes：Formation width is 1-10nm
Mask, control the width of fin portion top surface.
40. methods according to claim 35 or 36, it is characterised in that the material in the lower fin portion is Si, sacrificial region
Material be SiGe, the material in upper fin portion be Si.
41. methods according to claim 35 or 36, it is characterised in that the material in the lower fin portion is Si, sacrificial region
Material be SiGe, the material in upper fin portion be Ge contents lower than sacrificial region 10% SiGe.
42. methods according to claim 35 or 36, it is characterised in that the material of the sacrificial region is Ge contents 40%
SiGe, the material in upper fin portion is the SiGe of Ge contents 30%.
43. methods according to claim 34, it is characterised in that step B includes：Etch cavity uses multiple dry method
And/or wet-mixed etching, and plasma etching, wherein last time etching is wet etching.
44. methods according to claim 34, it is characterised in that step B includes：The height of cavity etching is 5-
20nm。
45. methods according to claim 34, it is characterised in that step B includes：In the diverse location shape in fin portion
Into one or more cavitys of different length.
46. methods according to claim 34, it is characterised in that etch shape in the fin portion below the position of drain region
Into cavity.
47. methods according to claim 34, it is characterised in that below drain region and part of grid pole structure position
In fin portion, etching forms cavity.
48. methods according to claim 34, it is characterised in that etching forms multiple short cavitys, the length of the short cavity
4 times less than fin portion width of degree.
49. methods according to claim 34, it is characterised in that the edge after step B has etched cavity, to cavity
Round and smooth process is carried out with the edge on fin portion top.
50. methods according to claim 49, it is characterised in that the method for the round and smooth process adopts isotropic etching
Or the annealing of lower more than 700 degrees Celsius of hydrogen environment.
51. methods according to claim 34, it is characterised in that step B includes：The insulant is SiO2With/
Or HfO2。
52. methods according to claim 40, it is characterised in that after the step B etches sacrificial area forms cavity, in fin
One layer of SiGe epitaxial layer of surface epitaxial growth of piece portion and cavity.
53. methods according to claim 52, it is characterised in that form one layer of Si in SiGe epitaxial layers Epitaxial growth again
Epitaxial layer.
54. methods according to claim 41, it is characterised in that after the step B etches sacrificial area forms cavity, in fin
One layer of Si epitaxial layer of surface epitaxial growth of piece portion and cavity.
55. methods according to claim 34, it is characterised in that step B before fill insulant, to fin
Portion carries out thermal oxidation, forms SiO on fin portion surface2, reduce or closed cavity.
56. methods according to claim 34, it is characterised in that when isolation area material is SiO2When, carved with Fluohydric acid. wet method
Erosion carries out switchback process.
57. methods according to claim 34, it is characterised in that the switchback area of formation is relative to the two sides indentation of fin portion
Distance less than fin portion width a quarter.
58. methods according to claim 34, it is characterised in that the step C-shaped into pseudo- grid structure cover switchback area
Surface, and on the inside of fin portion surround.
A kind of 59. methods for forming fin semiconductor structure, it is characterised in that comprise the following steps：
Step A, provide a long substrate, be pre-designed the quantity of construction featuress, length and the isolation area of individual devices, position and
Size；
The fin substrate of step B, formation with lower substrate and fin portion, the fin portion includes sacrificial region；
Some or all of sacrificial region below step C, the predetermined position of etching grid structure to form cavity, and in cavity
Middle fill insulant forms isolation area；
Insulant is continued to fill up, shallow trench isolation is formed；
Carry out that chemical machinery is flat, expose the upper surface in fin portion, etch shallow trench isolation, expose fin portion and isolation area
Top, carry out switchback process to isolation area, form switchback area；
Step D, fin substrate and shallow trench isolation are blocked by the device length being pre-designed；
Step E, the pseudo- grid structure being developed across above isolation area in fin portion simultaneously form side wall in pseudo- grid structure both sides,
Source region and drain region are formed in the fin portion of pseudo- grid structure both sides；
Step F, pseudo- grid structure is substituted using grid alternative techniques form metal-gate structures, metal-gate structures are covered in the table in switchback area
Face.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410135448.4A CN103904122B (en) | 2014-04-04 | 2014-04-04 | Fin-type semiconductor structure and forming method thereof |
| PCT/CN2015/075721 WO2015149705A1 (en) | 2014-04-04 | 2015-04-01 | Fin type semiconductor structure and forming method therefor |
| US15/301,464 US20170179275A1 (en) | 2014-04-04 | 2015-04-01 | Fin-type semiconductor structure and method for forming the same |
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| US10229856B2 (en) * | 2017-05-16 | 2019-03-12 | International Business Machines Corporation | Dual channel CMOS having common gate stacks |
| US10699967B2 (en) | 2018-06-28 | 2020-06-30 | International Business Machines Corporation | Co-integration of high carrier mobility PFET and NFET devices on the same substrate using low temperature condensation |
| CN111403469B (en) * | 2019-01-03 | 2023-09-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
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| CN101924133A (en) * | 2009-04-14 | 2010-12-22 | 台湾积体电路制造股份有限公司 | Fin FETs and forming method thereof |
| CN102117829A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | Fin type transistor structure and manufacturing method thereof |
| CN103594513A (en) * | 2012-08-16 | 2014-02-19 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN203895466U (en) * | 2014-04-04 | 2014-10-22 | 唐棕 | Fin type semiconductor structure |
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| CN101924133A (en) * | 2009-04-14 | 2010-12-22 | 台湾积体电路制造股份有限公司 | Fin FETs and forming method thereof |
| CN102117829A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | Fin type transistor structure and manufacturing method thereof |
| CN103594513A (en) * | 2012-08-16 | 2014-02-19 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN203895466U (en) * | 2014-04-04 | 2014-10-22 | 唐棕 | Fin type semiconductor structure |
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