CN111403469B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN111403469B
CN111403469B CN201910004931.1A CN201910004931A CN111403469B CN 111403469 B CN111403469 B CN 111403469B CN 201910004931 A CN201910004931 A CN 201910004931A CN 111403469 B CN111403469 B CN 111403469B
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region
source
drain
gate
forming
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CN111403469A (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention provides a semiconductor device including: a fin portion; the gate-all-around structure is formed above the fin part and surrounds part of the channel layer, and comprises a first gate structure and a second gate structure, and source/drain electrodes are arranged in the channel layers at two sides of the gate-all-around structure; and the isolation structure is arranged below the corresponding position of the source or the drain, and the second grid structure is contacted with the isolation structure. The isolation structure can block the current leakage channel, avoid electric leakage and improve the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor device and a method of forming the same.
Background
As semiconductor device dimensions continue to decrease, semiconductor device cells have evolved from conventional CMOS devices to the field of fin field effect transistors (finfets). However, as the physical size further decreases, finfets have failed to meet the demand. Gate-all-around (GAA) nanowire transistors have been favored by researchers. The gate-all-around structure can further increase the channel carrier migration rate, and meanwhile, the structure volume can be further reduced.
However, the current GAA structure is still easy to generate electric leakage, and has low working efficiency and poor performance.
Therefore, there is a need in the art for a semiconductor device and method for forming the same that avoids leakage of the gate-all-around transistor.
Disclosure of Invention
The embodiment of the invention discloses a method for forming a semiconductor device and the semiconductor device, wherein an isolation structure is formed below a source/drain corresponding position, so that a current leakage channel can be blocked, and leakage is avoided.
The present invention provides a semiconductor device including: a fin portion; the gate-all-around structure is formed above the fin part and surrounds part of the channel layer, and comprises a first gate structure and a second gate structure, and source/drain electrodes are arranged in the channel layers at two sides of the gate-all-around structure; and the isolation structure is arranged below the corresponding position of the source or the drain, and the second grid structure is contacted with the isolation structure.
According to one aspect of the invention, the isolation structure is disposed only under the source corresponding location or only under the drain corresponding location.
According to one aspect of the invention, isolation structures are disposed below the corresponding locations of the source and drain.
According to one aspect of the invention, the isolation structure is not in contact with the source or drain above the isolation structure.
According to one aspect of the invention, the thickness dimension of the isolation structure is t,3 nm.ltoreq.t.ltoreq.10 nm.
Correspondingly, the invention also discloses a method for forming the semiconductor device, which comprises the following steps: providing a fin; forming a sacrificial layer on the top of the fin part; forming a channel layer on the top of the sacrificial layer, wherein the channel layer comprises a first region, a second region and a third region, the first region and the third region are respectively positioned on two sides of the second region, and the sacrificial layer is at least in contact with the first region and the second region or at least in contact with the second region and the third region; forming a dummy gate structure positioned at the top of the second region; removing the sacrificial layer in contact with the first region or the third region to form a recess; forming an isolation structure in the groove; forming a source/drain inside the first region and the second region; and removing the dummy gate structure and the sacrificial layer contacting the second region to form a gate recess, and forming a gate-all-around structure in the gate recess.
According to one aspect of the present invention, after forming the channel layer, the sacrificial layer is in contact with the first region, the second region, and the third region.
According to one aspect of the present invention, grooves are formed on both sides of the sacrificial layer in contact with the second region.
According to one aspect of the invention, the process steps for forming the source/drain include: etching part of the first region and part of the third region to form a source/drain groove, wherein the bottom of the source/drain groove is not exposed out of the isolation structure; and forming a source/drain in the source/drain recess.
According to one aspect of the invention, the thickness dimension of the isolation structure formed is t, and t is more than or equal to 3nm and less than or equal to 10nm.
According to one aspect of the invention, the material forming the isolation structure comprises: siO (SiO) 2 SiON, siN, or a combination of two or more thereof.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the invention, a gate-all-around structure is formed above the fin portion and surrounds a portion of the channel layer. And the isolation structure is arranged below the corresponding position of the source or the drain, and the second grid structure is contacted with the isolation structure. The isolation structure is arranged, the second grid structure is in contact with the isolation structure, current generated between the source and the drain can be guaranteed to pass through the channel layer surrounded by the ring grid structure only, and cannot pass through the isolation structure to reach the lower side of the second grid structure, so that a current leakage channel is blocked, parasitic transistors are prevented from being formed, and the performance of the semiconductor device is improved.
Further, the isolation structure is arranged below the corresponding positions of the source and the drain. Isolation structures are arranged below corresponding positions of the source region and the drain region, so that a current leakage channel can be better blocked, and leakage current is avoided.
Accordingly, in the method for forming a semiconductor device disclosed by the invention, the channel layer comprises a first region, a second region and a third region, the first region and the third region are respectively positioned at two sides of the second region, and the sacrificial layer is at least contacted with the first region and the second region or at least contacted with the second region and the third region; forming a dummy gate structure positioned at the top of the second region; removing the sacrificial layer in contact with the first region or the third region to form a recess; forming an isolation structure in the groove; forming a source/drain inside the first region and the second region; and removing the dummy gate structure and the sacrificial layer in contact with the second region to form a gate recess, and forming a ring gate structure in the gate recess. After the source/drain is formed, the isolation structure is formed below the corresponding source or drain, and can block a current leakage channel of the device during operation, so that parasitic transistors are prevented from being formed between the gate-all-around structure and the fin portion, and the performance of the semiconductor device is improved.
Further, grooves are formed on both sides of the sacrificial layer contacting the second region. After the isolation structure is formed in the groove subsequently, the isolation structure is formed below the corresponding positions of the source region and the drain region simultaneously, so that a current leakage channel is better blocked, and the performance of the device is improved.
Further, etching part of the first region and part of the third region to form a source/drain groove, wherein the bottom of the source/drain groove is not exposed out of the isolation structure. The bottom of the source/drain recess does not expose the isolation structure, i.e., the bottom of the source/drain recess remains part of the channel layer, on which the source/drain can be grown relatively easily, making the process simpler and more convenient.
Drawings
Fig. 1 is a schematic cross-sectional structure after forming a dummy gate structure according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a groove formed in accordance with one embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of an isolation structure after formation according to one embodiment of the invention;
FIG. 4 is a schematic cross-sectional structure after source/drain formation in accordance with one embodiment of the present invention;
fig. 5 is a schematic cross-sectional structure after forming a gate recess according to an embodiment of the present invention;
FIG. 6a is a schematic cross-sectional structure after forming a gate-all-around structure in accordance with one embodiment of the present invention;
fig. 6b is a schematic cross-sectional view of another direction after forming a gate-all-around structure according to an embodiment of the present invention.
Detailed Description
As described above, the conventional semiconductor device has a problem of leakage.
It was found that the cause of the above problems is: the bottom of the gate-all-around structure and the bottom of the source/drain are directly adjacent to the fin, and because the source/drain is a structure shared by the gate-all-around structure, parasitic transistors are easily formed between the bottom of the gate-all-around structure and the source/drain, resulting in leakage.
In order to solve the problem, the invention provides a semiconductor device and a forming method thereof, wherein an isolation structure is formed below a corresponding position of a source/drain, so that a current leakage channel between the lower part of the source/drain and the bottom of a ring gate structure is blocked, the leakage phenomenon is prevented, and the performance of the semiconductor device is improved.
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of parts and steps, numerical expressions and numerical values set forth in these embodiments should not be construed as limiting the scope of the present invention unless it is specifically stated otherwise.
Furthermore, it should be understood that the dimensions of the various elements shown in the figures are not necessarily drawn to actual scale, e.g., the thickness or width of some layers may be exaggerated relative to other layers for ease of description.
The following description of the exemplary embodiment(s) is merely illustrative, and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but where applicable, should be considered part of the present specification.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined or illustrated in one figure, no further discussion thereof will be necessary in the description of the subsequent figures.
Referring to fig. 1, a sacrificial layer 110 is formed on a fin portion 100, a channel layer 120 is formed on the sacrificial layer 110, and a dummy gate structure 130 is formed on the channel layer 120.
The fin 100 is a bump on a semiconductor substrate (not shown). The material of the fin 100 is at least one of the following materials: polysilicon, silicon germanium, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and the like. In the embodiment of the present invention, the fin 100 is made of polysilicon. And other structures may be included in the semiconductor substrate, such as: the structures such as metal plugs, metal connection layers, dielectric layers, and the like, or other semiconductor devices including these structures, are not particularly limited herein.
The sacrificial layer 110 is formed on top of the fin 100 and occupies space for subsequent formation of isolation structures and/or gate-all-around structures.
Obviously, the sacrificial layer 110 needs to be removed later, so the material of the sacrificial layer 110 may meet the conditions that are different from the material of the fin portion 100 and that are easier to be etched, so that the subsequent removal is facilitated, and no specific limitation is made here.
A channel layer 120 is formed on top of the sacrificial layer 110 for subsequent source/drain and channel formation. In an embodiment of the present invention, the channel layer 120 includes three parts: the first region I, the second region II and the third region III are respectively positioned at two sides of the second region II, the distribution area division of the three parts is shown as a dotted line in fig. 1, source/drain is needed to be formed in the first region I and the third region III subsequently, and the second region II is used for forming a channel.
In an embodiment of the present invention, the sacrificial layer 110 is formed in contact with at least the first region i and the second region ii of the channel layer 120 or in contact with the second region ii and the third region iii. Specifically, in the embodiment of the present invention, the sacrificial layer 110 is in contact with the first region i, the second region ii, and the third region iii.
It should be noted that, in another embodiment of the present invention, the sacrificial layer 110 is only in contact with the first region i and the second region ii of the channel layer 120. In yet another embodiment of the present invention, the sacrificial layer 110 is in contact with only the second region ii and the third region iii.
The material of the channel layer 120 includes a (combined) material of a group iii-v element, such as one or more of Si, siC, gaN, inGaP, inP, gaAs. Specifically, in the embodiment of the present invention, the material of the channel layer 120 is Si.
The dummy gate structure 130 occupies space for the subsequent formation of a ring gate structure. The dummy gate structure 130 is formed on top of the second region ii.
Due to the special structure of the fin transistor, the dummy gate structure 130 and the sacrificial layer 110 are in contact for subsequent formation of the gate recess.
The embodiment of the invention further comprises grid side walls 140 formed on two sides of the pseudo grid structure, which are used for protecting the pseudo grid structure 130 and the subsequently formed ring grid structure from being damaged or destroyed by the process.
Referring to fig. 2, a portion of the sacrificial layer 110 is etched to form a recess 11.
For clarity of illustration, starting with fig. 2, the three area boundaries (dashed lines) of the channel layer 120 are no longer extended to the channel layer 120, as shown in fig. 1 for a specific division.
The grooves 11 are formed for forming isolation structures therein.
In the embodiment of the present invention, the recess 11 is formed by etching the sacrificial layer 110 in contact with the first region i of the channel layer 120 or by etching the sacrificial layer 110 in contact with the third region iii. Specifically, in the embodiment of the present invention, since the sacrificial layer 110 is in contact with the first region i, the second region ii and the third region iii, the grooves 11 are formed by etching the sacrificial layer 110 in contact with the first region i and the third region iii, i.e., the grooves 11 are distributed on both sides of the sacrificial layer 110 in contact with the second region ii. Obviously, the remaining sacrificial layer 110 is in contact with the second region ii. In another embodiment of the present invention, the recess 11 may be formed by etching only the sacrificial layer 110 in contact with the first region i or by etching only the sacrificial layer 110 in contact with the third region iii, i.e., the sacrificial layer 110 in contact with the second region ii and the third region iii is maintained or the sacrificial layer 110 in contact with the first region i and the second region ii is maintained, without being particularly limited thereto.
As previously described, in still another embodiment of the present invention, when the sacrificial layer 110 is in contact with only the first region i and the second region ii, it is apparent that the recess 11 is formed by etching only the sacrificial layer 110 in contact with the first region i. In yet another embodiment of the present invention, when the sacrificial layer 110 is in contact with only the second region ii and the third region iii, it is apparent that the recess 11 is formed by etching only the sacrificial layer 110 in contact with the third region iii.
In the embodiment of the present invention, since the gate-all-around structure is formed at the position of the sacrificial layer 110 contacting the second region ii, it is necessary to leave the remaining sacrificial layer 110 in this portion when forming the recess 11.
The width dimension of the remaining sacrificial layer 110 is not particularly limited in the embodiments of the present invention, as long as the remaining width can satisfy the condition of realizing the subsequent gate-all-around structure function.
Obviously, after forming the recess 11, the first region i and the third region iii of the channel layer 120 are separated from the fin 100 to form the floating channel layer 120. The floating channel layer 120 is equivalent to forming a floating source/drain after the source/drain is subsequently formed, thereby achieving isolation of the source or drain from the fin 100.
Referring to fig. 3, an isolation structure 150 is formed in the recess.
The isolation structure 150 is used to block the current leakage path, reduce leakage, and improve the performance of the semiconductor device.
The isolation structures 150 are formed in the recesses described above. For the specific location of the isolation structure 150, please refer to the location of the groove. In an embodiment of the present invention, the isolation structures 150 are formed on both sides of the remaining sacrificial layer 110.
The material of the isolation structure 150 is adapted to the material of the channel layer 120, so as to be easy to form, ensure that the internal structure of the formed isolation structure 150 is compact, and improve the isolation blocking effect. The material of the isolation structure 150 includes SiO 2 SiON, siN, or a combination of two or more thereof. Specifically, in the embodiment of the present invention, the material of the isolation structure 150 is SiO 2 . In another embodiment of the present invention, the material of the isolation structure 150 is SiN.
Note that, in different embodiments, since the material of the channel layer 120 may be different, the material of the isolation structure 150 is not particularly limited herein, as long as the condition of blocking the current leakage path can be satisfied.
The thickness dimension of the isolation structure 150 is t, and t is more than or equal to 3nm and less than or equal to 10nm. If too thin, the isolation effect on the current is poor and it is also relatively difficult to form. If too thick, the process and material costs are increased while the insulation effect is ensured. Thus, in the present embodiment, t=5 nm. In another embodiment of the invention, t=8 nm.
Referring to fig. 4, a source region 161 and a drain region 162 are formed.
In the embodiment of the present invention, the source region 161 and the drain region 162 are only for convenience of description, and do not represent that the source region 161 or the drain region 162 is formed at a specific location, and need to be defined according to specific semiconductor device properties. And in an embodiment of the present invention, the source region 161 and the drain region 162 are referred to as source/drain.
The process steps for forming the source/drain include: etching portions of the channel layer 120 of the first region i and the third region iii to form source/drain recesses; and forming a source/drain in the source/drain recess. The process of forming the source/drain includes a conventional epitaxial growth process.
Specifically, in the embodiment of the present invention, after the source/drain recess is formed, the isolation structure 150 is not exposed at the bottom of the source/drain recess, i.e., the bottom of the source/drain recess remains a part of the channel layer 120. To facilitate the formation of source/drains, similar elements are typically present in the source/drain and channel layer 120 materials. Therefore, by directly growing the source/drain on the channel layer 120 at the bottom of the source/drain groove, the source/drain can be formed more easily, and the structure for forming the source/drain is more compact.
It should be noted that, in other embodiments of the present invention, the bottom of the source/drain recess may also expose the isolation structure 150, so long as a suitable source/drain material and a suitable forming process are selected, a source/drain with a better structure may also be formed, which is not limited herein.
Referring to fig. 5, a gate recess 13 is formed.
Forming the gate recess 13 facilitates subsequent formation of a gate-all-around structure therein.
The process of forming the gate recess 13 includes: the dummy gate structure and the remaining sacrificial layer are etched away. Due to the special structure of the fin transistor, after the gate recess 13 is formed, a portion of the second region ii of the channel layer 120 for forming a channel is exposed.
Referring to fig. 6a and 6b, a gate-all-around structure 170 is formed in the gate recess 13.
As shown in fig. 6a, after forming the gate-all-around structure, the gate-all-around structure includes a first gate structure 171 and a second gate structure 172. The first gate structure 171 is located above the channel layer 120, the second gate structure 172 is located between the fin 100 and the channel layer 120, and the second gate structure 172 is in contact with the isolation structure 150. Specifically, in the embodiment of the present invention, the isolation structures 150 are respectively formed on two sides of the second gate structure 172, and the second gate structure 172 contacts with the isolation structures 150 on two sides. After the isolation structure 150 is contacted with the second gate structure 172, a leakage current loop cannot be formed on the outer sides of the second gate structure 172 and the isolation structure 150 when the device works, so that leakage current can be effectively prevented, and the electrical performance of the device is improved.
Obviously, the second gate structure 172 may only contact with the isolation structure 150 on one side thereof, and the complete leakage current loop cannot be formed, so as to achieve the effect of blocking the leakage current channel. But it must be ensured that the second gate structure 172 is in contact with the isolation structure 150. If the two are not contacted, a leakage current leakage channel can be formed in the device, and the target effect is not achieved.
After the gate-all-around structure is formed, the second gate structure 172 contacts the isolation structure 150, and when the device is in operation, carriers only migrate in the channel layer 120 surrounded by the gate-all-around structure due to the formation of the isolation structure 150, but do not cross the isolation structure 150, and flow between the second gate structure 172 and the fin portion 100, thereby blocking the flow channel of leakage current, avoiding the formation of parasitic transistors, and improving the performance of the semiconductor device.
As previously mentioned, the locations of the sacrificial layer distribution are not the same in different embodiments of the present invention. However, it is obvious that the isolation structure 150 is formed at a position corresponding to the lower portion of the source region 161 or the drain region 162, so that a leakage path of the leakage current can be blocked, and a leakage current formation path can be avoided. In the embodiment of the present invention, isolation structures 150 are formed at corresponding positions under the source region 161 and the drain region 162.
FIG. 6b is a schematic cross-sectional structure taken along section line A-A' of FIG. 6 a. Obviously, channel layer 120 is adjacently surrounded by gate-all-around structure 170. The boundary between the first gate structure 171 and the second gate structure 172 is shown as a dashed line in fig. 6 b.
In an embodiment of the present invention, the interior of the ring gate structure 170 further includes conventional metal gate structures such as a high-k dielectric layer (not shown), a work function layer (not shown), and a metal gate (not shown).
In the method for forming the semiconductor device, an isolation structure is not arranged between the formed gate-all-around structure and the fin portion. Because the channel layer and the source/drain are shared by the gate-all-around structure, the gate-all-around structure at the bottom and the source/drain at the two sides of the gate-all-around structure can form parasitic transistors in the area close to the fin part, namely, a channel for the circulation of carriers is formed below the gate-all-around structure at the bottom, so that leakage current is generated, and the performance of the semiconductor device is reduced.
In the method for forming the semiconductor device, an isolation structure is formed between the source/drain and the fin part, and meanwhile, the bottom part of the ring gate structure is contacted with the isolation structure, so that a current leakage channel is blocked, parasitic transistors are avoided, and the performance of the semiconductor device is improved.
In summary, the embodiment of the invention discloses a method for forming a semiconductor device, which forms an isolation structure at a corresponding position below a source/drain, blocks a current leakage channel, avoids the generation of a parasitic transistor, and improves the performance of the semiconductor device.
Accordingly, referring to fig. 6a and 6b, the embodiment of the present invention further provides a semiconductor device, including: fin 100, gate all around structure 170, channel layer 120, and isolation structure 150.
The fin 100 is a bump on a semiconductor substrate (not shown). The material of the fin 100 is at least one of the following materials: polysilicon, silicon germanium, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and the like. In the embodiment of the present invention, the fin 100 is made of polysilicon. And other structures may be included in the semiconductor substrate, such as: the structures such as metal plugs, metal connection layers, dielectric layers, and the like, or other semiconductor devices including these structures, are not particularly limited herein.
The gate-all-around structure 170 is used to control the turn-on and turn-off of the circuit. A gate-all-around structure 170 is formed over the fin 100.
In an embodiment of the present invention, the gate-all-around structure 170 includes a first gate structure 171 and a second gate structure 172, and the boundary between the two is shown as a dotted line in fig. 6 b.
The interior of the ring gate structure 170 also includes conventional metal gate structures such as a high-k dielectric layer (not shown), a work function layer (not shown), and a metal gate (not shown).
The channel layer 120 is used to form a channel when the device is in operation. In an embodiment of the present invention, the channel layer 120 is surrounded by a ring gate structure 170, as shown in fig. 6 b.
The material of the channel layer 120 includes a (combined) material of a group iii-v element, such as one or more of Si, siC, gaN, inGaP, inP, gaAs. Specifically, in the embodiment of the present invention, the material of the channel layer 120 is Si.
In the embodiment of the present invention, the source region 161 and the drain region 162 are further disposed in the channel layer 120 at both sides of the gate-all-around structure 170. The source region 161 and the drain region 162 are only for convenience of description and do not represent a region formed at a specific location, specifically, whether the source region 161 or the drain region 162, needs to be defined according to specific semiconductor device properties. And in an embodiment of the present invention, the source region 161 and the drain region 162 are referred to as source/drain.
The isolation structure 150 is used for blocking the channel of leakage current conduction, and preventing leakage.
The isolation structures 150 are disposed at corresponding locations under the source/drain. In the embodiment of the present invention, the isolation structure 150 is disposed only under the position corresponding to the source region 161, or only under the position corresponding to the drain region 162, or both the source region 161 and the drain region 162. Specifically, in the embodiment of the present invention, the isolation structures 150 are disposed at corresponding positions under the source region 161 and the drain region 162 at the same time.
In an embodiment of the present invention, the second gate structure 172 is in contact with the isolation structure 150. The contact arrangement of the two can block the leakage channel of the leakage current, avoid forming parasitic transistors below the ring gate structure 170 and between the fin parts, and reduce the performance of the semiconductor device.
In other embodiments of the present invention, the second gate structure 172 may also be in contact with the isolation structure 150 on only one side thereof. But it must be ensured that the two are in contact and if not in contact, a leakage path for leakage current still occurs, resulting in leakage.
The material of the isolation structure 150 is adapted to the material of the channel layer 120, so as to be easy to form, ensure that the internal structure of the formed isolation structure 150 is compact, and improve the isolation blocking effect. The material of the isolation structure 150 includes SiO 2 SiON, siN, or a combination of two or more thereof. Specifically, in the embodiment of the present invention, the material of the isolation structure 150 is SiO 2 . In another embodiment of the present invention, the material of the isolation structure 150 is SiN.
Note that, in different embodiments, since the material of the channel layer 120 may be different, the material of the isolation structure 150 is not particularly limited herein, as long as the condition of blocking the current leakage path can be satisfied.
The thickness dimension of the isolation structure 150 is t, and t is more than or equal to 3nm and less than or equal to 10nm. If too thin, the isolation effect on the current is poor and it is also relatively difficult to form. If too thick, the process and material costs are increased while the insulation effect is ensured. Thus, in the present embodiment, t=5 nm. In another embodiment of the invention, t=8 nm.
In the embodiment of the present invention, a channel layer 120 is further disposed between the source/drain and the isolation structure 150 corresponding to the source/drain. It is easier to grow the source/drain directly on the channel layer 120 and the source/drain structure is relatively dense.
It should be noted that, in other embodiments of the present invention, the source/drain may also directly contact the isolation structure 150, which is not particularly limited herein.
In summary, in the semiconductor device provided by the embodiment of the invention, the isolation structure is formed below the corresponding position of the source/drain, so that the current leakage channel can be blocked, the formation of the parasitic transistor is avoided, and the performance of the semiconductor device is improved.
The present invention has been described in detail so far. In order to avoid obscuring the concepts of the invention, some details known in the art have not been described. How to implement the solutions disclosed herein will be fully apparent to those skilled in the art from the above description.
While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims (10)

1. A semiconductor device, comprising:
a fin portion;
the gate-all-around structure is formed above the fin part and surrounds part of the channel layer, the gate-all-around structure comprises a first gate structure and a second gate structure, and source/drain is further arranged in the channel layer at two sides of the gate-all-around structure; and
an isolation structure arranged below the corresponding position of the source or the drain, wherein the second grid structure is contacted with the isolation structure, and the material of the isolation structure comprises SiO 2 SiON, siN, or a combination of two or more thereof.
2. The semiconductor device of claim 1, wherein the isolation structure is disposed only under the source-corresponding location or only under the drain-corresponding location.
3. The semiconductor device of claim 1, wherein the isolation structure is disposed below the source and drain corresponding locations.
4. The semiconductor device of claim 1, wherein the isolation structure and the source or the drain above the isolation structure are not in contact.
5. The semiconductor device of claim 1, wherein the thickness dimension of the isolation structure is t,3 nm.ltoreq.t.ltoreq.10 nm.
6. A method of forming a semiconductor device, comprising:
providing a fin;
forming a sacrificial layer on the top of the fin part;
forming a channel layer on top of the sacrificial layer, wherein the channel layer comprises a first region, a second region and a third region, the first region and the third region are respectively positioned on two sides of the second region, and the sacrificial layer is at least in contact with the first region and the second region or at least in contact with the second region and the third region;
forming a pseudo gate structure positioned at the top of the second region;
removing the sacrificial layer in contact with the first region or the third region to form a recess; forming an isolation structure in the groove, wherein the material for forming the isolation structure comprises the following components: siO (SiO) 2 SiON, siN, or a combination of two or more thereof;
forming a source/drain inside the first region and the second region; and
and removing the dummy gate structure and the sacrificial layer in contact with the second region to form a gate groove, and forming a ring gate structure in the gate groove.
7. The method for forming a semiconductor device according to claim 6, wherein after the channel layer is formed, the sacrificial layer is in contact with the first region, the second region, and the third region.
8. The method of forming a semiconductor device according to claim 7, wherein the grooves are formed on both sides of the sacrificial layer in contact with the second region.
9. The method of forming a semiconductor device according to claim 6, wherein the step of forming the source/drain includes:
etching part of the first region and part of the third region to form a source/drain groove, wherein the bottom of the source/drain groove is not exposed out of the isolation structure; and
and forming the source/drain in the source/drain groove.
10. The method of forming a semiconductor device according to claim 6, wherein a thickness dimension of the isolation structure formed is t,3 nm.ltoreq.t.ltoreq.10 nm.
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Citations (2)

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Publication number Priority date Publication date Assignee Title
CN103904122A (en) * 2014-04-04 2014-07-02 唐棕 Fin-type semiconductor structure and forming method thereof
CN106486532A (en) * 2015-08-26 2017-03-08 中芯国际集成电路制造(上海)有限公司 The forming method of ring gate field-effect transistor

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Publication number Priority date Publication date Assignee Title
US9443978B2 (en) * 2014-07-14 2016-09-13 Samsung Electronics Co., Ltd. Semiconductor device having gate-all-around transistor and method of manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103904122A (en) * 2014-04-04 2014-07-02 唐棕 Fin-type semiconductor structure and forming method thereof
CN106486532A (en) * 2015-08-26 2017-03-08 中芯国际集成电路制造(上海)有限公司 The forming method of ring gate field-effect transistor

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