CN103904057B - PoP encapsulates structure and manufacturing process - Google Patents
PoP encapsulates structure and manufacturing process Download PDFInfo
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- CN103904057B CN103904057B CN201410129744.3A CN201410129744A CN103904057B CN 103904057 B CN103904057 B CN 103904057B CN 201410129744 A CN201410129744 A CN 201410129744A CN 103904057 B CN103904057 B CN 103904057B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Abstract
The present invention relates to a kind of PoP and encapsulate structure and manufacturing process, it is characterized in that, when fan-out package unit makes, adopt chip front side technical process upward, by making metal level on slide glass, then press the arrangement position fluting of chip and need by design to make and the electrode of other encapsulation unit interconnection, thus change the internal structure of fan-out-type wafer-level packaging, strengthen its rigidity and coefficient of thermal expansion so that the warpage of whole wafer and the slippage, the dislocation that cause because of plastic cement harmomegathus are controlled. In back side perforate after plastic packaging, filler metal, the electrode formed with metal level before forms interconnection, and metal level exposes at the capsulation material back side after removing slide glass and adhesive-layer, can make metal pad. Such encapsulation unit can be connected by the metal pad at the encapsulation unit back side and other encapsulation unit, forms multilayer PoP encapsulation knot and forms.
Description
Technical field
The present invention relates to a kind of PoP and encapsulate structure and manufacturing process, belong to technical field of semiconductor encapsulation.
Background technology
As the at present highly dense integrated main mode of encapsulation, PoP(packageonpackage, laminate packaging) obtain the attention that gets more and more. Chip stacking is improved between the main approach of Electronic Packaging high densification, and PoP design in the industry cycle has obtained comparing development and application widely. At present, adopting the PoP solution of the fan-out package of plastic packaging (molding) technique very difficult in warpage (warpage) control, the solution of prior art is all from material behavior, the final shape aspect of plastic packaging to reduce warpage; The slippage, the dislocation (shift) that cause because of plastic cement (EMC) harmomegathus in addition also are difficult to be controlled.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, it is provided that a kind of PoP encapsulates structure and manufacturing process, it is possible to more effectively improve warpage, and simple.
According to technical scheme provided by the invention, described PoP encapsulates structure, comprise upper and lower two layers of fan-out package unit, it is characterized in that: described fan-out package unit comprises and becomes an entirety with chip and metal level, chip and the metal level of the first metal electrode and the 2nd metal electrode by capsulation material plastic packaging; The front of described chip and the front of capsulation material are positioned at same plane, and the back side of chip and the back side of capsulation material are positioned at same plane; The capsulation material of described metal level region makes vertical through hole, fill in vertical through hole and form metal post, first surface of metal post is positioned at same plane with the front of capsulation material, 2nd surface of metal post is connected with the first surface of metal level, and the 2nd surface of metal level is positioned at same plane with the back side of capsulation material; In the front of described capsulation material, the first dielectric layer is set, first dielectric layer is arranged wiring metal routing layer and ubm layer again, ubm layer is put weldering ball, then wiring metal routing layer connects the first metal electrode, the 2nd metal electrode and ubm layer; 2nd dielectric layer is set at the back side of described capsulation material, the 2nd dielectric layer is arranged back side wiring metal routing layer and back side ubm layer again, the back side again wiring metal routing layer be connected with metal level; The weldering ball of described upper strata fan-out package unit is connected with the back side ubm layer of lower floor's fan-out package unit.
The outside surface of described ubm layer and the flush with outer surface of the first dielectric layer, or protrude from the outside surface of the first dielectric layer.
The outside surface of described back side ubm layer and the flush with outer surface of the 2nd dielectric layer, or protrude from the outside surface of the 2nd dielectric layer.
Described PoP encapsulates the manufacturing process of structure, it is characterized in that, adopts following processing step:
(1) prepare carrier disk, apply the first adhesive-layer at carrier disk upper surface, and make metal level, make through hole on the metal layer, expose the upper surface of carrier disk; At via bottoms coating the 2nd adhesive-layer of metal level, the front of chip is pasted on carrier disk upward;
(2) by metal level, chip plastic packaging in capsulation material, and ensureing that the front of chip and the front of capsulation material are positioned at same plane, the back side of chip and the back side of capsulation material are positioned at same plane;
(3) making vertical through hole on the capsulation material obtained in step (2), expose the first surface of metal level, filled conductive material in through hole, forms metal post;
(4) front surface coated first dielectric layer of the capsulation material obtained in step (3), makes wiring metal routing layer again on the first dielectric layer, then wiring metal routing layer connects the first metal electrode and the 2nd metal electrode;
(5) remove carrier disk and adhesive-layer, expose the back side of chip; At the upper surface coating dielectric layer of wiring metal routing layer again, and making ubm layer in the dielectric layer, ubm layer embeds in dielectric layer, is connected with wiring metal routing layer again;
(6) on ubm layer, plant ball backflow, form solder bumps array;
(7) backside coating the 2nd dielectric layer of the capsulation material obtained in step (6), makes back side wiring metal routing layer and back side ubm layer again on the 2nd dielectric layer, obtains fan-out package unit;
(8) two fan-out package unit are carried out stacking, backflow, obtain three-dimensional stacked PoP and encapsulate structure.
Described chip is by the IC Wafer Thinning with multiple chip and cuts.
Described metal level adopts sputtering, deposition or electric plating method making to obtain, or adopts the mode directly pasting tinsel/sheet or metal otter board to make.
The operation of described step (1) operates replacement below adopting: apply the first adhesive-layer at carrier disk upper surface, pastes the metal level that preprocessing has through hole, then is pasted on upward on carrier disk in the front of chip.
PoP of the present invention encapsulates structure and manufacturing process and fan-out package is applied to PoP encapsulates structure, encapsulates the encapsulation unit in structure as PoP, effectively improves warpage and slippage dislocation that capsulation material harmomegathus causes, and simple; Simultaneously in the part of the upper and lower packaging interconnection of PoP, the filling of metal through hole is also more easy.
Accompanying drawing explanation
Fig. 1 a is the schematic diagram of described IC disk.
Fig. 1 b is the cutting schematic diagram of described IC disk.
Fig. 1 c is the schematic diagram after described IC disk cuts.
Fig. 2 is the schematic diagram making metal level on described carrier disk.
Fig. 3 is the schematic diagram making through hole on described metal level.
Fig. 4 is the schematic diagram of the via bottoms adhering chip at described metal level.
Fig. 5 is by schematic diagram in capsulation material of metal level, chip plastic packaging.
Fig. 6 is the schematic diagram manufacturing through hole on capsulation material.
Fig. 7 is the schematic diagram obtaining metal post.
Fig. 8 is the schematic diagram obtaining the first dielectric layer and figure opening.
Fig. 9 is the schematic diagram obtaining wiring metal routing layer again.
Figure 10 is the schematic diagram obtaining ubm layer.
Figure 11 a is the schematic diagram obtaining welding the first embodiment of ball.
Figure 11 b is the schematic diagram obtaining welding the 2nd kind of embodiment of ball.
Figure 12 a is the schematic diagram of the first embodiment obtaining fan-out package unit.
Figure 12 b is the schematic diagram of the 2nd kind of embodiment obtaining fan-out package unit.
Figure 13 a is the schematic diagram of the first embodiment obtaining PoP encapsulation structure.
Figure 13 b is the schematic diagram of the 2nd kind of embodiment obtaining PoP encapsulation structure.
In figure, sequence number is: chip 100, IC disk 101, first metal electrode 102a, the 2nd metal electrode 102b, slide glass disk 201, first adhesive-layer 202, the 2nd adhesive-layer 202a, metal level 203, capsulation material 501, metal post 701, first dielectric layer 901, the 2nd dielectric layer 902, figure opening 1001, again wiring metal routing layer 1101, the back side again wiring metal routing layer 1102, ubm layer 1201, back side ubm layer 1202, weldering ball 1301.
Embodiment
Below in conjunction with concrete accompanying drawing, the invention will be further described.
As shown in Figure 13 a, Figure 13 b: as described in PoP encapsulate structure comprise upper and lower two layers of fan-out package unit; Described fan-out package unit comprises the chip 100 with the first metal electrode 102a and the 2nd metal electrode 102b and metal level 203, chip 100 and metal level 203 become an entirety by capsulation material 501 plastic packaging; The front 100a of described the chip 100 and front 501a of capsulation material 501 is positioned at same plane, and the back side 100b of the chip 100 and back side 501b of capsulation material 501 is positioned at same plane; The capsulation material 501 of described metal level 203 region makes vertical through hole, fill in vertical through hole and form metal post 701, first surface 701a of metal the post 701 and front 501a of capsulation material 501 is positioned at same plane, 2nd surface 701b of metal post 701 is connected with the first surface 203a of metal level 203, and the 2nd surface 203b of the metal level 203 and back side 501b of capsulation material 501 is positioned at same plane; At the front 501a of described capsulation material 501, the first dielectric layer 901 is set, first dielectric layer 901 is arranged wiring metal routing layer 1101 and ubm layer 1201 again, ubm layer 1201 is put weldering ball 1301, then wiring metal routing layer 1101 connects the first metal electrode 102a, the 2nd metal electrode 102b and ubm layer 1201; Arrange at the back side 501b of described capsulation material 501 and the 2nd dielectric layer the 902, two dielectric layer 902 arranged back side wiring metal routing layer 1102 and back side ubm layer 1202 again, the back side again wiring metal routing layer 1102 be connected with metal level 203; The weldering ball 1301 of described upper strata fan-out package unit is connected with the back side ubm layer 1202 of lower floor's fan-out package unit, it is achieved the electrical interconnection of levels fan-out package unit;
The outside surface 1201a of described ubm layer 1201 is concordant with the outside surface 901a of the first dielectric layer 901, or protrudes from the outside surface 901a of the first dielectric layer 901; The outside surface 1202a of described back side ubm layer 1202 is concordant with the outside surface 902a of the 2nd dielectric layer 902, or protrudes from the outside surface 902a of the 2nd dielectric layer 902.
Described PoP encapsulates the manufacturing process of structure, adopts following processing step:
(1) as shown in Fig. 1 a, Fig. 1 b, Fig. 1 c, it is provided that IC disk 101, IC disk 101 comprises multiple chip 100, above-mentioned IC disk 101 is subtracted thin and cut into the chip 100 of single;
(2) as shown in Figure 2, preparing carrier disk 201, carrier disk 201 can be metal, wafer, glass, organic materials etc., and the upper surface at carrier disk 201 applies the first adhesive-layer 202, and makes metal level 203; Described metal level 203 can adopt the method making such as sputtering, deposition or plating to obtain, or adopts the mode directly pasting tinsel/sheet or metal otter board to make; The selection of metal level 203 is in height low than the height of chip 100;
(3) as shown in Figure 3, making through hole on the metal level 203 that step (2) obtains, shape of through holes is square or circular, and size size is relevant to the size of chip 100, exposes the upper surface of carrier disk 201;
As shown in Figure 4, (4) in via bottoms coating the 2nd adhesive-layer 202a of the metal level 203 that step (3) obtains, the front 100a of chip 100 is pasted on carrier disk 201 upward; (need the etching through hole operation carrying out step (3) when the metal level 203 adopting whole plate to make, and apply the 2nd adhesive-layer 202a, in order to adhering chip 100; When adopting the metal sheet/sheet of preprocessing sky as metal level 203, it is not necessary to carry out the etching through hole operation of step (3), after applying the first adhesive-layer 202, paste metal level 203 and chip 100 successively);
(5) as shown in Figure 5, metal level 203 in step (4), chip 100 is as a whole by capsulation material 501 plastic packaging, and ensureing that the front 100a of the chip 100 and front 501a of capsulation material 501 is positioned at same plane, the back side 100b of the chip 100 and back side 501b of capsulation material 501 is positioned at same plane; Owing to the height of metal level 203 is less than the height of chip 100, thus the front 100a of the first of metal level 203 the surface 203a and chip 100 is in Different Plane, and the 2nd surface 203b of the metal level 203 and back side 100b of chip is in same plane;
(6) as shown in Figure 6, the capsulation material 501 that step (5) obtains makes vertical through hole, expose the first surface 203a of metal level 203; The manufacture craft of vertical through hole can adopt machine drilling, laser boring or adopt mould directly to form vertical through hole in Shooting Technique; The shape of vertical through hole can be circular hole or square hole;
(7) as shown in Figure 7, adopt mode filled conductive material in the through hole that step (6) obtains of plating, electroless plating or sputtering, form metal post 701;
As shown in Figure 8, (8) material that the front 501a of the capsulation material 501 obtained in step (7) applies the first dielectric layer 901, first dielectric layer 901 can be selected from solder resist, polyimide, polybenzoxazoles, moulding compound etc.; First dielectric layer 901 offers figure opening 1001;
(9) as shown in Figure 9, first dielectric layer 901 in capsulation material 501 front that step (8) obtains makes individual layer or multilayer wiring metal routing layer 1101 again, then wiring metal routing layer 1101 connects the first metal electrode 102a and the 2nd metal electrode 102b by figure opening 1001;
(10) as shown in Figure 10, the capsulation material 501 that step (9) is obtained by subtracting the methods such as thin, etching remove carrier disk 201, clean and remove adhesive-layer, expose the back side 100b of chip 100; At the upper surface coating dielectric layer of wiring metal routing layer 1101 again, and obtain ubm layer (UBM) 1201 by the method such as optical mask, etching in the dielectric layer; Ubm layer 1201 embeds in dielectric layer 901, is connected with wiring metal routing layer 1101 again; The outside surface 1201a of ubm layer 1201 is concordant with the outside surface 901a of the first dielectric layer 901, or protrudes from the outside surface 901a of the first dielectric layer 901;
(11) as shown in Figure 11 a, Figure 11 b, the ubm layer 1201 that step (8) obtains is planted ball backflow, form the weldering convex lattice array of ball 1301;
Wherein, when step (3) makes through hole on metal level 203, metal level 203 makes different through holes to form Figure 11 a metal level different with Figure 11 b 203 structure;
Or, when step (3) adopts the metal sheet/sheet of preprocessing sky as metal level 203, according to the shape of the metal sheet/sheet of different preprocessings, obtain Figure 11 a, Figure 11 b different metal level 203 structure;
(12) as shown in Figure 12 a, Figure 12 b, in back side 501b coating the 2nd dielectric layer 902 of the capsulation material 501 that step (11) obtains, 2nd dielectric layer 902 makes back side wiring metal routing layer 1102 and back side ubm layer 1202 again, obtains the fan-out package unit as shown in Figure 12 a, Figure 12 b; The described back side again wiring metal routing layer 1102 be connected with metal level 203, the outside surface 1202a of back side ubm layer 1202 is concordant with the outside surface 902a of the 2nd dielectric layer 902, or protrudes from the outside surface 902a of the 2nd dielectric layer 902;
(13) the fan-out package unit that two steps (12) obtain is carried out stacking, backflow, obtain three-dimensional stacked PoP and encapsulate structure. As depicted in fig. 13 a, it is that the fan-out package unit of two Figure 12 a is carried out stacking; As illustrated in fig. 13b, it is that the fan-out package unit of two Figure 12 b is carried out stacking.
The present invention is when fan-out package unit makes, adopt chip front side technical process upward, by making metal level on slide glass (carrierwafer), then press the arrangement position fluting of chip and need by design to make and the electrode of other encapsulation unit interconnection, thus change the internal structure of fan-out-type wafer-level packaging (fanoutWLP), strengthen its rigidity and coefficient of thermal expansion so that the warpage (warpage) of whole wafer (wafer) and the slippage, the dislocation (shift) that cause because of plastic cement (EMC) harmomegathus are controlled. Plastic packaging (Molding) is later in back side perforate, and filler metal, the electrode formed with metal level before forms interconnection, and metal level exposes at the capsulation material back side after removing slide glass and adhesive-layer, can make metal pad. Such encapsulation unit can be connected by the metal pad at the encapsulation unit back side and other encapsulation unit, forms multilayer PoP encapsulation knot and forms.
Claims (7)
1. a PoP encapsulates structure, comprise upper and lower two layers of fan-out package unit, it is characterized in that: described fan-out package unit comprises the chip (100) with the first metal electrode (102a) and the 2nd metal electrode (102b) and metal level (203), and chip (100) becomes an entirety with metal level (203) by capsulation material (501) plastic packaging; The front (100a) of described chip (100) and the front (501a) of capsulation material (501) are positioned at same plane, and the back side (100b) of chip (100) and the back side (501b) of capsulation material (501) are positioned at same plane; The capsulation material (501) of described metal level (203) region makes vertical through hole, fill in vertical through hole and form metal post (701), first surface (701a) of metal post (701) and the front (501a) of capsulation material (501) are positioned at same plane, 2nd surface (701b) of metal post (701) is connected with first surface (203a) of metal level (203), and the 2nd surface (203b) of metal level (203) and the back side (501b) of capsulation material (501) are positioned at same plane; In the front (501a) of described capsulation material (501), the first dielectric layer (901) is set, first dielectric layer (901) is arranged wiring metal routing layer (1101) and ubm layer (1201) again, ubm layer (1201) is put weldering ball (1301), then wiring metal routing layer (1101) connects the first metal electrode (102a), the 2nd metal electrode (102b) and ubm layer (1201); At the back side (501b) of described capsulation material (501), the 2nd dielectric layer (902) is set, 2nd dielectric layer (902) is arranged back side wiring metal routing layer (1102) and back side ubm layer (1202) again, the back side again wiring metal routing layer (1102) be connected with metal level (203); The weldering ball (1301) of described upper strata fan-out package unit is connected with the back side ubm layer (1202) of lower floor's fan-out package unit.
2. PoP as claimed in claim 1 encapsulates structure, it is characterized in that: the outside surface (1201a) of described ubm layer (1201) is concordant with the outside surface (901a) of the first dielectric layer (901), or protrude from the outside surface (901a) of the first dielectric layer (901).
3. PoP as claimed in claim 1 encapsulates structure, it is characterized in that: the outside surface (1202a) at described back side ubm layer (1202) is concordant with the outside surface (902a) of the 2nd dielectric layer (902), or protrude from the outside surface (902a) of the 2nd dielectric layer (902).
4. PoP encapsulates a manufacturing process for structure, it is characterized in that, adopts following processing step:
(1) prepare carrier disk (201), apply the first adhesive-layer (202) at carrier disk (201) upper surface, and make metal level (203), metal level (203) makes through hole, exposes the upper surface of carrier disk (201); At via bottoms coating the 2nd adhesive-layer (202a) of metal level (203), the front (100a) of chip (100) is pasted on carrier disk (201) upward;
(2) by metal level (203), chip (100) plastic packaging in capsulation material (501), and ensureing that the front (100a) of chip (100) and the front (501a) of capsulation material (501) are positioned at same plane, the back side (100b) of chip (100) and the back side (501b) of capsulation material (501) are positioned at same plane;
(3) capsulation material (501) obtained in step (2) makes vertical through hole, exposes first surface (203a) of metal level (203), filled conductive material in through hole, form metal post (701);
(4) front (501a) of the capsulation material (501) obtained in step (3) applies the first dielectric layer (901), first dielectric layer (901) makes wiring metal routing layer (1101) again, then wiring metal routing layer (1101) connects the first metal electrode (102a) and the 2nd metal electrode (102b);
(5) remove carrier disk (201) and adhesive-layer, expose the back side (100b) of chip (100); At the upper surface coating dielectric layer of wiring metal routing layer (1101) again, and making ubm layer (1201) in the dielectric layer, ubm layer (1201) embeds in dielectric layer (901), is connected with wiring metal routing layer (1101) again;
(6) on ubm layer (1201), plant ball backflow, form weldering ball (1301) convex lattice array;
(7) back side (501b) of the capsulation material (501) obtained in step (6) applies the 2nd dielectric layer (902), at the 2nd dielectric layer (902) upper making back side wiring metal routing layer (1102) and back side ubm layer (1202) again, obtain fan-out package unit;
(8) two fan-out package unit are carried out stacking, backflow, obtain three-dimensional stacked PoP and encapsulate structure.
5. PoP as claimed in claim 4 encapsulates the manufacturing process of structure, it is characterized in that: described chip (100) subtracts thin by the IC disk (101) with multiple chip (100) and cuts.
6. PoP as claimed in claim 4 encapsulates the manufacturing process of structure, it is characterized in that: described metal level (203) employing sputtering, deposition or electric plating method make and obtain, or adopt the mode directly pasting tinsel/sheet or metal otter board to make.
7. PoP as claimed in claim 4 encapsulates the manufacturing process of structure, it is characterized in that: the operation employing of described step (1) is following operates replacement: apply the first adhesive-layer (202) at carrier disk (201) upper surface, paste the metal level (203) that preprocessing has through hole, then the front (100a) of chip (100) is pasted on carrier disk (201) upward.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410129744.3A CN103904057B (en) | 2014-04-02 | 2014-04-02 | PoP encapsulates structure and manufacturing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410129744.3A CN103904057B (en) | 2014-04-02 | 2014-04-02 | PoP encapsulates structure and manufacturing process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103904057A CN103904057A (en) | 2014-07-02 |
| CN103904057B true CN103904057B (en) | 2016-06-01 |
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| CN104538380A (en) * | 2014-12-10 | 2015-04-22 | 华进半导体封装先导技术研发中心有限公司 | Small-spacing PoP monomer |
| CN104505382A (en) * | 2014-12-30 | 2015-04-08 | 华天科技（西安）有限公司 | Wafer-level fan-out PoP encapsulation structure and making method thereof |
| CN104659021A (en) * | 2014-12-30 | 2015-05-27 | 华天科技（西安）有限公司 | Three-dimensional wafer level fan-out PoP encapsulating structure and preparation method for encapsulating structure |
| CN104659004A (en) * | 2014-12-30 | 2015-05-27 | 华天科技（西安）有限公司 | Pop structure and manufacture method thereof |
| CN105304507B (en) * | 2015-11-06 | 2018-07-31 | 通富微电子股份有限公司 | Fan-out wafer level packaging methods |
| CN105390471B (en) * | 2015-11-06 | 2018-06-12 | 通富微电子股份有限公司 | Fan-out wafer class encapsulation structure |
| US10290590B2 (en) * | 2016-11-29 | 2019-05-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Stacked semiconductor device and method of manufacturing the same |
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| US11257747B2 (en) | 2019-04-12 | 2022-02-22 | Powertech Technology Inc. | Semiconductor package with conductive via in encapsulation connecting to conductive element |
| CN110634756A (en) * | 2019-08-09 | 2019-12-31 | 上海先方半导体有限公司 | Fan-out packaging method and packaging structure |
| CN110993517A (en) * | 2019-12-13 | 2020-04-10 | 江苏中科智芯集成科技有限公司 | Chip stacking and packaging method and packaging structure |
| WO2021253225A1 (en) * | 2020-06-16 | 2021-12-23 | 广东省科学院半导体研究所 | Chip packaging structure and method |
| CN113937017A (en) * | 2020-07-14 | 2022-01-14 | 中芯集成电路（宁波）有限公司上海分公司 | Wafer level packaging method |
| CN111883480B (en) * | 2020-07-28 | 2022-04-01 | 南通通富微电子有限公司 | Chip interconnection method |
| CN111863790A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Semiconductor packaging device |
| CN115424980B (en) * | 2022-11-04 | 2023-02-07 | 成都复锦功率半导体技术发展有限公司 | Stacking and packaging method for double-side interconnection of chips |
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Application publication date: 20140702 Assignee: Jiangsu Xinde Semiconductor Technology Co.,Ltd. Assignor: National Center for Advanced Packaging Co.,Ltd. Contract record no.: X2022980027357 Denomination of invention: PoP packaging structure and manufacturing process Granted publication date: 20160601 License type: Common License Record date: 20221213 |
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