CN103837724A

CN103837724A - High-speed serial signal analysis device

Info

Publication number: CN103837724A
Application number: CN201210488086.8A
Authority: CN
Inventors: 宋云衢; 吕华平
Original assignee: JIANGSU LVYANG ELECTRONIC INSTRUMENT GROUP CO Ltd
Current assignee: JIANGSU LVYANG ELECTRONIC INSTRUMENT GROUP CO Ltd
Priority date: 2012-11-27
Filing date: 2012-11-27
Publication date: 2014-06-04

Abstract

The invention relates to a high-speed serial signal analysis device which belongs to the field of an electronic measurement instrument with an oscilloscope being a representative. The high-speed serial signal analysis device comprises an analog front end, an analog-digital converter, a time-domain equalizer, a clock and data restorer, a branching device and an FPGA module, wherein the analog front end is electrically connected with the analog-digital converter and the time-domain equalizer; the time-domain equalizer is connected with the clock and data restorer; the clock and data restorer is connected with the branching device; and the analog-digital converter and the branching device are electrically connected with the FPGA module. The high-speed serial signal analysis device has extremely-high speed and complete real-time performance; the protocol of the high-speed serial signal analysis device is flexible; and thus the high-speed serial signal analysis device can be widely applied to the high-performance digital oscilloscope.

Description

High-speed serial signals analytical equipment

Technical field

The present invention relates to a kind of oscillograph is the electronic measuring instrument field high-speed serial signals analytical equipment of representative.

Background technology

Along with computer bus is developed to high-speed serial bus by low-speed parallel bus, in the face of the technical bottleneck of the field high speed serial signal tests such as optical communication, radio communication, network, national defense safety and national Important Project, plan of science and technology needs urgent solution demand, traditional surveying instrument can not meet the test request of this class signal far away.Be badly in need of a kind of specialized equipment equipment that these signals is carried out to quantitative test analysis of development, i.e. high-speed serial signals analytic system.Must possess the features such as high sampling rate, high bandwidth, low noise, low jitter and high refresh rate due to high-speed serial signals analytic system, therefore technology content is high, system complex, add external technology barriers and technical monopoly, what this kind equipment can be provided at present both at home and abroad only has U.S. Agilent, Tektronix, LeCroy only a few manufacturer.Even and domestic in conventional digital oscillograph field, only this index of bandwidth has just just reached 1GHz, on sampling rate and these two key indexs of bandwidth, we also with exist gap abroad.And for the digital oscilloscope that can carry out high-speed serial signals analysis, bandwidth at least should be 2.5GHz.Cannot realize this index due at present domestic, therefore domesticly be entirely blank in this field.The index such as background shake and refresh rate cannot meet the analysis of high-speed serial signals especially still more.Therefore, no matter be high-speed serial signals analytic system, or high-performance digital oscilloscope, the scientific research institutions that current China is important and the equal dependence on import of high-end digital fluorescence oscilloscope product of national defense industry key.Development digital phosphor serial signal analytic system has great meaning to raising China instrument and equipment integral level, minimizing to the dependence of imported product.

Summary of the invention

Technique effect of the present invention can overcome above-mentioned defect, and a kind of high-speed serial signals analytical equipment is provided, and it has improved high-speed serial signals power of test.

For achieving the above object, the present invention adopts following technical scheme: it comprises AFE (analog front end), analog to digital converter, time domain equalizer, clock and data recovery device, shunt, FPGA module, AFE (analog front end) is electrically connected with analog to digital converter, time domain equalizer respectively, time domain equalizer connects clock and data recovery device, clock and data recovery device connects shunt, and analog to digital converter, shunt are electrically connected with FPGA module respectively.

FPGA module comprises storage manager, triggers manager, 8b/10b demoder, pattern adaptation, storage manager is electrically connected with triggering manager, analog to digital converter respectively, trigger manager and be electrically connected with pattern adaptation, 8b/10b demoder is electrically connected with shunt, pattern adaptation respectively.

High-speed serial signals analytical approach is as follows:

A, shake, timing and eye Diagram Analysis: shake, timing and eye Diagram Analysis are in high-speed serial signals analytical approach most important one.By obtaining and analyze the eye pattern of measured signal, can extract a lot of information of high-speed serial signals, as clock jitter, timing error, noise, signal to noise ratio (S/N ratio) etc.This analysis project can reflect the signal quality of high-speed serial signals the most intuitively; Can realize the measurement to following parameter: extinction ratio (absolute value, %, dB), eye is high, and eye is wide, eye top, eyeground, intersection %, noise (p-p, RMS), signal to noise ratio (S/N ratio), cycle distortion, Q factor.Can realize the NRZ data stream that speed is PRBS lower than 1.25Gbps, pattern, software can be measured the parameters of its eye pattern automatically.As Fig. 1.

B, agreement and serial pattern trigger: be debugging serial framework, can use hardware clock restoring circuit to carry out the triggering of serial pattern to NRZ serial data stream, and by the event correlation in Physical layer and link layer.Instrument can recovered clock signal, and identification saltus step arranges required coded word for the serial pattern of catching triggers.User can check the 8b/10b bit sequence that is decoded into word, analyzes easily, also can needs the field of decoding be set to the pattern of serial pattern in triggering and catch it.The NRZ data stream that this analysis project is PRBS for speed lower than 1.25Gbps, pattern, software can automatically carry out clock identification and recovers and it is carried out to correct decoding it.

C, template test: template test, for long-term validation signal quality, belongs to the one application of eye pattern test.In the time that signal eye diagram does not meet template standard, instrument can be by this signal record, and informs user.

High-speed serial signals analytical equipment of the present invention, it possesses high speed and real-time completely, and its agreement is flexible, can be widely used in high-performance digital oscilloscope.

Accompanying drawing explanation

Fig. 1 is modular structure schematic diagram of the present invention.

Embodiment

As shown in Figure 1, high-speed serial signals analytical equipment of the present invention comprises AFE (analog front end), analog to digital converter, time domain equalizer, clock and data recovery device, shunt, FPGA module, AFE (analog front end) is electrically connected with analog to digital converter, time domain equalizer respectively, time domain equalizer connects clock and data recovery device, clock and data recovery device connects shunt, and analog to digital converter, shunt are electrically connected with FPGA module respectively.

High-speed serial signals analysis is the process of a cooperative work of software and hardware.Wherein, hardware process: first input signal sends into AFE (analog front end), carries out suitable amplification or decay, then sends into analog to digital converter, sends into time domain equalizer simultaneously and carries out balanced to improve the success ratio of clock recovery in the situation that signal quality is poor.Signal after equilibrium is sent into clock and data recovery device (Clock and Data Recovery, CDR) and is carried out Clock Extraction.The essence of CDR is a narrow band phase lock loop, the clock information in high-speed serial signals can be extracted, then go out data with this clock recovery.The speed data stream now generating is higher, therefore enters DEMUX and carries out phase-splitting and send into FPGA module, carries out 8b/10b decoding and pattern coupling in FPGA module, realizes pattern and triggers thereby generate trigger pip.

Software process comprises that eye pattern generation, jitter analysis, timing analysis, protocol-decoding and template are relatively etc.Although advanced digital phosphor imaging processor also can generate real-time eye pattern, this eye pattern is applicable to observation, and information extraction precision is poor.Therefore, carry out when detailed high-speed serial signals is analyzed using software approach to complete.This project possesses the dark storage of every passage 2Gpts, therefore can obtain the analysis result that precision is very high.Jitter analysis and timing analysis also here complete.And protocol-decoding work both can have been completed by hardware, also can be completed by software.The former possesses high speed and real-time completely, and the latter has agreement feature flexibly.

Claims

1. a high-speed serial signals analytical equipment, it is characterized in that, comprise AFE (analog front end), analog to digital converter, time domain equalizer, clock and data recovery device, shunt, FPGA module, AFE (analog front end) is electrically connected with analog to digital converter, time domain equalizer respectively, time domain equalizer connects clock and data recovery device, clock and data recovery device connects shunt, and analog to digital converter, shunt are electrically connected with FPGA module respectively.

2. high-speed serial signals analytical equipment according to claim 1, it is characterized in that, FPGA module comprises storage manager, triggers manager, 8b/10b demoder, pattern adaptation, storage manager is electrically connected with triggering manager, analog to digital converter respectively, trigger manager and be electrically connected with pattern adaptation, 8b/10b demoder is electrically connected with shunt, pattern adaptation respectively.