CN103811549B - 横向mosfet - Google Patents

横向mosfet Download PDF

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Publication number
CN103811549B
CN103811549B CN201310032027.4A CN201310032027A CN103811549B CN 103811549 B CN103811549 B CN 103811549B CN 201310032027 A CN201310032027 A CN 201310032027A CN 103811549 B CN103811549 B CN 103811549B
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Prior art keywords
isolation area
top surface
semiconductor device
substrate
gate electrode
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CN201310032027.4A
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CN103811549A (zh
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刘惠如
周建志
郑光茗
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

横向MOSFET包括形成在衬底中的多个隔离区，其中第一隔离区的顶面低于衬底的顶面。横向MOSFET还包括栅电极层，其具有形成在第一隔离区上方的第一栅电极层和形成在衬底顶面上方的第二栅电极层，第一栅电极层的顶面低于第二栅电极层的顶面。

Description

横向MOSFET
技术领域
本发明总的来说涉及半导体领域，更具体地，涉及横向MOSFET。
背景技术
由于各种电子部件(例如，晶体管、二极管、电阻器、电容器等)集成密度的提高，半导体行业经历了快速发展。在很大程度上，集成密度的这种提高源自半导体工艺节点的缩小(例如，朝亚20nm节点缩小工艺节点)。随着半导体尺寸的按比例缩小，需要新技术来一代代维持电子部件的性能。例如，期望晶体管的低导通阻抗和高击穿电压可用于各种高功率应用。
随着半导体技术的发展，金属氧化物半导体场效应晶体管(MOSFET)已广泛应用到当今的集成电路。MOSFET是压控器件。当向MOSFET的栅极施加控制电压并且控制电压大于MOSFET的阈值时，在MOSFET的漏极和源极之间建立导电沟道。结果，电流在MOSFET的漏极和源极之间流动。另一方面，当控制电压小于MOSFET的阈值时，相应地截止MOSFET。
根据极性的不同，MOSFET可包括两大类。一类是n沟道MOSFET，另一类是p沟道MOSFET。另一方面，根据结构的不同，MOSFET可进一步分为三个子类：平面MOSFET，横向扩散MOS(LDMOS)FET和垂直扩散MOSFET。
与其他MOSFET相比，LDMOS晶体管具有更多的优点。例如，由于LDMOS晶体管的不对称结构在其漏极和源极之间提供了短沟道，所以LDMOS晶体管每单位面积能够传送更大的电流。
发明内容
根据本发明的一个方面，提供了一种半导体器件，包括：多个隔离区，形成在具有顶面的衬底中，多个隔离区中的第一隔离区的顶面低于衬底的顶面；以及栅电极层。栅电极层包括：第一栅电极层，形成在第一隔离区上方；和第二栅电极层，形成在衬底的顶面上方，第一栅电极层的顶面低于第二栅电极层的顶面。
优选地，高压栅极介电层包括：第一高压栅极介电层，形成在第一隔离区上方；以及第二高压栅极介电层，形成在衬底的顶面上方，第一高压栅极介电层的顶面低于第二高压栅极介电层的顶面。
优选地，高压栅极介电层包括两种或多种不同的介电材料。
优选地，隔离区是浅沟槽隔离(STI)区。
优选地，第一栅电极层形成高压横向扩散晶体管的栅极结构。
优选地，栅电极层包括多晶硅。
优选地，隔离区包括两种或多种不同的介电材料。
优选地，第一隔离区是减小表面电场(RESURF)STI。
根据本发明的另一方面，提供了一种器件，包括：第一器件，形成在衬底中；以及第二器件，形成在衬底中。第一器件包括：第一栅极介电层，形成在第一隔离区上方，第一栅极介电层具有第一厚度；和第一栅电极层，形成在第一栅极介电层上方。第一栅电极层包括：第一部分，与第一隔离区垂直对齐；和第二部分，其顶面高于第一部分的顶面。第二器件包括：具有第二厚度的第二栅极介电层，并且第一厚度大于第二厚度。
优选地，第一器件是形成在衬底的高压区中的高压器件；以及第二器件是形成在衬底的低压区中的低压器件。
优选地，该器件进一步包括：伪结构，形成在高压介电层上方并位于高压区和低压区之间的边界处，伪结构形成在衬底中的第二隔离区上方。
优选地，伪结构包括多晶硅。
优选地，伪结构包括：第一部分，与第二隔离区垂直对齐；以及第二部分，其顶面高于第一部分的顶面。
优选地，第一器件是高压横向扩散晶体管；以及第二器件是低压平面晶体管。
根据本发明的又一方面，提供了一种方法，包括：在衬底中形成第一隔离区，第一隔离区的顶面与衬底的顶面平齐；移除第一隔离区的上部以形成凹槽；在第一隔离区的上方沉积栅极介电层；以及在栅极介电层上方形成栅电极层。其中，栅电极层的第一部分与第一隔离区垂直对齐；并且栅电极层的第二部分形成在衬底上方，并且第一部分的顶面低于第二部分的顶面。
优选地，该方法进一步包括：在衬底的高压区中形成多个高压阱；在衬底的低压区中形成多个低压阱；在高压区和低压区之间的边界处形成第二隔离区；在第二隔离区上方形成伪结构，伪结构包括：第一部分，与第二隔离区垂直对齐；以及第二部分，其顶面高于第一部分的顶面。
优选地，该方法进一步包括：将离子注入高压区中，以形成位于高压阱中的晶体管的第一源极区；以及将离子注入高压区中，以形成位于高压阱中的晶体管的第一漏极区，源极区和漏极区位于第一隔离区的相对侧。
优选地，晶体管是横向扩散晶体管。
优选地，第一隔离区是浅沟槽隔离(STI)区。
优选地，第一隔离区是减小表面电场(RESURF)STI区。
附图说明
为了更完整地理解本发明及其优点，现在结合附图作为参考进行以下描述，其中：
图1示出了根据实施例的包括横向扩散金属氧化物半导体(LDMOS)晶体管的半导体器件的截面图；
图2示出了根据实施例的在衬底上方沉积介电层之后半导体器件的截面图；
图3示出了根据实施例的图2所示半导体器件在向半导体器件应用图案化工艺之后的截面图；
图4示出了根据实施例的图3所示半导体器件在向半导体器件应用蚀刻工艺之后的截面图；
图5示出了根据实施例的图4所示半导体器件在向半导体器件的隔离区应用蚀刻工艺之后的截面图；
图6示出了根据实施例的图5所示半导体器件在衬底上方沉积高压栅极介电层之后的截面图；
图7示出了根据实施例的图6所示半导体器件在高压介电层上方沉积光刻胶层之后的截面图；
图8示出了根据实施例的图7所示半导体器件在向高压栅极介电层应用蚀刻工艺之后的截面图；
图9示出了根据实施例的图8所示半导体器件在向介电层应用蚀刻工艺之后的截面图；
图10示出了根据实施例的图9所示半导体器件在衬底上方的低压区中形成低压阱之后的截面图；
图11示出了根据实施例的图10所示半导体器件在低压区上方形成薄介电层之后的截面图；
图12示出了根据实施例的图11所示半导体器件在衬底上方沉积栅电极层之后的截面图；
图13示出了根据实施例的图12所示半导体器件在向半导体器件的顶面应用蚀刻工艺之后的截面图；
图14示出了根据实施例的图13所示半导体器件在向半导体器件的顶面应用蚀刻工艺之后的截面图；
图15示出了根据实施例的图14所示半导体器件在向半导体器件的顶面应用蚀刻工艺之后的截面图；以及
图16示出了根据实施例的图15所示半导体器件在形成高压漏极/源极区和低压漏极/源极区之后的截面图。
除非另有说明，否则不同附图中对应的数字和符号通常表示对应的部件。为了清楚示出各个实施例的相关方面绘制附图，但并不需要按照比例绘制。
具体实施方式
以下详细讨论本发明实施例的制造和使用。然而，应该理解，本发明提出了许多可在各种具体环境中具体化的可应用发明概念。所讨论的具体实施例仅是制造和使用本发明实施例具体方式的说明，而不限制本发明的范围。
本发明将参照具体环境的实施例进行描述，即横向金属氧化物半导体场效应晶体管(MOSFET)。然而，本发明的实施例还可应用于各种金属氧化物半导体晶体管。下文中，将参照附图详细说明各个实施例。
图1示出了根据实施例的包括横向扩散金属氧化物半导体(LDMOS)晶体管的半导体器件的截面图。在衬底101中形成LDMOS晶体管100。根据实施例，衬底101可由硅、锗硅、碳化硅等形成。
如图1所示，可在衬底101中中形成三个阱。这三个阱是第一p型阱112、第一n型阱114和第二p型阱116。具体地，第一n型阱114设置在第一p型阱112和第二p型阱116之间。
通过注入诸如硼、镓、铝、铟、它们的组合等的p型掺杂材料来形成第一p型阱112和第二p型阱116。根据实施例，可注入约1015/cm3至1018/cm3的掺杂浓度的诸如硼的p型材料。可选地，可通过扩散工艺形成第一p型阱112和第二p型阱116。
类似地，通过注入诸如磷、砷等的n型掺杂材料来形成第一n型阱114。根据实施例，可注入约1015/cm3至1018/cm3的掺杂浓度诸如磷的n型材料。可选地，可通过扩散工艺形成第一n型阱114。
如图1所示，可在衬底101中形成多个隔离区和有源区。有源区包括第一P+区152、第一漏极/源极区154、第二漏极/源极区156以及第二P+区158。漏极/源极区和P+区可形成LDMOS晶体管。
根据实施例，图1中所示的阱(例如，p型阱112、116和n型阱114)是高压阱。因此，LDMOS晶体管100是高压晶体管。这种高压晶体管可用于额定电压范围在约2V至约8V之间的中压应用。可选地，这种高压晶体管可用于额定电压范围在约8V至约400V之间的高压应用。此外，这种高压晶体管可用于额定电压大于400v的超高压应用。
图1所示的隔离区提供了有源区之间的隔离。例如，隔离区132在衬底101中形成在第一n型阱112和外部阱或部件之间界面处。隔离区134用于隔离有源区(例如，第一P+区152和第一漏极/源极区154)，以防止漏电流在相邻的有源区之间流动。
隔离区136用作减小表面电场(RESURF)结构。更具体地，隔离区136是第二漏极/源极区156的延伸。第二漏极/源极区156的这种电介质延伸有助于实现均匀的电场分布。结果，LDMOS晶体管100可得到更高的击穿电压和更低的导通阻抗。
应该注意，隔离区136的顶面低于其他隔离区(例如，隔离区132和134)的顶面。利用栅极介电材料填充隔离区136的顶面和衬底101的顶面之间的间隙。如图1所示，间隙的高度定义为H2。以下参照图5描述位于隔离区136的顶面和衬底101的顶面之间的间隙的详细形成工艺。
隔离区138形成在第二漏极/源极区156和第二P+区158之间。隔离区140形成为与第二P+区158相邻。隔离区138和140的功能和结构分别与隔离区134和132的功能和结构类似，因此为避免不必要的重复本文没有详细讨论。
可通过各种适合的制造技术(例如，热生长、沉积)和各种材料(例如，氧化硅、氮化硅、任意它们的组合等)形成隔离区(例如，隔离区132、134、136、138和140)。在这个实施例中，可使用浅沟槽隔离(STI)技术来制造隔离区。
栅极介电层沉积于衬底101上方。为了通过离子注入技术来形成有源区，可在两个相邻的栅极介电块之间形成多个开口。例如，为了形成第一P+区152，在第一栅极介电块172和第二栅极介电块174之间具有开口。以下参照图14-图16描述在栅极介电层中形成开口的详细工艺。
栅电极层形成在衬底101上方。如图1所示，栅电极层可分为两部分，即第一栅电极层180和第二栅电极层182。如图1所示，在衬底101的顶面上形成的第一栅极介电区176上方形成第一栅电极层180。第二栅电极层182与隔离区136垂直对齐。更具体地，由于隔离区136和衬底101顶面之间的间隙，在第一栅电极层180的顶面和第二栅电极层182的顶面之间具有高度差。图1所示高度差定义为H1。根据实施例，H1在约到约之间范围内。
本领域技术人员将意识到，图1示出了理想的剖面图。在随后的制造工艺之后，可改变H1和H2。图1所示的高度差(例如，H1和H2)用于示出各个实施例的发明方面。本发明不限于任何特定的高度差。
应该注意，第一栅电极层180的高度与常规LDMOS晶体管的栅电极层的高度类似。在隔离区136上没有凹槽的情况下，第二栅电极层182的顶面可高于常规LDMOS晶体管的栅电极层的顶面。凸出的第二电极层182可导致第二栅电极层182和随后形成的金属层(例如，第一金属层M1)之间的短路。
第二栅电极层182具有较低顶面的一个有利特征是，第二栅电极层182的较低顶面有助于防止第二栅电极层182与随后形成的金属层(例如，第一金属层M1)发生短路。因此，可提高LDMOS晶体管100的工艺裕度。提高的工艺裕度可进一步简化制造工艺并降低LDMOS晶体管100的制造成本。
图2至图16示出了根据实施例的制造包括图1所示LDMOS晶体管的半导体器件的中间步骤的截面图。图2示出了根据实施例的在衬底101上方沉积介电层之后的半导体器件的截面图。衬底101可以是半导体衬底，诸如体硅衬底、绝缘体上硅(SOI)等。
衬底101可包括两个区，即高压区110和低压区150。在这个实例中，利用两个虚线框区分高压区110和低压区150。例如根据适当的高压和低压应用，衬底101可掺杂有各种阱。在高压区110中，第一p型阱112、第一n型阱114和第二p型阱116形成在衬底101中。
高压区110用于形成高压LDMOS晶体管。类似地，低压区150用于形成低压平面晶体管。以下参照图3-图16描述高压LDMOS晶体管和低压平面晶体管的详细形成工艺。
如图2所示，介电层190形成在衬底101上方。介电层190可由集成电路制造中常用的各种介电材料形成。例如，介电层190由二氧化硅、氮化硅或诸如硼硅酸盐玻璃的掺杂玻璃层等形成。可选地，介电层可以是氮氧化硅层、聚酰胺层、低介电常数绝缘体等。此外，上述介电材料的组合也可用于形成介电层190。
根据实施例，介电层190可由氮化硅形成。可使用诸如化学汽相沉积(CVD)等的适当沉积技术来形成氮化硅层190。
图3示出了根据实施例的图2所示半导体器件在向半导体器件应用图案化工艺之后的截面图。根据实施例，光刻胶掩膜层302通过适合的沉积技术沉积在介电层190上方。而且，根据介电层190中开口的位置，适合的光刻技术用于形成光刻胶层302中的开口304。
图4和图5示出了根据实施例的高压栅极氧化物预清洗工艺。图4示出了根据实施例的图3所示半导体器件在向半导体器件应用蚀刻工艺之后的截面图。执行蚀刻工艺(诸如反应离子蚀刻(RIE)或其他干蚀刻、各向异性湿蚀刻或任何其他适合的各向异性蚀刻或图案化工艺)以移除介电层190的一部分。可通过使用合适的灰化工艺来移除剩余的光刻胶层(未示出)。
图5示出了根据实施例的图4所示半导体器件在向半导体器件的隔离区应用蚀刻工艺之后的截面图。向隔离区136的上部应用诸如湿蚀刻技术的适当蚀刻工艺。结果，填充在隔离区136上部中的介电材料被移除。通过控制蚀刻工艺的强度和方向，在隔离区136中形成凹槽502。根据实施例，凹槽502的高度为H2。H2在约至约之间的范围内。
图6示出了根据实施例的图5所示半导体器件在衬底上方沉积高压栅极介电层之后的截面图。高压栅极介电层602共形地沉积在衬底101上方。可使用诸如CVD等的适合沉积技术来形成高压栅极介电层602。
根据各个实施例，高压栅极介电层602可由诸如氧化硅的氧化物、氮化硅、复合氧化物/氮化物/氧化物、类似材料或它们的组合形成。其他可接受的材料可用于高压栅极介电层602。高压栅极介电层602的厚度在约至约之间的范围内。
应该注意，由于隔离区136中的凹槽502(图5中示出)，高压栅极介电层602具有不平坦的表面(例如，用虚线框604标出的区域)。还应注意，高压栅极介电层602可具有多层结构。可选地，高压栅极介电层602可包括不同的介电材料。
图7示出了根据实施例的图6所示半导体器件在高压栅极介电层上方沉积光刻胶层之后的截面图。使用旋转沉积等在高压栅极介电层602的上方沉积光刻胶层702。对光刻胶层702进行曝光并显影，使得只保留高压区110上方的部分。剩余的光刻胶层702从隔离区132横向延伸至隔离区140。通过光刻胶层702露出高压栅极介电层602位于低压区150上方的部分。
图8示出了根据实施例的图7所示半导体器件在向高压栅极介电层应用蚀刻工艺之后的截面图。向半导体器件应用蚀刻工艺。如图8所示，结果移除了高压栅极介电层602位于低压区150上方的部分。
图9示出了根据实施例的图8所示半导体器件在向介电层应用蚀刻工艺之后的截面图。向半导体器件应用蚀刻工艺。如图9所示，结果移除了低压区150上方的介电层190。
图10示出了根据实施例的图9所示半导体器件在衬底上方的低压区中形成低压阱之后的截面图。类似于图2所示的掺杂工艺，低压区150可掺有各种阱。如图10所示，在低压区150中，在衬底101中形成的深n型阱(DNW)102中形成n型阱122、126和p型阱124。
图11示出了根据实施例的图10所示半导体器件在低压区上方形成薄介电层之后的截面图。薄介电层1102是低压栅极介电层。通过使用诸如热氧化等的适合制造技术来形成低压栅极介电层1102。
根据实施例，低压栅极介电层1102包括诸如氧化硅的氧化物。可选地，低压栅极介电层1102可包括氧化铪、氧化钽、氧化铝、类似材料或它们的组合。低压栅极介电层1102的厚度在约至约之间的范围内。
应该注意，虽然图11示出的低压栅极介电层1102是单层，但低压栅极介电层1102可具有多层结构。可选地，低压栅极介电层1102可包括多种介电材料。还应注意，高压栅极介电层602的厚度大于低压栅极介电层1102的厚度。
图12示出了根据实施例的图11所示半导体器件在衬底上方沉积栅电极层之后的截面图。栅电极层1202可由多晶硅形成。可选地，栅电极层1202可由其他常用的导电材料形成，诸如金属(例如，钽、钛、钼、钨、铂、铝、铪、钌)、金属硅化物(例如，硅化钛、硅化钴、硅化镍、硅化钽)、金属氮化物(例如，氮化钛、氮化钽)、掺杂多晶硅、其他导电材料、它们的组合等。
使用诸如CVD等的适合沉积技术在高压栅极介电层602和低压栅极介电层1102上方沉积栅电极层。栅电极层1202随后可用于形成用于高压区110中的晶体管器件和低压区150中的晶体管器件的栅电极。
底部抗反射涂料(BARC)层1204形成在栅电极层1202上方。BARC层1204可由氮化物材料、有机材料、氧化物材料等形成。可使用诸如CVD等的适合技术来形成BARC层1204。
应该注意，由于图6所示高压栅极介电层的不平坦表面，导致高压区110上方的栅电极层1202具有不平坦的表面。
图13示出了根据实施例的图12所示半导体器件在向半导体器件的顶面应用蚀刻工艺之后的截面图。图案化栅电极层1202以形成包括第一部分180和第二部分182的高压栅电极层、低压栅电极186和位于高压区110和低压区150之间的边界处的伪结构184。高压栅电极具有不平坦的表面。具体地，第二部分182的顶面低于第一部分180的顶面。这种较低的顶面有助于防止高压栅电极和随后形成的金属层(未示出)之间的短路。
图14示出了根据实施例的图13所示半导体器件在向半导体器件的顶面应用蚀刻工艺之后的截面图。诸如通过各向异性蚀刻来图案化高压栅极介电层602以形成如图14所示的开口1402、1404、1406和1408。
图15示出了根据实施例的图14所示半导体器件在向半导体器件的顶面应用蚀刻工艺之后的截面图。根据实施例，为了向高压区110应用离子注入工艺，向开口1402、1404、1406和1408应用蚀刻工艺。结果，移除开口1402、1404、1406和1408底部处的介电材料。
当向半导体器件的顶面应用蚀刻工艺时，可以向半导体器件应用BARC移除工艺。可通过使用包括干蚀刻、湿蚀刻、它们的组合等的合适蚀刻技术来移除BARC层。
图16示出了根据实施例的图15所示半导体器件在形成高压漏极/源极区和低压漏极/源极区之后的截面图。在高压区110中，漏极/源极区154和156可在衬底101上方形成在隔离区136的相对两侧。第一P+区152形成在隔离区132和隔离区134之间。第二P+区158形成在隔离区138和隔离区140之间。
根据实施例，当衬底101是n型衬底时，可通过注入诸如硼、镓、铟等合适的p型掺杂物来形成漏极/源极区(例如，漏极/源极区154)。可选地，在衬底101是p型衬底的实施例中，可通过注入诸如磷、砷等合适的n型掺杂物来形成漏极/源极区(例如，漏极/源极区154)。根据实施例，漏极/源极区(例如漏极/源极区154)的掺杂浓度在约1019/cm3至约5×1019/cm3之间的范围内。应该注意，虽然图16示出的漏极/源极区是n型，但是根据不同的设计需要，漏极/源极区也可以是p型。
在低压区150中，漏极/源极区(例如，N+区164和166)可形成在衬底101上方。根据实施例，当衬底101是n型衬底时，可通过注入诸如硼、镓、铟等合适的p型掺杂物来形成漏极/源极区(例如，漏极/源极区164)。可选地，在衬底101是p型衬底的实施例中，可通过注入诸如磷、砷等合适的n型掺杂物来形成漏极/源极区(例如，漏极/源极区164)。根据实施例，漏极/源极区(例如漏极/源极区164)的掺杂浓度在约1019/cm3至约5×1019/cm3之间的范围内。应该注意，虽然图16示出的低压漏极/源极区是n型，但是根据不同的设计需要，低压漏极/源极区也可以是p型。
尽管已经详细描述本发明及其优点，但是应该理解，在不背离所附权利要求限定的本发明的精神和范围的情况下，可以进行各种改变、替换和变更。
而且，本申请的范围并不旨在限于说明书中描述的工艺、机器装置、制造、物质组成、工具、方法和步骤的特定实施例。根据本发明本领域技术人员会很容易理解，根据本发明可使用与本文描述的对应实施例执行基本相同功能或实现基本相同结果的目前现有或或即将开发的工艺、机器装置、制造、物质组成、工具、方法或步骤。因此，所附权利要求旨在包括这种工艺、机器装置、制造、物质组成、工具、方法或步骤范围内。

Claims (20)

1.一种半导体器件，包括：
多个隔离区，形成在具有顶面的衬底中，其中所述多个隔离区的第一隔离区的顶面低于所述衬底的顶面；以及
栅电极层，包括：
第一栅电极层，形成在所述第一隔离区上方；以及
第二栅电极层，形成在所述衬底的顶面上方，其中所述第一栅电极层的顶面低于所述第二栅电极层的顶面，
所述第一栅电极的顶面高于所述衬底的顶面。
2.根据权利要求1所述的半导体器件，其中：
高压栅极介电层包括：
第一高压栅极介电层，形成在所述第一隔离区上方；以及
第二高压栅极介电层，形成在所述衬底的顶面上方，其中所述第一高压栅极介电层的顶面低于所述第二高压栅极介电层的顶面。
3.根据权利要求2所述的半导体器件，其中：
所述高压栅极介电层包括多种不同的介电材料。
4.根据权利要求1所述的半导体器件，其中：
所述隔离区是浅沟槽隔离区(STI)。
5.根据权利要求1所述的半导体器件，其中：
所述第一栅电极层形成高压横向扩散晶体管的栅极结构。
6.根据权利要求1所述的半导体器件，其中：
所述栅电极层包括多晶硅。
7.根据权利要求1所述的半导体器件，其中：
所述隔离区包括多种不同的介电材料。
8.根据权利要求1所述的半导体器件，其中：
所述第一隔离区是减小的表面电场(RESURF)浅沟槽隔离区。
9.一种半导体器件，包括：
第一器件，形成在衬底中，其中所述第一器件包括：
第一栅极介电层，形成在第一隔离区上方，其中所述第一栅极介电层具有第一厚度；以及
第一栅电极层，形成在所述第一栅极介电层上方，其中所述第一栅电极层包括：
第一部分，与所述第一隔离区垂直对齐；以及
第二部分，其顶面高于所述第一部分的顶面；以及
第二器件，形成在所述衬底中，其中所述第二器件包括：
具有第二厚度的第二栅极介电层，并且其中所述第一厚度大于所述第二厚度，
其中，所述第一隔离区的顶面低于所述衬底的顶面。
10.根据权利要求9所述的半导体器件，其中：
所述第一器件是形成在所述衬底的高压区中的高压器件；以及
所述第二器件是形成在所述衬底的低压区中的低压器件。
11.根据权利要求10所述的半导体器件，进一步包括：
伪结构，形成在高压介电层上方并位于所述高压区和所述低压区之间的边界处，其中所述伪结构形成在所述衬底中的第二隔离区上方。
12.根据权利要求11所述的半导体器件，其中：
所述伪结构包括多晶硅。
13.根据权利要求11所述的半导体器件，其中所述伪结构包括：
第一部分，与所述第二隔离区垂直对齐；以及
第二部分，其顶面高于所述第一部分的顶面。
14.根据权利要求9所述的半导体器件，其中：
所述第一器件是高压横向扩散晶体管；以及
所述第二器件是低压平面晶体管。
15.一种用于形成半导体器件的方法，包括：
在衬底中形成第一隔离区，其中所述第一隔离区的顶面与所述衬底的顶面平齐；
移除所述第一隔离区的上部以形成凹槽；
在所述第一隔离区的上方沉积栅极介电层；以及
在所述栅极介电层上方形成栅电极层，其中：
所述栅电极层的第一部分与第一隔离区垂直对齐；以及
所述栅电极层的第二部分形成在所述衬底上方，并且其中，所述第一部分的顶面低于所述第二部分的顶面，
所述栅电极层的第一部分的顶面高于所述衬底的顶面。
16.根据权利要求15所述的用于形成半导体器件的方法，进一步包括：
在所述衬底的高压区中形成多个高压阱；
在所述衬底的低压区中形成多个低压阱；
在所述高压区和所述低压区之间的边界处形成第二隔离区；
在所述第二隔离区上方形成伪结构，其中所述伪结构包括：
第一部分，与所述第二隔离区垂直对齐；以及
第二部分，其顶面高于所述第一部分的顶面。
17.根据权利要求16所述的用于形成半导体器件的方法，进一步包括：
将离子注入所述高压区中，以形成位于所述高压阱中的晶体管的第一源极区；以及
将离子注入所述高压区中，以形成位于所述高压阱中的晶体管的第一漏极区，其中所述源极区和所述漏极区位于所述第一隔离区的相对两侧。
18.根据权利要求17所述的用于形成半导体器件的方法，其中：
所述晶体管是横向扩散晶体管。
19.根据权利要求15所述的用于形成半导体器件的方法，其中：
所述第一隔离区是浅沟槽隔离区(STI)。
20.根据权利要求19所述的用于形成半导体器件的方法，其中：
所述第一隔离区是减小的表面电场(RESURF)浅沟槽隔离区。
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