CN103811048A - Low power consumption refresh method of hybrid memory structure - Google Patents

Abstract

The invention provides a low power consumption refresh method of a hybrid memory structure. When a DRAM (Dynamic Random Access Memory) is in a very busy state, a temperature sensitive mode is selected, a storage unit in a nonvolatile memory takes the place of a worst storage unit detected within a present temperature range to reconfigure the DRAM refresh cycle; when the condition that the present temperature is changed to another temperature range at one moment is detected, the information of the worst storage unit is updated, and the refresh cycle is updated; if the DRAM is operated in a temperature non-sensitive mode, the storage unit in the nonvolatile memory takes the place of the detected worst storage unit to reconfigure the refresh cycle of the DRAM; if the operation temperature of the DRAM exceeds a provided value at one moment, the DRAM is switched back to an ordinary refresh mode for a low power consumption refresh mode. By adopting the technical scheme of the invention, the improvement of the refresh cycle is achieved, the refresh power consumption is saved, and the original storage and reading performance of the DRAM is generally not affected.

Description

A kind of low-power consumption method for refreshing of mixing memory structure

Technical field

The invention belongs to computer hardware field, relate to a kind of memory bar method for refreshing, relate in particular to a kind of low-power consumption method for refreshing of mixing memory structure.

Background technology

Decades in the past, dynamic RAM (DRAM) cost is along with Moore's Law constantly reduces.But along with characteristic dimension is more and more less, chip is more and more higher to the requirement of power consumption, because therefore the electric leakage of DRAM memory capacitance just must refresh once at set intervals, along with DRAM capacity is increasing, refresh power consumption also increasing, as shown in Figure 1.Refresh operation is power consumption not only, and due to interfere with memory access therefore DRAM performance also can decline.DRAM refreshing frequency is to be determined by the poorest storage unit (tail bit) at present, for example 64ms, and the storage unit retention time distributes as shown in Figure 2, can find out that the ability of the maintenance data of absolutely large counting unit will be grown more than the refresh cycle in figure.And along with temperature raises, refreshing frequency also can rise.Therefore how to reduce that to refresh power consumption, reduce refreshing frequency be to improve DRAM performance and need badly the problem of solution.

DRAM has two kinds of basic modes that refresh, centralized refresh (burst refresh) and distributed refresh (distributed refresh) at present.In centralized refresh mode, will the refresh cycle be divided into two parts: in a period of time, all row of refresh memory, now CPU stops access memory; In another time period, CPU can access memory, and refresh circuit is not worked.There is read-write Dead Time in this refresh mode, is applicable to high-speed memory.Distributed refresh circuit is CPU and refresh circuit alternate access internal memory, and within a refresh cycle, all provisional capitals are refreshed once, and the time interval being refreshed with a line equal the refresh cycle of storage chip, two kinds are refreshed mode as shown in Figure 3.For example, concerning the capable DRAM memory array of 4K, the refresh cycle is 64ms, has 4096 refreshing frequencies in the refresh cycle, and it is 130ns that every a line is refreshed to the time needing.Concerning centralized refresh mode, need to 4096 row be concentrated and be refreshed, the time is:

4096×130ns=532480ns≈0.532ms；

64ms-0.532ms=63.468ms；

That is to say within a refresh cycle have the time consumption of 0.532ms on refreshing, now CPU cannot access DRAM, and residue 63.468ms offers CPU DRAM is read or write operation.Concerning distributed refresh mode, 64ms is assigned to every a line and is:

64ms÷4096=15.6us；

15.6us-0.13us=15.47us；

That is to say that, within a refresh cycle, the every a line in DRAM has 0.13us to expend on refreshing, residue 15.47us can carry out read-write operation to this row for CPU.

Auto thermal compensation self-refresh technology (Auto Temperature Compensated Self Refresh) is a kind of DRAM refresh technique of low-power consumption.When temperature raises, refreshing frequency must improve in order to avoid loss of data refreshes power consumption and also rises thereupon; On the contrary, when temperature reduces, data holding ability also can rise, and refreshing frequency can decrease, as shown in Figure 4.It realizes structural drawing as shown in Figure 5.Auto thermal compensation self-refresh module utilizes a built-in temperature sensor to go to respond to environment temperature, then automatically adjusts refresh interval, thereby significantly reduces power consumption.Thereby traditional temperature compensated self refresh module can change from outside the value of temperature register adjusts refreshing frequency.Although this technology can reduce refreshing frequency, in certain temperature range, the refreshing frequency setting is fixed, and does not consider the distribution of poor storage unit.And along with technical development DRAM from CPU more and more close to, temperature also can be more and more higher, the method for this reduction power consumption also more and more limitation.

DRAM intelligence refresh technique based on data hold time is that the capable DRAM difference according to the retention time is divided into different groups, and each group is refreshed with different refreshing frequencys.Those comprise the group of poor storage unit and refresh with normal refresh frequency, and the row refreshing frequency of the overwhelming majority reduces greatly, without DRAM array is revised, only need carry out minimal correction to dram controller.Data is presented in the eight core systems of 32GB DRAM, and refreshing frequency can reduce by 74.6%, and average DRAM power consumption can reduce by 16.1%.Although this method has been considered the poorest storage unit, no matter whether DRAM is busy, comprises the row of poor storage unit and still need to refresh with normal refresh frequency.

Recently, some novel DRAM structures or storage medium are suggested to solve the defect of current DRAM technology.IBM Corporation advocates to be combined with DRAM and to form a kind of mixing memory with nonvolatile memory phase transition storage (PCM).Its structure as shown in Figure 6.DRAM is only as Cache, and buffer memory most recently used information, only has when needed and just data are stored in PCM.Because DRAM is just as buffer memory, capacity does not need very large, PCM as primary storage medium storage when data without periodic refreshing, therefore this structure can reduce the power consumption of data storage greatly, but due to PCM storage and access speed slower, therefore this structure on overall performance obviously decline.As shown in Figure 7, wherein 5 is nonvolatile memory to another kind of mixing storage organization, and 7 is logic detection module.Utilize in the alternative former DRAM primary memory 2 of storage unit in nonvolatile memory 5 and be positioned at the storage unit of tail end distributive province, thereby can greatly improve the refresh cycle, reduce refreshing frequency, greatly reduced former DRAM and refreshed power consumption.

Summary of the invention

In view of this, the present invention is based on mixing memory structure, under the prerequisite of considering the poorest storage unit, realize the reduction of refreshing frequency, save and refresh power consumption, and substantially do not affect the access performance of former DRAM.

For achieving the above object, concrete technical scheme is as follows:

A low-power consumption method for refreshing for mixing memory structure, described mixing memory structure comprises DRAM, nonvolatile memory and logic detection module, and the temperature sensor that can configure on described mixing memory, comprises the following steps:

Step 1, detects the poorest location information in described DRAM inside, and the poorest location information is stored in described nonvolatile memory;

Step 2, if described DRAM in busy state, described DRAM is with conventional refresh mode work, now the refresh cycle of described DRAM is the conventional refresh cycle;

Step 3, if described DRAM is in non-busy state, so described DRAM enters low-power consumption refresh mode, described low-power consumption refresh mode comprises responsive to temperature pattern and temperature-insensitive pattern, if select responsive to temperature pattern, enter so step 4, if select temperature-insensitive pattern, enter step 5;

Step 4, if described DRAM operates under responsive to temperature pattern, the storage unit in described nonvolatile memory substitutes the poorest storage unit detecting in the inherent step 1 of current reference temperature, reconfigures the described DRAM refresh cycle; If at a time detect that Current Temperatures changes to another temperature range, upgrade so the poorest location information, upgrade the refresh cycle;

Step 5, if described DRAM operates in temperature-insensitive pattern, the storage unit in described nonvolatile memory substitutes the poorest storage unit detecting in step 1, reconfigures the refresh cycle of described DRAM; If when at a time described DRAM running temperature exceedes setting, described DRAM can switch back conventional refresh mode by low-power consumption refresh mode.

Preferably, also comprise step 6: when detecting the described DRAM moving in busy state under low-power consumption refresh mode, so the data in described non-volatile memory cells are written back in described DRAM, described DRAM switches to conventional refresh mode.

Preferably, the poorest location information in described step 1 comprises the poorest location information based on temperature variation or the poorest location information based on temperature variation not.

Preferably, self refresh power consumption when described DRAM access power consumption is approached or is less than described DRAM, so described DRAM is in non-busy state.

Preferably, temperature inductor described in step 2 is responded to described DRAM current operating temperature, and described DRAM is with the new cycle T _ refresh_spec of whisk broom periodic refresh, and whether detects described DRAM in busy state.

Preferably, the detection method in described step 1 comprises:

Step 1.1, described DRAM refreshes for the first time detection under initial testing temperature T emp, and the refresh cycle is T_refresh_spec, and the described refresh cycle is the shortest refresh cycle;

Step 1.2, record detects the poorest location information under current refresh cycle T_refresh;

Step 1.3, to being operated in the DRAM under responsive to temperature pattern, needs to detect the poorest location information under different temperatures; First judge whether current probe temperature reaches upper limit of detection temperature T emp_max, do not reach and Current Temperatures is improved to △ T after current detection, this new probe temperature is covered into Temp, then return to step 1.1 and again detect; Otherwise, this probe temperature setting is returned to the emp of initial testing temperature T for the first time, then carry out step 1.4; If described DRAM is only operated under temperature-insensitive pattern, so directly enter step 1.4;

Step 1.4, judges whether the current test refresh cycle reach the upper limit and detect refresh cycle T_refresh_max, if reach, stops detecting and enters step 1.5; If do not reach, improve the refresh cycle by improving △ t time delay, this stylish refresh cycle is covered into T_refresh_spec, then return to step 1.1;

Step 1.5, analyzing and testing result, and optimal case result is saved in nonvolatile memory.

Preferably, in described step 1.5, for the described DRAM that can be operated under responsive to temperature pattern, need to be recorded in the optimal case under different temperatures scope; For the described DRAM being only operated under temperature-insensitive pattern, only need to be recorded in the optimal case in current reference temperature.

Preferably, refreshing in described step 1.1 detects as distributed refresh detection or centralized refresh detection.

Preferably, the poorest location information in described step 1.2 is in current reference temperature, and data hold time is less than the physical address information of the described DRAM storage unit of current described DRAM refresh cycle.

With respect to prior art, the advantage of technical scheme of the present invention has:

Technical scheme of the present invention realizes the reduction of refreshing frequency under the prerequisite of considering the poorest storage unit, saves and refreshes power consumption, and substantially do not affect the access performance of former DRAM.

Accompanying drawing explanation

The accompanying drawing that forms a part of the present invention is used to provide a further understanding of the present invention, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:

Fig. 1 refreshes power consumption with DRAM volume change schematic diagram;

Fig. 2 is storage unit hold facility distribution plan in DRAM;

Fig. 3 is two kinds of refresh mode sequential schematic diagram in DRAM;

Fig. 4 is that in DRAM, storage unit hold facility varies with temperature schematic diagram;

Fig. 5 is the structural representation of auto thermal compensation self-refresh technology;

Fig. 6 is IBM mixing DRAM structural representation;

Fig. 7 is based on the mixing DRAM structural representation of poor storage unit;

Fig. 8 is that the embodiment of the present invention is mixed the implementation method schematic flow sheet that DRAM low-power consumption refreshes;

Fig. 9 is that the embodiment of the present invention detects the poorest location information schematic flow sheet in DRAM;

Figure 10 is embodiment of the present invention DRAM block array schematic diagram;

Figure 11 is the poorest storage unit sequential chart of embodiment of the present invention Distributed Detection;

Figure 12 is that embodiment of the present invention DRAM block array is divided into m sub-cell schematics;

Figure 13 is example 1 sequential chart of the present invention;

Figure 14 is the poorest storage unit sequential chart of the centralized detection of the embodiment of the present invention;

Figure 15 is example 2 sequential charts of the present invention;

Figure 16 is the poorest memory unit address exemplary plot of the present invention;

Figure 17 is that the poorest number of memory cells of the embodiment of the present invention varies with temperature schematic diagram;

Figure 18 is that the poorest number of memory cells of the embodiment of the present invention improved and changes schematic diagram with the refresh cycle;

Figure 19 is embodiment of the present invention DRAM structure piecemeal and hierarchy schematic diagram;

Figure 20 is that embodiment of the present invention operating system is improved mixing DRAM example performance figure.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.

It should be noted that, in the situation that not conflicting, the feature in embodiment and embodiment in the present invention can combine mutually.

Below with reference to accompanying drawing, embodiments of the invention are done to concrete explaination.

In the time that DRAM is busy, DRAM main power consumption is access power consumption, and DRAM is non-when busy, and DRAM main power consumption is for refreshing power consumption.Embodiments of the invention are basic based on the poorest storage unit, and as shown in Figure 7, wherein 2 is DRAM storage array to structure, 5 is nonvolatile memory, and 7 is logic detection module, and 8 is temperature sensor, it can be that mixing dram chip is built-in, can be also in system.If Temperature Detector is in DRAM external system, once temperature range changes, external system need send instruction to dram chip to adjust so; If be present in this DRAM inside, sending instruction DRAM without external system so can adjust automatically.

The implementation method flow process of the embodiment of the present invention is as shown in Figure 8:

Step 1, mix dram chip and first detect the poorest location information in inside, detection comprises the poorest location information based on temperature variation or the poorest location information based on temperature variation not, and the poorest location information is stored in nonvolatile memory 5.

Step 2, in the time that DRAM normally moves, logic detection module detects DRAM running status, if be operated in busy state, now to DRAM refresh the non-main power consumption of power consumption, now DRAM is with conventional refresh mode work.

Step 3, if need be operated in non-busy state, DRAM will enter low-power consumption refresh mode so, if " responsive to temperature pattern " enters step 4 so, if " temperature-insensitive pattern " enters step 5.

Step 4, if DRAM operates under responsive to temperature pattern, substitute the poorest storage unit detecting in the inherent step 1 of current reference temperature by the storage unit in nonvolatile memory, the configuration new refresh cycle of DRAM, DRAM with new refresh operation cycle under low-power consumption refresh mode.If at a time detect that Current Temperatures changes to another temperature range, upgrade so the poorest location information, upgrade the refresh cycle.If it is busy at a time to detect that DRAM duty is converted to, enter so step 6.

Step 5, if DRAM operates in temperature-insensitive pattern, substitutes by the storage unit in nonvolatile memory the poorest storage unit detecting in step 1 equally, the configuration new refresh cycle of DRAM.If when at a time DRAM running temperature exceedes setting (such as 85 ℃), DRAM can switch back conventional refresh mode by low-power consumption refresh mode, enters step 6.

Step 6, no matter the DRAM moving under low-power consumption refresh mode is with responsive to temperature pattern or temperature-insensitive mode operation, once detect that running status is busy, can immediately the data in non-volatile memory cells be written back to the designating unit in DRAM so, configuration DRAM gets back to the conventional refresh cycle, then switches to conventional refresh mode.

Embodiments of the invention switch under low-power consumption refresh mode and conventional refresh mode according to running status.

First the step 1 of the embodiment of the present invention is to detect in DRAM position and the data hold time of poor storage unit.

The DRAM of the embodiment of the present invention refreshes detection method as shown in Figure 9:

Step 1.1:DRAM refreshes for the first time detection under initial testing temperature T emp, refresh cycle is T_refresh_spec, this refresh cycle should equal the shortest refresh cycle stipulating on DRAM databook, for example 64ms, and mode can be that distributed refresh detects or centralized refresh detects.

Step 1.2: record detects the poorest location information under current refresh cycle T_refresh.

Step 1.3: to being operated in the DRAM under responsive to temperature pattern, need to detect the poorest location information under different temperatures.First judge whether current probe temperature reaches upper limit of detection temperature T emp_max, do not reach and Current Temperatures is improved to △ T after current detection, this new probe temperature is covered into Temp, then return to step 1.1 and again detect; Otherwise, this probe temperature setting is returned to the emp of initial testing temperature T for the first time, then carry out step 1.4; If DRAM is only operated under temperature-insensitive pattern, so directly enter step 1.4.

Step 1.4: judge whether the current test refresh cycle reach the upper limit and detect refresh cycle T_refresh_max, if reach, stop detecting and enter step 1.5; If do not reach, improve the refresh cycle by improving △ t time delay, this stylish refresh cycle is covered into T_refresh_spec, then return to step 1.1.

Step 1.5: analyzing and testing result, and optimal case result is saved in nonvolatile memory 5.For the DRAM that can be operated under responsive to temperature pattern, need to be recorded in the optimal case under different temperatures scope; For the DRAM being only operated under temperature-insensitive pattern, only need to be recorded in the optimal case in current reference temperature.

For step 1.1, suppose a DRAM block array as shown in figure 10, word line has n capable, and bit line has l row.Each word line and bit line intersection point are a basic storage unit, altogether just have n × l storage unit.At a certain temperature, in order to obtain the data holding ability information of each storage unit, need first to data writing in each storage unit, the data that write can be full 0 or complete 1, also or 55(101101) sequence, also or AA(10101010) sequence etc.And then data writing is exactly read data after a period of time, if sense data is consistent with data writing, shows so that the data hold time of this storage unit at least equals described in (also or be greater than) during this period of time.Data writing or accessing-data method have two kinds, distributed and centralized.

The sequential chart of distributed refresh as shown in figure 11, if k is described DRAM data input/output port, i.e. DRAM inputoutput data bit wide, the maximum data bit wide of namely once accessing DRAM, as shown in Figure 7.Concerning k storage unit, the time that write operation needs is write pulse time t_write_dis and postpones t_delay1_dis, the time that read operation needs is read pulse time t_read_dis and postpones t_delay2_dis, wherein t_write_dis is more than or equal to the shortest write time of the elementary cell k data that DRAM allows, and t_read_dis is more than or equal to the shortest output time of the elementary cell k data that DRAM allows.After all unit being carried out to write operation under a refresh cycle, immediately all storage unit are carried out to read operation, whether detection data under this refresh cycle are intact.K storage unit can be write or read to write pulse or read pulse, need to read or write so concerning n × l storage unit

inferior, in the test period, read cycle and write cycle time are respectively:

$T\_\mathrm{write}\_\mathrm{dis}=\left(\frac{n\&times;l}{k}\right)\&times;(t\_\mathrm{write}\_\mathrm{dis}+t\_\mathrm{<figure-callout\; id="1"\; label="delay"\; filenames="HDA0000470058410000012.png,HDA0000470058410000032.png"\; state="\{\{state\}\}">delay</figure-callout>}1\_\mathrm{dis})---\left(1\right)$

$T\_\mathrm{read}\_\mathrm{dis}=\left(\frac{n\&times;l}{k}\right)\&times;(t\_\mathrm{read}\_\mathrm{dis}+t\_\mathrm{<figure-callout\; id="2"\; label="delay"\; filenames="HDA0000470058410000032.png,HDA0000470058410000041.png"\; state="\{\{state\}\}">delay</figure-callout>}2\_\mathrm{dis})---\left(2\right)$

T_test_dis=T_write_dis+T_read_dis （3）

A test period time T _ test_dis comprises write cycle time T_write_dis and read cycle T_read_dis.First write pulse write k storage unit and with it the test duration T_test0_dis between corresponding first read pulse be:

$T\_\mathrm{<figure-callout\; id="0"\; label="test"\; filenames="HDA0000470058410000011.png,HDA0000470058410000121.png"\; state="\{\{state\}\}">test</figure-callout>}0\_\mathrm{dis}=\left(\frac{n\&times;l}{k}\right)\&times;(t\_\mathrm{write}\_\mathrm{dis}+t\_\mathrm{<figure-callout\; id="1"\; label="delay"\; filenames="HDA0000470058410000012.png,HDA0000470058410000032.png"\; state="\{\{state\}\}">delay</figure-callout>}1\_\mathrm{dis})---\left(4\right)$

Test duration T_test1_dis between second write pulse and with it corresponding second read pulse is:

$T\_\mathrm{<figure-callout\; id="1"\; label="test"\; filenames="HDA0000470058410000012.png,HDA0000470058410000032.png"\; state="\{\{state\}\}">test</figure-callout>}1\_\mathrm{dis}=(\frac{n\&times;l}{k}-1)\&times;(t\_\mathrm{write}\_\mathrm{dis}+t\_\mathrm{<figure-callout\; id="1"\; label="delay"\; filenames="HDA0000470058410000012.png,HDA0000470058410000032.png"\; state="\{\{state\}\}">delay</figure-callout>}1\_\mathrm{dis})+(t\_\mathrm{read}\_\mathrm{dis}+t\_\mathrm{<figure-callout\; id="2"\; label="delay"\; filenames="HDA0000470058410000032.png,HDA0000470058410000041.png"\; state="\{\{state\}\}">delay</figure-callout>}2\_\mathrm{dis})---\left(5\right)$

By that analogy, until the test duration between last write pulse and last read pulse be

$T\_\mathrm{testN}\_\mathrm{dis}=(t\_\mathrm{write}\_\mathrm{dis}+t\_\mathrm{<figure-callout\; id="1"\; label="delay"\; filenames="HDA0000470058410000012.png,HDA0000470058410000032.png"\; state="\{\{state\}\}">delay</figure-callout>}1\_\mathrm{dis})+(\frac{n\&times;l}{k}-1)\&times;(t\_\mathrm{read}\_\mathrm{dis}+t\_\mathrm{<figure-callout\; id="2"\; label="delay"\; filenames="HDA0000470058410000032.png,HDA0000470058410000041.png"\; state="\{\{state\}\}">delay</figure-callout>}2\_\mathrm{dis})---\left(6\right)$

Identical to the test duration of all storage unit for guaranteeing, need to guarantee the write pulse t_write_dis of k storage unit to add that stand-by period t_delay1_dis equals its read pulse t_read_dis to add stand-by period t_delay2_dis, and be designated as unit_runtime T_unit_dis,

T_unit_dis=t_write_dis+t_delay1_dis=t_read_dis+t_delay2_dis（7）

So just can guarantee all storage unit, the test duration is all identical,

$T\_\mathrm{<figure-callout\; id="0"\; label="test"\; filenames="HDA0000470058410000011.png,HDA0000470058410000121.png"\; state="\{\{state\}\}">test</figure-callout>}0\_\mathrm{dis}=T\_\mathrm{<figure-callout\; id="1"\; label="test"\; filenames="HDA0000470058410000012.png,HDA0000470058410000032.png"\; state="\{\{state\}\}">test</figure-callout>}1\_\mathrm{dis}=......=T\_\mathrm{testN}\_\mathrm{dis}=\frac{n\&times;l}{k}\&times;T\_\mathrm{unit}\_\mathrm{dis}---\left(8\right)$

For convenient test, can make read pulse the same with the write pulse time,

$t\_\mathrm{write}\_\mathrm{dis}=t\_\mathrm{read}\_\mathrm{dis}\&DoubleRightArrow;t\_\mathrm{<figure-callout\; id="1"\; label="delay"\; filenames="HDA0000470058410000012.png,HDA0000470058410000032.png"\; state="\{\{state\}\}">delay</figure-callout>}1\_\mathrm{dis}=t\_\mathrm{<figure-callout\; id="2"\; label="delay"\; filenames="HDA0000470058410000032.png,HDA0000470058410000041.png"\; state="\{\{state\}\}">delay</figure-callout>}2\_\mathrm{dis}---\left(9\right)$

Can be known by foregoing description, in a test period T_test_dis, the refresh time T_refresh of unit is the half of test period T_test_dis,

$T\_\mathrm{refresh}=\frac{1}{2}T\_\mathrm{test}\_\mathrm{dis}=\frac{n\&times;l}{k}\&times;T\_\mathrm{unit}\_\mathrm{dis}---\left(10\right)$

If within this test period, concerning each storage unit, if data writing and sense data are consistent, illustrate that so the retention time of this storage unit is greater than or equal to this refresh cycle; If data writing and sense data are inconsistent, illustrate that so this storage unit can not keep data integrity under this refresh cycle, be the poorest storage unit.

If because DRAM capacity is too large, even if T_delay1_dis and T_delay2_dis are 0, also cannot be within the test period of half (

for example, for the conventional refresh time defining in DRAM product manual, 64ms, 128ms) all storage unit are carried out to write operation or read operation,

$\frac{n\&times;l}{k}\&times;T\_\mathrm{unit}\_\mathrm{dis}>\frac{1}{2}T\_\mathrm{test}\_\mathrm{dis}=T\_\mathrm{refresh}---\left(11\right)$

Can consider so DRAM storage block to be divided into m subelement, as shown in figure 12.A test period is only carried out data writing and sense data test to a subelement, more next subelement is tested in next test period.So one test period build-in test number of memory cells be n × l/m, concerning each storage unit, refresh time is:

$T\_\mathrm{refresh}=\left(\frac{n\&times;l}{m\&times;k}\right)\&times;T\_\mathrm{unit}\_\mathrm{dis}---\left(12\right)$

Read and write so n × l storage unit and need m test period.

Lifting an instantiation 1 below further sets forth.

Suppose that a DRAM block array is 1Mbit=1K*1K=1024*1024, data inputoutput bandwidth is 32, i.e. k=32.Suppose a test period T_test_dis=128ms, concerning each storage unit, refresh time T_refresh=64ms.For convenience of test, data writing is complete 1 sequence, and read operation pulse and write operation pulse all need t_read_dis=t_write_dis=200ns, concerning every 32 storage unit, writes data or read data required time is 200ns.The write pulse needing or read pulse are counted N and are:

$N=\frac{1024\&times;1024}{32}=32768$

Unit_runtime T_unit is:

$T\_\mathrm{unit}\_\mathrm{dis}=\frac{T\_\mathrm{refresh}}{N}=\frac{64\mathrm{ms}}{32768}\&ap;1953\mathrm{ns}$

Be the time delay after each read pulse or write pulse so:

t_delay1_dis=t_delay2_dis=T_unit_dis-t_ead_dis=1953-200=1753ns

Obviously to this DRAM piece without being divided into multiple subelements.Data preparation is as shown in table 1, under this test period to the test sequence figure of DRAM as shown in figure 13.

Table 1

Centralized refresh sequential as shown in figure 14.Different from distributed refresh mode, under a test period, all unit are carried out to centralized write operation and more all storage unit are carried out to centralized read operation after one section of delay, whether detection data under this test period are intact.If k is described DRAM data input/output port, the maximum data bit wide of namely once accessing DRAM.Concerning every k storage unit, the time that write operation needs is write pulse time t_write_burst, concerning n × l storage unit, need to read or write

inferior, in the write cycle time within test period after N concentrated write pulse through postponing t_delay_burst, be exactly and then N concentrated read pulse in the read cycle, the time that read operation needs is read pulse time t_read_burst.In the test period, read cycle and write cycle time are respectively:

$T\_\mathrm{write}\_\mathrm{burst}=\left(\frac{n\&times;l}{k}\right)\&times;t\_\mathrm{write}\_\mathrm{burst}+t\_\mathrm{delay}\_\mathrm{burst}---\left(13\right)$

$T\_\mathrm{read}\_\mathrm{burst}=\left(\frac{n\&times;l}{k}\right)\&times;t\_\mathrm{read}\_\mathrm{burst}---\left(14\right)$

T_test_burst=T_write_burst+T_read_burst（15）

A test period time T _ test_burst comprises write cycle time T_write_burst and read cycle T_read_burst.First write pulse write k storage unit and with it the test duration T_test0_burst between corresponding first read pulse be:

$T\_\mathrm{<figure-callout\; id="0"\; label="test"\; filenames="HDA0000470058410000011.png,HDA0000470058410000121.png"\; state="\{\{state\}\}">test</figure-callout>}0\_\mathrm{burst}=\left(\frac{n\&times;l}{k}\right)\&times;t\_\mathrm{write}\_\mathrm{burst}+t\_\mathrm{delay}\_\mathrm{burst}---\left(16\right)$

Test duration T_test between second write pulse and with it corresponding second read pulse =1_burst is:

$T\_\mathrm{<figure-callout\; id="1"\; label="test"\; filenames="HDA0000470058410000012.png,HDA0000470058410000032.png"\; state="\{\{state\}\}">test</figure-callout>}1\_\mathrm{burst}=(\frac{n\&times;l}{k}-1)\&times;t\_\mathrm{write}\_\mathrm{burst}+t\_\mathrm{delay}\_\mathrm{burst}+t\_\mathrm{read}\_\mathrm{burst}---\left(17\right)$

By that analogy, until the test duration between last write pulse and last read pulse be

$T\_\mathrm{testN}\_\mathrm{burst}=t\_\mathrm{write}\_\mathrm{burst}+t\_\mathrm{delay}\_\mathrm{burst}+(\frac{n\&times;l}{k}-1)\&times;t\_\mathrm{read}\_\mathrm{burst}---\left(18\right)$

Identical to the test duration of all storage unit for guaranteeing, need to guarantee the write pulse time t_write_burst of every k storage unit to equal to its read pulse time t_read_burst,

t_write_burst=t_read_burst （19）

So just can guarantee all storage unit, refresh time T_refresh is identical, supposes that the time of N concentrated write pulse is denoted as T_total_burst, so

$T\_\mathrm{<figure-callout\; id="0"\; label="test"\; filenames="HDA0000470058410000011.png,HDA0000470058410000121.png"\; state="\{\{state\}\}">test</figure-callout>}0\_\mathrm{burst}=T\_\mathrm{<figure-callout\; id="1"\; label="test"\; filenames="HDA0000470058410000012.png,HDA0000470058410000032.png"\; state="\{\{state\}\}">test</figure-callout>}1\_\mathrm{burst}=......=T\_\mathrm{testN}\_\mathrm{burst}=T\_\mathrm{refresh}$

$=\frac{n\&times;l}{k}\&times;t\_\mathrm{write}\_\mathrm{burst}+t\_\mathrm{delay}\_\mathrm{burst}=T\_\mathrm{total}\_\mathrm{burst}+t\_\mathrm{delay}\_\mathrm{burst}---\left(20\right)$

In a test period T_test, the refresh time T_refresh of unit is so:

$T\_\mathrm{refresh}=\frac{n\&times;l}{k}\&times;t\_\mathrm{write}\_\mathrm{burst}+t\_\mathrm{delay}\_\mathrm{burst}---\left(21\right)$

If within this test period, concerning each storage unit, if data writing and sense data are consistent, illustrate that so the retention time of this storage unit is greater than or equal to this refresh cycle; If data writing and sense data are inconsistent, illustrate that so this storage unit can not keep data integrity under this refresh cycle, be the poorest storage unit.

If because DRAM capacity is too large, even if T_delay_burst is 0, also cannot be within a T_total_burst time (in being DRAM product manual, define conventional refresh time, for example 64ms, 128ms etc.) all storage unit are carried out to write operation one time,

$\frac{n\&times;l}{k}\&times;t\_\mathrm{write}\_\mathrm{burst}>T\_\mathrm{refresh}---\left(22\right)$

Can consider so DRAM storage block to be divided into m subelement, also as shown in figure 12.A test period is only carried out data writing and sense data test to a subelement, more next subelement is tested in next test period.So one test period build-in test number of memory cells be n × l/m, concerning each storage unit, refresh time is:

$T\_\mathrm{refresh}=\left(\frac{n\&times;l}{m\&times;k}\right)\&times;t\_\mathrm{write}\_\mathrm{burst}+t\_\mathrm{delay}\_\mathrm{burst}---\left(23\right)$

Read and write so n × l storage unit and need m test period.

Lifting an instantiation 2 below further sets forth.

Suppose that a DRAM block array is 256Mbit=32K × 8K=32768 × 8192, data inputoutput bandwidth is 32, i.e. k=32.Suppose refresh time T_refresh=64ms.For convenience of test, data writing is complete 1 sequence, and read operation pulse and write operation pulse all need t_read_burst=t_write_burst=200ns, concerning every 32 storage unit, writes data or read data required time is 200ns.The write pulse needing or read pulse are counted N and are:

$N=\frac{32768\&times;8192}{32}=8388608$

Concentrate write pulse time T _ total_burst to be:

T_total_burst=N×t_write_brust=8388608×200n=1677.7216ms＞64ms

Obviously need be divided into multiple subelements to this DRAM piece, can be divided into 32 subelements, so in each subelement, in the test period, write pulse or read pulse number are:

$N\_m=\frac{N}{m}=8088608/32=262144$

Concentrate write pulse time T _ total_burst to be:

t_total_burst=N_m×t_write_burst=262144×200n≈52.4288ms

Be the time delay after each write pulse:

t_delay_burst=T_refresh-t_total_burst=64-52.4288=11.5712ms

Data preparation is as shown in table 2, under this test period to the test sequence figure of DRAM as shown in figure 15.

Table 2:

Be to record the poorest location information detecting for step 1.2, the poorest location information of what is called is in current reference temperature, and data hold time is less than the physical address information of those DRAM storage unit of current DRAM refresh cycle.For example detect that the poorest storage unit can be as shown in figure 16, we know that DRAM refreshes with behavior unit and refresh, within a refresh cycle (such as 64ms, 128ms etc.), each provisional capital in DRAM can be by refresh all successively once, take distributed refresh as example, if a DRAM piece has 8k capable, refresh cycle is 128ms, every 15.6us that crosses, and all DRAM unit in a line all can be refreshed once.If DRAM capacity rises, in a DRAM piece, there is 16k capable, in the time window of 15.6us, just have so two row and be successively refreshed, the above-mentioned line number being refreshed that needs is in a certain time interval referred to as to refresh group (refresh bundles).In Figure 16 (a), be to refresh group with a behavior, stain representative the poorest storage unit position, (b) refreshes group with two behaviors.The poorest location information can be a single the poorest storage unit institute corresponding address, comprise wordline address, bit line address etc., can be only also this addresses of being expert in the poorest unit, being wordline address, can be also the address (only consider to refresh group here and be greater than 1 row) of refreshing group.For three's contrast, as shown in table 3.If only record the poorest single memory unit address, advantage is little to the unit writing in nonvolatile memory under low-power consumption mode, thereby to DRAM performance impact minimum, shortcoming is that word line, the bit line address quantity of information of record is many, and this poorest storage unit be expert at and still need to refresh.If recorded information is the poorest storage unit place row address, advantage is under low-power consumption mode, this row is without refreshing, the quantity of information of record is less, shortcoming is under low-power consumption mode, to need the equal unloading in all this row unit to nonvolatile memory, the amount of writing is many, larger to DRAM performance impact.If the information of record is one and refreshes group address, advantage be this refresh group under low-power consumption mode all without refreshing, the information of record is minimum, and shortcoming is that this refreshes all row under group and all needs unloading to nonvolatile memory at low-power consumption mode, to DRAM performance impact maximum.

Table 3:

On the above-mentioned two kinds bases of refreshing mode, consider that DRAM is operated in responsive to temperature pattern and temperature-insensitive pattern detects DRAM respectively.For step 1.3, DRAM can be operated under responsive to temperature pattern, after having detected under initial detecting cycle T _ refresh_spec and initial temperature Temp, Current Temperatures need be improved to △ T and re-start detection, the temperature range for example detecting can be set as Temp+ △ T, Temp+2 △ T, Temp+3 △ T, Temp+4 △ T ... Temp_max.Until detected temperatures reaches highest detection temperature T emp_max, be for example 90 ℃, stop detecting.Along with temperature raises, the poorest number of memory cells in DRAM piece also can raise gradually, as shown in figure 17.Improving the refresh cycle in step 1.4 time by raising time delay (t_delay1_dis or t_delay2_dis, T_delay_burst) is T_refresh1, can under different temperatures scope, detect equally the poorest location information.So circulation, reaches maximum sense cycle T_refresh_max until detect the refresh cycle in step 1.4.

For step 1.4, by improving (if distributed refresh time delay, be t_delay1_dis time delay, if centralized refresh, be T_delay_burst time delay) improve the refresh cycle, and under the new refresh cycle again detect, until the poorest number of memory cells detecting exceedes the maximum size of nonvolatile memory, reach maximum refresh detection time T_refresh_max stop detect.Along with the refresh cycle improves, the poorest storage unit is constantly accumulation also, as shown in figure 18.Along with the refresh cycle improves constantly, although refreshing power consumption constantly reduces, but the storage unit being replaced also increases thereupon, replacing power consumption also can increase, due to the access performance of nonvolatile memory not as good as access performance to former DRAM piece, the storage unit being replaced in former DRAM increases and also can cause mixing DRAM access performance and decline to some extent, so have a compromise between reducing refreshing power-dissipation-reduced and performance.

For step 1.5, to being operated in the DRAM under responsive to temperature pattern, the poorest location information detecting can be as shown in table 4, detect respectively the poorest location information under different temperatures scope and under the different refresh cycle, and be recorded within the scope of different temperatures the poorest location information under the optimum refresh cycle, the poorest location information under the so-called optimum refresh cycle refreshes power consumption and can significantly decline under this refresh cycle, can not affect in a large number again and mix the performance of DRAM under low-power consumption mode.For not needing to be operated in the DRAM under responsive to temperature pattern, only detect the poorest location information of in certain specific range of temperatures (such as under ambient temperature), while test such as room temperature, DRAM is just from the system operation that powers on, be recorded in the poorest location information under the optimum refresh cycle at this temperature, recorded information is as shown in table 5.

Table 4:

Table 5:

Step 1 has detected after the information of the poorest storage unit, step 2 just starts to detect DRAM running status in the time that DRAM normally moves, first temperature inductor induction DRAM current operating temperature, DRAM has just started to power on, DRAM is with the new cycle T _ refresh_spec of whisk broom periodic refresh, and whether detects DRAM in busy state.If be operated in busy state, now to DRAM refresh the non-main power consumption of power consumption, now DRAM is with conventional refresh mode work.This state can be judged by following information: our hypothesis to the read and write power consumption of DRAM with to refresh power consumption roughly suitable,

P _read≈P _write≈P _refresh （25）

If DRAM access power consumption is far longer than to the power consumption that refreshes to DRAM,

P _read+P _write>>P _refresh （26）

DRAM duty is just busy state so.In the refresh cycle, on average at least to every line operate twice, read or write, DRAM is just in busy state so.Under busy state, DRAM refreshes with the new cycle T _ refresh_spec of whisk broom; If contrary, DRAM access power consumption is approached and is even less than DRAM is refreshed to power consumption, judge that so DRAM is in non-busy state.Step 3 is that DRAM enters low-power consumption refresh mode by conventional refresh mode.

Step 4 operates under responsive to temperature pattern for DRAM.Due in operational process to responsive to temperature, therefore the detection of poor storage unit must be carried out in the time that dram chip is tested, in DRAM operational process, can adjust the refresh cycle according to temperature variation, reduce to greatest extent DRAM and refresh power consumption, apply more extensive.Now logic detection module is selected the optimum alternative under Current Temperatures, refresh cycle improves, read in the data of poor storage unit under this refresh cycle under this temperature range, and the data in these unit are stored to the designating unit in nonvolatile memory, complete the replacement of storage unit.Complete and replace the rear configuration refresh cycle, the refresh cycle is increased to the new refresh cycle by original T_refresh_spec.Under the new refresh cycle, when data in the storage unit being replaced in system request access DRAM, in the direct designating unit from nonvolatile memory of these data meetings, read in to read buffer (read buffer) and be accessed again, if next time is while reading the data in identical address again and to read in impact damper corresponding data capped, can directly from read buffer, directly read, and without reading from nonvolatile memory, it is unaffected that DRAM reads performance; If system request to be replaced in DRAM storage unit data writing time, data can first be written into particular address in corresponding write buffer (write buffer), and only have data in the time that the data on this address will be capped just can write to the designating unit in nonvolatile memory, not so as long as data can not be capped, also unaffected to DRAM write performance so.Because DRAM temperature in the time moving can change, once if exceeded or lower than place temperature range of above-mentioned refresh cycle, regain so the information of the poorest storage unit under new temperature range, and repeat above-mentioned conversion, replace the poorest storage unit under new temperature range, configure the new refresh cycle.

Step 5 operates under temperature-insensitive pattern for DRAM, under this pattern, needn't consider the temperature variation in specified for temperature ranges (such as lower than 85 ℃), so in DRAM the detection of poor storage unit can in the time that dram chip is tested, carry out, also can power on or lower electricity regularly carries out in system, for example can be regularly under system power up or system, carry out step 1 when electricity and detect the poorest location information in DRAM, and be saved in nonvolatile memory, regular object is can be by again detecting to upgrade the poorest location information when after DRAM is by long-time read-write operation, data retention declines.Under low-power consumption mode, the data in these unit are stored to the designating unit in nonvolatile memory, complete the replacement of storage unit.Complete and replace the rear configuration refresh cycle, the refresh cycle is increased to the new refresh cycle by original T_refresh_spec.If for example, because environment temperature exceedes designated value (85 ℃), system thinks that DRAM operation is busy, and DRAM will enter conventional refresh mode so.But temperature is brought up to more than 85 ℃, now DRAM is not necessarily operated under busy state, it may be due to around parts are busy with one's work that temperature raises, but DRAM itself is also in non-busy state, refreshes power consumption so temperature-insensitive pattern can not at utmost reduce DRAM.

Logic detection module detects state in real time, if get back to conventional refresh mode formula (26) and again set up if DRAM duty at a time detected, under normal mode, the power consumption that reads to DRAM is greater than the power consumption that refreshes to DRAM, and DRAM is in busy state so.Step 6 is that DRAM is transformed into conventional refresh mode again from low-power consumption refresh mode.The data that are now used for replacing in DRAM in the nonvolatile memory of poor storage unit will be written back to the storage unit of specifying in DRAM, reconfiguring the refresh cycle is the original refresh cycle, DRAM is to move under conventional refresh mode, with original refresh cycle T_refresh periodic refresh.

After above conversion, DRAM just can not carry out refresh operation with the higher refresh cycle under busy state, thereby greatly reduces and refresh power consumption.Above layoutprocedure has completed the conversion of DRAM from conventional refresh mode to low-power consumption refresh mode, and low-power consumption refresh mode is back to normal mode.

Figure 19 shows that a memory bar (DIMM), conventionally comprise several dram chips, form and each chip has some DRAM layer stacked package.For each DRAM layer, because the poorest storage unit distribution is different, thereby refresh cycle T_refresh also can be different.That is to say, in each dram chip, the refresh cycle can be different; And also can be operated under the different refresh cycles for each DRAM layer at different temperature.

Under low-power consumption refresh mode, the poorest storage unit is kept in nonvolatile memory, and in the time of these resources of system access, DRAM performance can decline to some extent.One of solution is exactly to adjust the access performance of nonvolatile memory.For example nonvolatile memory is phase transition storage (PCM), and we can adjust the component of phase-change material, reduces the retention time (retention) (being for example reduced to 3 days) of phase transition storage, thereby improves its reading speed, reaches the reading speed of DRAM.Such mixing DRAM performance is influenced hardly, just need to refresh once phase transition storage every the data hold time of phase transition storage, and such power consumption that refreshes is negligible.Two of solution was informed operating system by the poorest location information detecting exactly before entering low-power consumption refresh mode, the operating system look-up table (LUT) that can remap as far as possible like this, the content in group of refreshing that contains the poorest storage unit is deposited as far as possible to other and do not contained refreshing in group address of the poorest storage unit, and this is refreshed to group inefficacy, can under low-power consumption refresh mode, not go to use these to refresh group so, thereby avoid replacement operation, further reduced power consumption.As shown in Figure 20-A, suppose that in the corresponding DRAM of a LUT page table, a line is word line.Whether generally the corresponding page table of LUT is not paid close attention to place word line the poorest storage unit.If operating system can be known the poorest storage unit distribution situation, before entering low-power consumption refresh mode, page table upgrades again so, will be preferentially corresponding those the word lines of the poorest storage unit not of page table correspondence, then make to contain the word line of poor storage unit and lost efficacy, as shown in Figure 20-B.

Give an actual example below and further set forth.

In large server or data center, dram chip enormous amount, and each dram chip capacity is large, refreshes power consumption very high.At night or when festivals or holidays, because a large amount of servers can be in non-busy state, but concerning DRAM, but have to carry out periodic refresh, cause power wastage.Utilization the present invention is based on and mixes DRAM structure (Fig. 7) and propose a kind of novel implementation method and can greatly reduce and refresh power consumption.The most dram chip refresh cycle is 64ms, under non-busy state, the poorest storage unit in DRAM is substituted in the designating unit in nonvolatile memory, and the refresh cycle just can improve greatly, for example, bring up to 5s, has improved fully nearly 80 times! Suppose to refresh that once to need power consumption be 10mW, refresh so for former DRAM, the power consumption that refreshes in two days festivals or holidays is

$P=\frac{2\&times;24\&times;60\&times;60s}{64\mathrm{ms}}\&times;10\mathrm{mW}=27\mathrm{kW}$

If adopt low-power consumption refresh mode of the present invention, in 5s, only need refresh once, the power consumption that refreshes in two days festivals or holidays is

$P=\frac{2\&times;24\&times;60\&times;60s}{5s}\&times;10\mathrm{mW}=345.6W$

The two contrast is as shown in table 6, refreshes as seen power consumption and greatly reduces.

Table 6:

	Refresh cycle	Power consumption in two days
				Routine refreshes	64ms	27kW	Refresh power consumption high
Low-power consumption refreshes	5s	345.6W	Refresh power consumption very low

Based on above analysis, the present invention is based on mixing memory structure and propose a kind of novel implementation method, under the prerequisite of considering the poorest storage unit, realize the raising of refresh cycle, save and refresh power consumption, and substantially do not affect the memory property of former DRAM.

Above specific embodiments of the invention be have been described in detail, but it is as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that this practicality is carried out and alternative also all among category of the present invention.Therefore, equalization conversion and the modification done without departing from the spirit and scope of the invention, all should contain within the scope of the invention.

Claims (13)

1. the low-power consumption method for refreshing of a mixing memory structure, described mixing memory structure comprises DRAM, nonvolatile memory and logic detection module, and the temperature sensor that can configure on described mixing memory, it is characterized in that, comprise the following steps:

Step 1, detects the poorest location information in described DRAM inside, and the poorest location information is stored in described nonvolatile memory;

Step 2, if described DRAM in busy state, described DRAM is with conventional refresh mode work, now the refresh cycle of described DRAM is the conventional refresh cycle;

Step 3, if described DRAM is in non-busy state, so described DRAM enters low-power consumption refresh mode, described low-power consumption refresh mode comprises responsive to temperature pattern and temperature-insensitive pattern, if select responsive to temperature pattern, enter so step 4, if select temperature-insensitive pattern, enter step 5;

Step 4, if described DRAM operates under responsive to temperature pattern, the storage unit in described nonvolatile memory substitutes the poorest storage unit detecting in the inherent step 1 of current reference temperature, reconfigures the described DRAM refresh cycle; If at a time detect that Current Temperatures changes to another temperature range, upgrade so the poorest location information, upgrade the refresh cycle;

Step 5, if described DRAM operates in temperature-insensitive pattern, the storage unit in described nonvolatile memory substitutes the poorest storage unit detecting in step 1, reconfigures the refresh cycle of described DRAM; If when at a time described DRAM running temperature exceedes setting, described DRAM can switch back conventional refresh mode by low-power consumption refresh mode.

2. the low-power consumption method for refreshing of mixing memory structure as claimed in claim 1, it is characterized in that, also comprise step 6: when detecting the described DRAM moving in busy state under low-power consumption refresh mode, so the data in described non-volatile memory cells are written back in described DRAM, described DRAM switches to conventional refresh mode.

3. the low-power consumption method for refreshing of mixing memory structure as claimed in claim 2, it is characterized in that, the poorest location information in described step 1 comprises the poorest location information based on temperature variation or the poorest location information based on temperature variation not.

4. the low-power consumption method for refreshing of mixing memory structure as claimed in claim 3, is characterized in that, self refreshes power consumption when described DRAM access power consumption is approached or is less than described DRAM, and so described DRAM is in non-busy state.

5. the low-power consumption method for refreshing of mixing memory structure as claimed in claim 4, it is characterized in that, temperature inductor described in step 2 is responded to described DRAM current operating temperature, described DRAM is with the new cycle T _ refresh_spec of whisk broom periodic refresh, and whether detects described DRAM in busy state.

6. the low-power consumption method for refreshing of mixing memory structure as claimed in claim 1, is characterized in that, the detection method in described step 1 comprises:

Step 1.1, described DRAM refreshes for the first time detection under initial testing temperature T emp, and the refresh cycle is T_refresh_spec, and the described refresh cycle is the shortest refresh cycle;

Step 1.2, record detects the poorest location information under current refresh cycle T_refresh; Step 1.3, to being operated in the DRAM under responsive to temperature pattern, needs to detect the poorest location information under different temperatures; First judge whether current probe temperature reaches upper limit of detection temperature T emp_max, do not reach and Current Temperatures is improved to △ T after current detection, this new probe temperature is covered into Temp, then return to step 1.1 and again detect; Otherwise, this probe temperature setting is returned to the emp of initial testing temperature T for the first time, then carry out step 1.4; If described DRAM is only operated under temperature-insensitive pattern, so directly enter step 1.4;

Step 1.4, judges whether the current test refresh cycle reach the upper limit and detect refresh cycle T_refresh_max, if reach, stops detecting and enters step 1.5; If do not reach, improve the refresh cycle by improving △ t time delay, this stylish refresh cycle is covered into T_refresh_spec, then return to step 1.1;

Step 1.5, analyzing and testing result, and optimal case result is saved in nonvolatile memory.

7. the low-power consumption method for refreshing of mixing memory structure as claimed in claim 6, is characterized in that, in described step 1.5, for the described DRAM that can be operated under responsive to temperature pattern, need to be recorded in the optimal case under different temperatures scope; For the described DRAM being only operated under temperature-insensitive pattern, only need to be recorded in the optimal case in current reference temperature.

8. the low-power consumption method for refreshing of mixing memory structure as claimed in claim 7, is characterized in that, refreshing in described step 1.1 detects as distributed refresh detection or centralized refresh detection.

9. the low-power consumption method for refreshing of mixing memory structure as claimed in claim 8, it is characterized in that, the poorest location information in described step 1.2 is in current reference temperature, and data hold time is less than the physical address information of the described DRAM storage unit of current described DRAM refresh cycle.

10. the low-power consumption method for refreshing of mixing memory structure as claimed in claim 1, is characterized in that, under described responsive to temperature pattern, the described detection of poor storage unit is carried out in the time that dram chip is tested.

The low-power consumption method for refreshing of 11. mixing memory structures as claimed in claim 1, is characterized in that, under described temperature-insensitive pattern, in DRAM the detection of poor storage unit in the time that dram chip is tested, carry out; Or power on or lower electricity regularly carries out in system, can be by again detecting to upgrade the poorest location information when after DRAM is by long-time read-write operation, data retention declines.

The low-power consumption method for refreshing of 12. mixing memory structures as claimed in claim 9, is characterized in that, the poorest location information in described step 1.2 is a single the poorest storage unit institute corresponding address, comprises wordline address, bit line address; Or this address that the poorest storage unit is expert at, i.e. wordline address; Or need in a certain time interval the line number being refreshed, refresh the address of group.

The low-power consumption method for refreshing of 13. mixing memory structures as claimed in claim 12, it is characterized in that, also be included in to enter before low-power consumption refresh mode the poorest location information detecting is informed to operating system, the operating system look-up table (LUT) that remaps, first refresh content in group and deposit and do not contain second of the poorest storage unit to other and refresh in group address what contain the poorest storage unit, and refresh group by first and lost efficacy.

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