CN103809104A - Scanning clock pulse generator and scanning clock pulse generation method - Google Patents
Scanning clock pulse generator and scanning clock pulse generation method Download PDFInfo
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- CN103809104A CN103809104A CN201210447504.9A CN201210447504A CN103809104A CN 103809104 A CN103809104 A CN 103809104A CN 201210447504 A CN201210447504 A CN 201210447504A CN 103809104 A CN103809104 A CN 103809104A
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Abstract
The invention discloses a scanning clock pulse generator and a scanning clock pulse generation method for providing a plurality of intra-chip scanning clock pulses required by testing a plurality of elements to be tested. The scanning clock pulse generator includes: a receiving circuit for receiving an extra-chip scanning clock pulse; and a clock pulse processing circuit which is coupled to the receiving circuit for generating the plurality of intra-chip scanning clock pulses according to the received extra-chip scanning clock pulse; wherein the clock pulse edges of the plurality of intra-chip scanning clock pulses are staggered mutually, and the scanning clock pulse generator and the plurality of elements to be tested are arranged in a same chip. The scanning clock pulse generator of the invention can be used to reduce the condition that pins are occupied when the chip is in the scanning test mode because a plurality of scanning clock pulse inputs are needed, and can be used to generate multiple groups of internal scanning clock pulses having different phases at the same time to achieve the purpose of reducing the instantaneous test power.
Description
Technical field
Disclosed embodiment is relevant to the generation of scanning clock pulse, espespecially a kind of scanning clock pulse generator that can produce multiple scanning clock pulses and associated method.
Background technology
Sweep test (scan test) is splendid for the detectability of defective workmanship (process defect), no matter and circuit size or function are why, an accurate and single scoring numeral can be provided, and therefore sweep test has become chip volume production and has tested indispensable important indicator.But; in order to shorten the test duration; sweep test can allow circuit be triggered as much as possible on board (toggle) conventionally; to expect to detect the circuit of largest portion within the minimum time; therefore; power consumption when test power consumption (test power) tends to much larger than circuit normal operation, when serious, excessive electric current may cause chip to burn or cause test mistake to kill (over-kill).For fear of such shortcoming, circuit can be divided into traditionally to several less blocks, each block has the independent scanning clock pulse of oneself, each scanning clock pulse can not start in the time of test simultaneously, but there is each other a phase deviation (phase skew), in other words, the clock pulse edge of each scanning clock pulse staggers each other in the time of test.This practice has solved the excessive problem of test power consumption effectively, but, along with circuit complexity increases, circuit size is also constantly grown up, therefore the circuit under test in a chip to be measured need to be frittered into more block of cells, representative needs more scanning clock signals that provided by tester table to input to internal circuit from the scanning clock pulse input port of chip, but, the number of signals that stitch (pin) quantity after chip package and tester table can provide is all fixed, therefore the scanning clock signal number of Sustainable Growth will face the not enough problem of stitch (or test signal).
Consider the demand, therefore the required chip stitch (or test signal) of using when needing the design of an innovation to can effectively reducing sweep test with simple core on-chip circuit.
Summary of the invention
One of object of the present invention is to provide a kind of scanning clock pulse generator that can produce multiple scanning clock pulses and associated method to solve the problems referred to above.
According to the first embodiment of the present invention, disclose a kind of scanning clock pulse generator, in order to provide the multiple element under tests of test required multiple chip interscan clock pulses, this scanning clock pulse generator includes a receiving circuit, is used for receiving a chip and scans clock pulse outward; And a clock pulse treatment circuit, be coupled to this receiving circuit, be used for scanning clock pulse outward according to this received chip and produce the plurality of chip interscan clock pulse; Wherein the clock pulse edge of the plurality of chip interscan clock pulse staggers each other, and this scanning clock pulse generator and the plurality of element under test are arranged in same chip.
According to a second embodiment of the present invention, disclose a kind ofly in order to the scanning clock pulse generation methods of the required multiple chip interscan clock pulses of the multiple element under tests of test to be provided, include and receive a chip and scan clock pulse outward; And scan clock pulse outward according to this received chip and produce the plurality of chip interscan clock pulse; Wherein the clock pulse edge of the plurality of chip interscan clock pulse staggers each other.
By adopting scanning clock pulse generator proposed by the invention and scanning clock pulse generation methods, can be with producing multiple inner scanning clock pulses of organizing outs of phase by an external scan clock pulse of a chip exterior input more, reduce chip and cause the occupied situation of stitch because needing multiple scanning clock pulse inputs under scan testing mode, the inner scanning clock pulse that while scanning clock pulse generator of the present invention can produce many group outs of phase also can reach the object that reduces moment measured power.
Accompanying drawing explanation
Fig. 1 is the Organization Chart that the present invention scans the first one exemplary embodiment of clock pulse generator.
Fig. 2 is the Organization Chart that the present invention scans the second one exemplary embodiment of clock pulse generator.
Fig. 3 is the Organization Chart that the present invention scans the 3rd one exemplary embodiment of clock pulse generator.
Fig. 4 is the schematic diagram of an embodiment of the clock pulse commutation circuit shown in Fig. 3.
Fig. 5 is the circuit diagram of an embodiment of the controller shown in Fig. 4.
Wherein, description of reference numerals is as follows:
100,200,300 scanning clock pulse generators
102,202,302 chips
104 receiving circuits
106,206,306 clock pulse treatment circuits
108_1 ~ 108_M delay circuit
110,210 controllers
111 triggers
112_1 ~ 112_M scans time pulse domain
208_1 ~ 208_M, 308_1 ~ 308_M delay element
310 clock pulse commutation circuits
312 controllers
314 demoders
502,504,506 selector switchs
508,510,512 triggers
Embodiment
Please refer to Fig. 1, Fig. 1 is the Organization Chart that the present invention scans the first one exemplary embodiment of clock pulse generator.In this one exemplary embodiment, scanning clock pulse generator 100 includes a receiving circuit 104 and is coupled to a clock pulse treatment circuit 106 of receiving circuit 104, and wherein receiving circuit 104 is for receiving a chip outer (off-chip) scanning clock pulse sclk
off_chipand output scanning clock pulse sclk is to clock pulse treatment circuit 106, for example, one or more impact damper (buffer)/reverser (inverter) can be set in receiving circuit 104.In this embodiment, clock pulse treatment circuit 106 can produce (on-chip) scanning clock pulse sclk in multiple chips according to scanning clock pulse sclk
1, sclk
2..., sclk
m, in addition, preferably, these chip interscan clock pulses sclk
1, sclk
2..., sclk
mclock pulse edge (clock edge) stagger mutually each other, and be used to respectively be used as follow-up multiple scanning time pulse domain (scan clock domain) 112_1,112_2 ..., 112_M sweep test clock pulse.In other words, multiple chip interscan clock pulse sclk
1, sclk
2..., sclk
mfor drive the multiple element under tests in multiple scanning time pulse domains under scan testing mode, (but not in order to limit the scope of the invention) for instance, the plurality of element under test can comprise multiple triggers (flip flop) 111.In addition, scanning clock pulse generator 100 is arranged in same chip 102 with the plurality of scanning time pulse domain, and more particularly, scanning clock pulse generator 100 is arranged in same chip 102 with the plurality of element under test.
About clock pulse treatment circuit 106, its include a controller 110 and multiple delay circuit 108_1,108_2 ..., 108_M, its middle controller 110 is used for controlling data sequence input d_in and an input control signal hold produces M delayed control signal S according to scanning clock pulse sclk,
cTR1, S
cTR2..., S
cTRMinput to respectively multiple delay circuit 108_1,108_2 ..., in 108_M, thus, delay circuit 108_1,108_2 ..., 108_M can be respectively according to delayed control signal S
cTR1, S
cTR2..., S
cTRMcorresponding multiple retardations are added on scanning clock pulse sclk, and obtain the phase place relativeness of finally wanting to reach between multiple scanning clock pulses of follow-up multiple scanning time pulse domains, in other words, delay circuit 108_1,108_2 ..., 108_M is that the chip that individually postpones to be received in the mode of parallel processing scans clock pulse (that is sclk) outward, to produce respectively desired chip interscan clock pulse.
It should be noted, in the middle of this one exemplary embodiment, in order to reach the object of the input/output port (I/O port) of saving chip 102 simultaneously, the control data sequence input d_in of controller 110 inputs in the mode of sequence (serial), and arrange in pairs or groups input control signal hold and scanning clock pulse sclk are used as the foundation of controller 110 identification control data sequences input d_in, more particularly, user can set arbitrarily delay circuit 108_1 with controlling data sequence input d_in from chip exterior, 108_2, time delay/retardation of 108_M.But the input mode of controller 110 only as example explanation, is not restrictive condition of the present invention at this, any design that can reach similar functions, all belongs to the scope that the present invention is contained such as.
Please refer to Fig. 2, Fig. 2 is the Organization Chart that the present invention scans the second one exemplary embodiment of clock pulse generator.In this one exemplary embodiment, scanning clock pulse generator 200 includes aforesaid receiver 104 and a clock pulse treatment circuit 206, and wherein receiving circuit 104 is used for receiving a chip and scans clock pulse sclk outward
off_chipand output scanning clock pulse sclk is to clock pulse treatment circuit 206, so that clock pulse treatment circuit 206 is able to produce multiple chip interscan clock pulse sclk according to scanning clock pulse sclk
1, sclk
2..., sclk
m, have about chip interscan clock pulse sclk
1, sc lk
2..., sclk
mand follow-up multiple scanning time pulse domain 112_1,112_2 ..., operation between 112_M is substantially identical with aforesaid one exemplary embodiment with idea, therefore just seldom repeat at this.It should be noted, scanning clock pulse generator 200 and multiple scanning time pulse domain 112_1,112_2 ..., 112_M is arranged in same chip 202, more particularly, scanning clock pulse generator 200 is arranged in same chip with multiple element under tests.
About clock pulse treatment circuit 206, its include a controller 210 and multiple delay element 208_1,208_2 ..., 208_M, its middle controller 210 is for controlling data sequence input d_in according to scanning clock pulse sclk, one and an input control signal hold produces M delayed control signal S
cTR1, S
cTR2..., S
cTRMinput to respectively delay element 208_1,208_2 ..., in 208_M, it should be noted, in this one exemplary embodiment, delay element 208_1,208_2 ..., 208_M is that the mode being connected in series forms, that is to say that the output terminal of delay element 208_1 is coupled to the input end of the delay element 208_2 of next stage, the output terminal of delay element 208_2 is coupled to the input end of the delay element 208_3 of next stage, and the connected mode of subsequent delay element by that analogy.Thus, delay element 208_1,208_2 ..., 208_M can be respectively according to delayed control signal S
cTR1, S
cTR2..., S
cTRMcorresponding multiple retardations are added on scanning clock pulse sclk.For instance, take sclk as benchmark, scanning clock pulse sclk
1be the time delay that delay element 208_1 causes compared to the time delay of sclk, and scanning clock pulse sclk
2the summation of the time delay of causing for delay element 208_1 and delay element 208_2 compared to time delay of sclk, the rest may be inferred, therefore last scanning clock pulse sclk
mcompared to the time delay of sclk be delay element 208_1,208_2 ..., 208_M time delay of causing summation.In other words, delay element 208_1,208_2 ..., 208_M is that the chip that postpones in order to be received in serial connection mode scans clock pulse (that is sclk) outward, to produce respectively desired chip interscan clock pulse.In addition much more no longer, the operating process of controller 210 is identical with aforesaid one exemplary embodiment, just to repeat at this.
Please refer to Fig. 3, Fig. 3 is the Organization Chart that the present invention scans the 3rd one exemplary embodiment of clock pulse generator.In this one exemplary embodiment, scanning clock pulse generator 300 includes aforesaid receiver 104 and a clock pulse treatment circuit 306, and wherein receiving circuit 104 is to scan clock pulse sclk outward for receiving a chip
off_chipand output scanning clock pulse sclk is to clock pulse treatment circuit 306, so that clock pulse treatment circuit 306 is able to produce multiple chip interscan clock pulse sclk according to scanning clock pulse sclk
1, sclk
2..., sclk
m, have about chip interscan clock pulse sclk
1, sclk
2..., sclk
mand follow-up multiple scanning time pulse domain 112_1,112_2 ..., operation between 112_M is substantially identical with aforesaid one exemplary embodiment with idea, therefore just seldom repeat at this.It should be noted, scanning clock pulse generator 300 and multiple scanning time pulse domain 112_1,112_2 ..., 112_M is arranged in same chip 202, more particularly, scanning clock pulse generator 300 is arranged in same chip with multiple element under tests.
About clock pulse treatment circuit 306, its include a clock pulse commutation circuit 310 and multiple delay element 308_1,308_2 ..., 308_M, wherein delay element 308_1,308_2 ..., the scanning clock pulse sclk that exports of 308_M
1', sclk
2' ..., sclk
m' input to respectively clock pulse commutation circuit 310, please note, in this one exemplary embodiment, delay element 308_1,308_2 ..., 308_M is that the mode being connected in series forms, that is to say, the output terminal of delay element 308_1 is coupled to the input end of the delay element 308_2 of next stage, and the output terminal of delay element 308_2 is coupled to the input end of the delay element 308_3 of next stage, and the connected mode of subsequent delay element by that analogy.In addition, clock pulse commutation circuit 310 can according to scanning clock pulse sclk, control data sequence input d_in and an input control signal hold by by delay element 308_1,308_2 ..., the scanning clock pulse sclk that inputs of 308_M
1', sclk
2' ..., sclk
m' do the switching in corresponding order, and further will scan clock pulse sclk again
1', sclk
2' ..., sclk
m' take new Sequential output as chip interscan clock pulse sclk
1, sclk
2..., sclk
mthus, can by scanning clock pulse sclk, control data sequence input d_in and input control signal hold change follow-up multiple scanning time pulse domain 112_1,112_2 ..., 112_M scanning clock pulse set, that is to say the scanning clock pulse that user can reset element under test from chip exterior phase relation each other.
Fig. 4 is the schematic diagram of an embodiment of the clock pulse commutation circuit 310 shown in Fig. 3.Clock pulse commutation circuit 310 includes a controller 312 and a demoder 314, its middle controller 312 reads the control data sequence input d_in of outside input according to scanning clock pulse sclk and input control signal hold, and be converted into control data parallel output d_out0, d_out1 ..., d_outM to demoder 314, using as change sclk
1', sclk
2' ..., sclk
m' order be sclk
1, sclk
2..., sclk
mfoundation.Please refer to Fig. 5, Fig. 5 is the circuit diagram of an embodiment of the controller 312 shown in Fig. 4.Controller 312 includes the multiple selector switchs (selector/multiplexer) 502 that switch input according to input control signal hold, 504, 506, and the multiple triggers (for example D flip-flop) 508 that driven by scanning clock pulse sclk, 510, 512, in the time that control signal hold reduces to 0 from 1, one first bit of controlling data sequence input d_in can input to trigger 508 and be stored in wherein, until next clock pulse, the first bit can be input to trigger 510 and be stored in wherein, and a second bit of controlling data sequence input d_in can input to trigger 508 and be stored in wherein, the rest may be inferred, after next clock pulse starts, the first bit of controlling data sequence input d_in can be stored in trigger 512, the second bit of controlling data sequence input d_in can be stored in trigger 510, and the 3rd bit of controlling data sequence input d_in can be stored in trigger 508.In addition, now control signal hold can be upgraded to 1 to keep the store results trigger 508 ~ 512 from 0, until need to write new control data sequence input d_in next time.The framework of controller 312 and bit number at this only as example explanation, be not restrictive condition of the present invention, bit number can decide according to each number of scanning time pulse domain, and about the design of framework, such as any practice that can reach similar functions, all belongs to the scope that the present invention is contained.
In sum, by adopting scanning clock pulse generator proposed by the invention and scanning clock pulse generation methods, can be with producing multiple inner scanning clock pulses of organizing outs of phase by an external scan clock pulse of a chip exterior input more, reduce chip and cause the occupied situation of stitch because needing multiple scanning clock pulse inputs under scan testing mode, the inner scanning clock pulse that while scanning clock pulse generator of the present invention can produce many group outs of phase also can reach the object that reduces moment measured power.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the present patent application Patent right requirement scope change and modify, and all should belong to covering scope of the present invention.
Claims (14)
1. a scanning clock pulse generator, in order to provide the multiple element under tests of test required multiple chip interscan clock pulses, this scanning clock pulse generator includes:
One receiving circuit, is used for receiving a chip and scans clock pulse outward; And
One clock pulse treatment circuit, is coupled to this receiving circuit, is used for scanning clock pulse outward according to this received chip and produces the plurality of chip interscan clock pulse;
Wherein the clock pulse edge of the plurality of chip interscan clock pulse staggers each other, and this scanning clock pulse generator and the plurality of element under test are arranged in same chip.
2. scanning clock pulse generator as claimed in claim 1, wherein this clock pulse treatment circuit includes:
Multiple delay circuits, scan clock pulse outward in order to this chip that postpones respectively to receive, and produce the plurality of chip interscan clock pulse.
3. scanning clock pulse generator as claimed in claim 2, wherein this clock pulse treatment circuit separately includes:
One controller, is coupled to the plurality of delay circuit, in order to adjust a retardation of each delay circuit.
4. scanning clock pulse generator as claimed in claim 1, wherein this clock pulse treatment circuit includes:
One delay circuit, scans clock pulse outward in order to this chip that postpones to receive, and wherein this delay circuit includes the delay element of multiple serial connections, in order to produce respectively the plurality of chip interscan clock pulse.
5. scanning clock pulse generator as claimed in claim 4, wherein this clock pulse treatment circuit separately includes:
One controller, is coupled to the plurality of delay element, in order to adjust a retardation of each delay element.
6. scanning clock pulse generator as claimed in claim 4, wherein this clock pulse treatment circuit separately includes:
One clock pulse commutation circuit, is used for switching the pairing connected mode between the plurality of chip interscan clock pulse and the plurality of element under test.
7. scanning clock pulse generator as claimed in claim 6, wherein this clock pulse commutation circuit comprises:
One controller, is used for producing a control signal; And
One demoder, is coupled to this controller and the plurality of delay element being connected in series, and adjusts the pairing connected mode between the plurality of chip interscan clock pulse and the plurality of element under test in order to this control signal of decoding.
8. scanning clock pulse generator as claimed in claim 7, wherein this controller receives multiple control bits, and produces this control signal according to the plurality of control bit; And the plurality of control bit is inputted this controller in the mode of sequence transmission.
9. in order to a scanning clock pulse generation methods for the required multiple chip interscan clock pulses of the multiple element under tests of test to be provided, include:
Receive a chip and scan clock pulse outward; And
Scan clock pulse outward according to this received chip and produce the plurality of chip interscan clock pulse;
Wherein the clock pulse edge of the plurality of chip interscan clock pulse staggers each other.
10. scanning clock pulse generation methods as claimed in claim 9, wherein scans according to this received chip the step that clock pulse produces the plurality of chip interscan clock pulse outward and includes:
This chip that individually postpones to be received in the mode of parallel processing scans clock pulse outward, to produce respectively the plurality of chip interscan clock pulse.
11. scanning clock pulse generation methods as claimed in claim 9, wherein scan according to this received chip the step that clock pulse produces the plurality of chip interscan clock pulse outward and include:
This chip that postpones in order to be received in serial connection mode scans clock pulse outward, to produce respectively the plurality of chip interscan clock pulse.
12. scanning clock pulse generation methods as claimed in claim 11, wherein scan according to this received chip the step that clock pulse produces the plurality of chip interscan clock pulse outward and separately include:
Switch the pairing connected mode between the plurality of chip interscan clock pulse and the plurality of element under test.
13. scanning clock pulse generation methods as claimed in claim 12, the step of wherein switching the pairing connected mode between the plurality of chip interscan clock pulse and the plurality of element under test includes:
Produce a control signal; And
This control signal of decoding is adjusted the pairing connected mode between the plurality of chip interscan clock pulse and the plurality of element under test.
14. scanning clock pulse generation methods as claimed in claim 13, the step that wherein produces this control signal comprises:
Receive and inputted multiple control bits in the mode of sequence transmission; And
Produce this control signal according to the plurality of control bit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210447504.9A CN103809104B (en) | 2012-11-09 | 2012-11-09 | Scanning clock pulse generator and scanning clock pulse generation methods |
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|---|---|---|---|
| CN201210447504.9A CN103809104B (en) | 2012-11-09 | 2012-11-09 | Scanning clock pulse generator and scanning clock pulse generation methods |
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| CN103809104A true CN103809104A (en) | 2014-05-21 |
| CN103809104B CN103809104B (en) | 2017-03-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106896317A (en) * | 2015-12-21 | 2017-06-27 | 瑞昱半导体股份有限公司 | By circuit misarrangement method and circuit debuggers performed by the scan chain of sweep test |
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| CN103809104B (en) | 2017-03-01 |
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