CN103782387A - 单片集成有源缓冲器 - Google Patents

单片集成有源缓冲器 Download PDF

Info

Publication number
CN103782387A
CN103782387A CN201280043011.7A CN201280043011A CN103782387A CN 103782387 A CN103782387 A CN 103782387A CN 201280043011 A CN201280043011 A CN 201280043011A CN 103782387 A CN103782387 A CN 103782387A
Authority
CN
China
Prior art keywords
buffer
drain
drift region
capacitor
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201280043011.7A
Other languages
English (en)
Other versions
CN103782387B (zh
Inventor
C·B·科措
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN103782387A publication Critical patent/CN103782387A/zh
Application granted granted Critical
Publication of CN103782387B publication Critical patent/CN103782387B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H01L27/0733—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H01L28/24—Resistors with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种包含具有集成缓冲器的延伸漏极MOS晶体管(106)的半导体器件(100)，该集成缓冲器通过如下步骤形成：形成MOS晶体管的漏极漂移区(108)；形成包括延伸漏极(108)上方的电容介电层(122)和电容板(124)的缓冲电容器；以及在MOS晶体管的栅极(114)上方形成缓冲电阻器(136)，以便该电阻器串联连接在MOS晶体管的电容板和源极(118)之间。

Description

单片集成有源缓冲器
技术领域
本发明涉及包括延伸漏极金属氧化物半导体(MOS)晶体管的半导体器件。
背景技术
半导体器件可以是产生不期望的电压偏移的电路的一部分或包含该电路，例如接收输入DC电压并且生成低于输入电压的输出DC电压的降压转换器电路。半导体器件可以包括延伸漏极金属氧化物半导体(MOS)晶体管，其中在电路操作期间在导通状态和关断状态之间的切换MOS晶体管可能在漏极节点处导致不期望的电压振荡(通常称为鸣震(ring))。将抑制鸣震的缓冲器添加到半导体器件可能是可取的。根据需要的性能在半导体器件中集成缓冲器而不显著增加制造成本和半导体器件复杂性可能是有待解决的。
发明内容
具有集成缓冲器的包含延伸漏极金属氧化物半导体(MOS)晶体管的半导体器件可以通过如下工艺形成：在MOS晶体管的延伸漏极中形成漏极漂移区；以及在延伸漏极上方形成包括电容介电层和电容板的缓冲电容器。缓冲电阻器形成在MOS晶体管的栅极上方，并且串联在MOS晶体管的电容板和源极之间。缓冲电阻器和缓冲电容器形成MOS晶体管的集成缓冲器。电阻可与半导体器件的其它元件同时形成。
附图说明
图1A-1C是示出根据示例实施例的半导体器件制造中的阶段的透视横截面图，该半导体器件包括具有缓冲器的延伸漏极MOS晶体管。
图2A-2C是示出根据改进实施例的半导体器件制造中的阶段的透视横截面图，该半导体器件包括具有缓冲器的延伸漏极MOS晶体管。
图3A-3C是示出根据另一改进实施例的半导体器件制造中的阶段的透视横截面图，该半导体器件包括具有缓冲器的延伸漏极MOS晶体管。
图4A和4B是示出根据另一改进实施例的半导体器件制造中的阶段的透视横截面图，该半导体器件包括具有缓冲器的延伸漏极MOS晶体管。
具体实施方式
包含延伸漏极金属氧化物半导体(MOS)晶体管的半导体器件可以被形成为具有集成到MOS晶体管的集成缓冲器。该半导体器件可以通过包括如下步骤的工艺而形成：在MOS晶体管的延伸漏极中形成漏极漂移区。通过在延伸漏极上方形成电容介电层和电容板，从而在漏极漂移区上方形成缓冲电容器。缓冲电阻器形成在MOS晶体管的栅极上方，并且串联在电容板和MOS晶体管的源极之间。缓冲电阻器和缓冲电容器形成MOS晶体管的集成缓冲器。电阻器可以与半导体器件的其它元件同时形成。电阻器可以与电容板同时形成。
半导体器件可以是包括具有集成缓冲器的延伸漏极MOS晶体管的分立功率器件。可替换地，半导体器件可以是集成电路，该集成电路除了具有集成缓冲器的延伸漏极MOS晶体管之外还包括其它电路例如感测电路和/或控制电路。
为避免重复，将描述n沟道延伸漏极MOS晶体管的形成。然而，应当理解，通过掺杂剂极性和导电类型中的适当变化，相同的描述还适用于形成p沟道延伸漏极MOS晶体管。
图1A-1C示出根据示例实施例的半导体器件制造中的阶段，该半导体器件包括具有缓冲器的延伸漏极MOS晶体管。
参考图1A，半导体器件100形成在半导体衬底102之中和之上，半导体衬底102可以是单晶硅晶片、绝缘体上硅(SOI)晶片、具有不同晶体取向的区域的混合取向技术(HOT)晶片或者是适用于加工半导体器件100的其它材料。在衬底102顶表面处的半导体材料是p型材料。可以在衬底102顶表面处形成场氧化物104。场氧化物104可包括厚度在250到600纳米之间的二氧化硅，并且可以通过浅沟槽隔离(STI)或局部硅氧化(LOCOS)工艺而成形。在STI工艺中，可通过高密度等离子体(HDP)或高纵横比工艺(HARP)沉积二氧化硅。
半导体器件100包含延伸漏极MOS晶体管106。MOS晶体管106具有延伸到衬底102顶表面的n型漏极漂移区108。漏极漂移区108可以通过例如将第一组n型掺杂剂(例如，磷和砷以及可能的锑)以1·1011到1·1013原子/cm2的剂量离子注入到漂移区注入掩模(例如光刻胶图案)所暴露的区域而形成。随后退火工艺激活第一组n型掺杂剂的至少一部分，以便形成漏极漂移区108。漏极漂移区108在衬底102中可延伸到350到1000纳米之间的深度。漏极漂移区108可与半导体器件100的其它组件例如p沟道MOS晶体管的n型阱(未示出)同时形成。
MOS晶体管106进一步包括邻接漏极漂移区108的衬底102中的p型体区110。体区110可以通过例如将一组p型掺杂剂(例如，硼以及可能的镓和/或铟)以1·1011到1·1014原子/cm2的剂量离子注入到体区注入掩模(例如光刻胶图案)所暴露的区域而形成。随后退火工艺激活p型掺杂剂的至少一部分，以便形成体区110。体区110在衬底102中可延伸到300到1000纳米之间的深度。体区110可与半导体器件100的其它组件例如n沟道MOS晶体管的p型阱(未示出)同时形成。激活p型掺杂剂的退火工艺可与激活在漏极漂移区108中的第一组n型掺杂剂的退火工艺同时执行。
在衬底102的上方形成MOS晶体管106的栅极介电层112，栅极介电层112与体区110的一部分和漏极漂移区108的一部分重叠。栅极介电层112可以是二氧化硅、氮氧化硅、氧化铝、氮氧化铝、氧化铪、硅酸铪、氮氧化铪硅、氧化锆、硅酸锆、氮氧化硅锆、前述材料的组合或其它绝缘材料中的一层或多层。由于以50C和800C之间的温度暴露含氮等离子体或含氮氛围气体，因此栅极介电层112可以包括氮。栅极介电层112可由多种栅极介电质形成工艺中的任何一种形成，例如热氧化、氧化层的等离子体氮化和/或通过原子层沉积(ALD)进行的介电材料沉积。栅极介电层112的厚度可以在例如10纳米和80纳米之间。
在栅极介电层112上形成MOS晶体管106的栅极114，栅极114与体区110的一部分和漏极漂移区108的一部分重叠。栅极114可以包括例如多晶体硅(通常称为多晶硅)、金属硅化物(例如硅化钨、硅化钛、硅化钴和/或硅化镍)和/或金属(例如铝、钨和/或氮化钛)的一层或更多层。
可以在栅极114侧表面上形成可选的栅极侧壁116，例如，通过在栅极114顶表面和侧表面以及衬底102顶表面上沉积氮化硅和/或二氧化硅的一个或多个共形层，接着通过各向异性蚀刻方法例如反应性离子蚀刻(RIE)从栅极114顶表面和衬底102顶表面移除共形层材料，将共形层材料留在栅极114侧表面上以便形成栅极侧壁116。
MOS晶体管106还包括n型源极区118和可能的可选n型漏极接触区120。源极区118形成在衬底102中，与栅极114相邻，与漏极漂移区108相对。漏极接触区120形成在衬底102中，接触漏极漂移区108，与栅极114相对。源极区118和漏极接触区120可以通过例如将第二组n型掺杂剂(例如磷和砷以及可能的锑)以3·1014和1·1016原子/cm2之间的总剂量离子注入到源极/漏极注入掩模(例如光刻胶图案)所暴露的区域而形成。随后源极/漏极退火工艺激活第二组n型掺杂剂的一部分，以便形成源极区118和漏极接触区120。源极区118和漏极接触区120可从衬底102顶表面延伸到100纳米和500纳米之间的深度。源极区118和漏极接触区120可与半导体器件100的其它组件例如其它n沟道MOS晶体管的源极/漏极区(未示出)同时形成。可以在源极区118和漏极接触区120上形成例如硅化钛、硅化钴或硅化镍的金属硅化物层(未示出)。
可以将场氧化物104的元件设置在漏极漂移区108中以便将漏极接触区120与漏极接触区120的余留部分横向分离；漏极接触区120在场氧化物104下延伸。
参考图1B，缓冲电容介电层122形成在漏极漂移区108上方，与栅极114相邻。缓冲电容介电层122可以可选地与设置在(如果存在的)漏极漂移区108中的场氧化物元件104重叠。缓冲电容介电层122可以包括例如二氧化硅、氮氧化硅、氧化铝、氮氧化铝、氧化铪、硅酸铪、氮氧化硅铪、氧化锆、硅酸锆、氮氧化硅锆、前述材料的组合或其它绝缘材料中的一层或多层。缓冲电容介电层122的厚度可以在例如10纳米和200纳米之间。缓冲电容介电层122可由多种栅极介电质形成工艺中的任何一种形成，例如热氧化、氧化层的等离子体氮化和/或通过ALD进行的介电材料沉积。
可以将缓冲电容板124形成在缓冲电容介电层122上方以便与漏极漂移区108电隔离。缓冲电容板124可由任何导电材料形成，例如多晶硅、钨、铝、钛、钽、钨钛、金属硅化物、氮化钛、氮化钽和/或氮化钨中的一层或多层。缓冲电容板124的宽度在与栅极114的横向边界垂直的方向中可以例如为1微米和10微米之间。缓冲电容板124可以与半导体器件100中的其它组件例如解耦电容板(未示出)同时形成。缓冲电容板124、缓冲电容介电层122和漏极漂移区108形成缓冲电容器126。
金属前介电(PMD)层形成在半导体器件100的现有顶表面上方。PMD层可以例如是包括PMD衬里、PMD主层和可选的PMD覆盖层的介电层堆叠。PMD衬里可以是由等离子体增强化学气相沉积(PECVD)沉积在半导体器件100的现有顶表面上的厚度为10纳米到100纳米的氮化硅或二氧化硅。PMD主层可以是由HARP工艺形成的二氧化硅层，接着该二氧化硅层的是通过PECVD工艺沉积在PMD衬里的顶表面上的并且有时通过化学机械抛光(CMP)工艺整平的(厚度为100纳米到1000纳米)的二氧化硅层、磷硅玻璃层(PSG)或硼磷硅酸盐玻璃(BPSG)层。可选的PMD覆盖层可以是在PMD主层顶表面上形成的10到100纳米的硬材料，例如氮化硅、碳氮化硅或碳化硅。PMD层没有在图1C中示出，以便更清楚地说明MOS晶体管106的其它元件。
参考图1C，一个或多个缓冲电容器接触件128穿过PMD层形成，以便与缓冲电容板124进行电接触。一个或多个缓冲源极接触件130形成在PMD层中，以便与源极区118进行电接触。缓冲电容接触件128和缓冲源极接触件130可同时形成。
一个或多个晶体管漏极接触件132穿过PMD层形成，以便穿过(如果存在的)漏极接触区120与漏极漂移区108进行电接触。一个或多个晶体管源极接触件134穿过PMD层形成，以便与源极区118进行电接触。晶体管漏极接触件132和晶体管源极接触件134可同时形成，并且可与缓冲电容接触件128和缓冲源极接触件130同时形成。
晶体管漏极接触件132、晶体管源极接触件134、缓冲电容接触件128和缓冲源极接触件130可以通过例如如下步骤形成：使用接触光刻胶图案(未示出)限定PMD顶表面上的接触区；通过使用蚀刻方法例如RIE移除PMD层材料来蚀刻在接触区中的接触孔，以便暴露缓冲电容板124、源极区118和漏极接触区120；以及使用接触衬里(例如钛和氮化钛)以及接触填充金属(例如钨)来填充接触孔，然后通过使用蚀刻和/或CMP方法从PMD层顶表面移除接触填充金属和接触衬里。
缓冲电阻连接件136形成在PMD层上方以便与缓冲电容接触件128和缓冲源极接触件130进行电接触。漏极互连138形成在PMD层上方以便与晶体管漏极接触件132进行电接触，并且源极互连140形成在PMD层上方以便与晶体管源极接触件134进行电接触。在本实施例中，漏极互连138、源极互连140和缓冲电阻连接件136同时形成，并且可与在半导体器件100中的其它互连(未示出)同时形成。
可以使用铝金属化工艺形成漏极互连138、源极互连140和缓冲电阻连接件136，该铝金属化工艺包括：在PMD层上形成厚度为5纳米和15纳米之间的阻挡金属(例如，钛钨或氮化钛)层；在阻挡金属层上形成厚度为100和1500纳米之间的铝互连金属(例如96％铝、2％硅和2％铜的合金)层；以及在铝互连金属层上形成厚度为5和15纳米之间的覆盖金属(例如，钛钨或氮化钛)层。例如光刻胶图案的金属化蚀刻掩模形成在覆盖金属层上方，以便暴露区域中的覆盖金属层从而移除不必要的金属。可以通过例如如下步骤执行金属化蚀刻工艺：RIE步骤，其包括利用氟移除暴露区中的覆盖金属；随后的RIE步骤包括利用氯蚀刻铝互连金属，并且利用氟钝化所蚀刻的铝互连金属的侧表面；随后的另一个RIE步骤包括利用氯蚀刻阻挡金属，以便留下互连元件。
可替换地，可以使用铜镶嵌(damascene)互连工艺形成漏极互连138、源极互连140和缓冲电阻连接件136，该铜镶嵌互连工艺包括在PMD层上方形成层间介电(ILD)层，例如二氧化硅或低k介电层，并且在为铜镶嵌互连所定义的区域中蚀刻通常在100和250纳米的深度之间的ILD层中的沟槽。沟槽暴露漏极互连138、源极互连140和缓冲电阻连接件136的顶表面。例如氮化钽的衬里金属层通常通过物理气相沉积、原子层沉积或化学气相沉积而形成在沟槽的底部和侧部上。铜的籽晶层通常通过溅射法形成在衬里金属上。沟槽随后通常通过电镀来填充铜。铜和衬里金属通过CMP和蚀刻工艺从ILD层的顶表面中被移除，将铜镶嵌互连留在ILD层中。
在本实施例中，缓冲电容接触件128、缓冲电阻连接件136和缓冲源极接触件130形成缓冲电阻器142，该缓冲电阻器串联连接在缓冲电容板124和源极区118之间。一个或多个电阻孔144可形成在缓冲电阻器连接件136中从而增加缓冲电阻器142的电阻。可以选择缓冲电容接触件128的总数量和/或缓冲源极接触件130的总数量以便提供缓冲电阻器142的电阻的期望值。缓冲电阻器142的电阻可以例如在0.5欧姆和20欧姆之间。缓冲电阻器142和缓冲电容器126形成集成缓冲器146。
图2A-2C示出半导体器件制造中的阶段，该半导体器件包括具有根据改进示例实施例的缓冲器的延伸漏极MOS晶体管。
参考图2A，如参考图1A所描述，半导体器件200形成在半导体衬底202之中和之上。如参考图1A所描述，场氧化物(未示出)可以可选地形成在衬底202的顶表面处。如参考图1A所描述，MOS晶体管204具有延伸到衬底202的顶表面的n型漏极漂移区206。如参考图1A所描述，MOS晶体管204进一步包括在衬底202中的p型体区208，该p型体区208与漏极漂移区206邻接。如参考图1A所描述，在衬底202上方形成的MOS晶体管204的栅极介电层210、栅极212和可选的栅极侧壁214与体区208的一部分和漏极漂移区206的一部分重叠。如参考图1A所描述，MOS晶体管204还包括n型源极区216和可能的可选n型漏极接触区218。
缓冲电容介电层220形成在半导体器件200的现有顶表面上方。缓冲电容介电层220可以由参考图1B所描述的材料形成。在本实施例中，缓冲电容介电层220在漏极漂移区206上并且在栅极212和源极区216上方延伸。
参考图2B，缓冲电阻/电容层222形成在缓冲电容介电层220上，该缓冲电阻/电容层222在漏极漂移区206上方并且在栅极212和源极区216上方延伸。将缓冲电阻/电容层222图案化以便与在半导体器件200中的其它组件(未示出)电隔离。缓冲电阻/电容层222可包括如下中的一层或多层：例如多晶硅的导电性材，例如硅化钨、硅化钛、硅化钴或硅化镍的金属硅化物，例如铝、钨、钛、钽的金属，或者例如钛钨、氮化钛、氮化钽、镍铬、硅铬的金属合金，或者例如金属陶瓷、陶瓷金属材料的薄膜电阻材料。
在漏极漂移区206上方的缓冲电阻/电容层222的一部分形成缓冲电容板224。缓冲电容板224、缓冲电容介电层220和漏极漂移区206形成缓冲电容器226。
在栅极212和源极216上方的缓冲电阻/电容层222的一部分形成缓冲电阻器228。可以选择缓冲电阻/电容层222的厚度以便提供缓冲电阻器228的电阻的期望值。可以在缓冲电阻/电容层222中形成一个或多个电阻孔230中以便增加缓冲电阻器228的电阻。缓冲电阻器228的电阻可以例如在0.5和20欧姆之间。
如参考图1C所描述，PMD层(未示出)形成在半导体器件200的现有顶表面上方。在图2C中没有示出PMD层，以便更清楚地说明MOS晶体管204的其它元件。
参考图2C，一个或多个晶体管漏极接触件232穿过PMD层形成，以便穿过(如果存在的)漏极接触区218与漏极漂移区206进行电接触。一个或多个晶体管源极接触件234穿过PMD层形成，以便与源极区216和缓冲电阻器228进行电接触。晶体管漏极接触件232和晶体管源极接触件234可以如参考图1C所描述而形成。
缓冲电阻器228和缓冲电容器226形成集成缓冲器236。
图3A-3C示出根据另一个改进示例实施例的在半导体器件制造中的阶段，该半导体器件包括具有缓冲器的延伸漏极MOS晶体管。
参考图3A，半导体器件300形成在薄半导体衬底302之中和之上。衬底302可以是单晶硅或例如硅锗的半导体合金。在本实施例中，衬底302的厚度在5和100微米之间。MOS晶体管304包括n型漏极漂移区306，该漏极漂移区306从衬底302的顶表面延伸到衬底302的底表面或延伸到邻近衬底302的底表面。MOS晶体管304可以可选地包括在衬底302底表面处并且接触漏极漂移区306的n型漏极接触区308。通过用n型掺杂剂离子注入衬底302的底表面，并且随后执行退火工艺以激活注入掺杂剂的至少一部分，可以形成漏极接触区308。MOS晶体管304进一步包括衬底302底表面上并且与其进行电连接的漏极接触金属层310。
MOS晶体管304包括在衬底302顶表面处与漏极漂移区306邻接的衬底302中的p型体区312。MOS晶体管304的栅极介电层314和栅极316形成在衬底302上方，栅极介电层314和栅极316与在衬底302顶表面处的体区312的一部分和漏极漂移区306的一部分重叠。MOS晶体管304还包括n型源极区318，该n型源极区318形成在衬底302中，与栅极316相邻，与漏极漂移区306相对，并且通过体区312与漏极漂移区306隔离。
参考图3B，缓冲电容介电层320形成在半导体器件300的现有顶表面上方。缓冲电容介电层320可由参考图1B所描述的材料形成。在本实施例中，缓冲电容介电层320在漏极漂移区306上面并且在栅极316和源极区318上方延伸。
穿过源极区318并且进入体区312的源极沟槽322形成在衬底302中，源极沟槽322与栅极316相邻但横向分离。
参考图3C，在缓冲电容介电层320上形成缓冲电阻/电容层324，其在漏极漂移区306上面并且在栅极316和源极区318上方延伸，并且进入源极沟槽322中，以便与源极区318和体区312进行电接触。将缓冲电阻/电容层324图案化以便与半导体器件300中的其它组件(未示出)电隔离。缓冲电阻/电容层324可由参考图2C所描述的材料形成。
在漏极漂移区306上方的缓冲电阻/电容层324的一部分形成缓冲电容板326。缓冲电容板326、缓冲电容介电层320和漏极漂移区306形成缓冲电容器328。
栅极316上方的缓冲电阻/电容层324的一部分形成缓冲电阻器330。可以选择缓冲电阻/电容层324的厚度以便提供缓冲电阻器330的电阻的期望值。一个或多个电阻孔332可以形成在缓冲电阻/电容层324中，以便增加缓冲电阻器330的电阻。缓冲电阻器330的电阻可以例如处于0.5和20欧姆之间。缓冲电阻器330和缓冲电容器328形成集成缓冲器334。
图4A和4B示出根据另一个改进示例实施例的在半导体器件制造中的阶段，该半导体器件包括具有缓冲器的延伸漏极MOS晶体管。
参考图4A，如参考图1A所描述，半导体器件400形成在半导体衬底402之中和之上。如参考图1A所描述，场氧化物404可以形成在衬底402的顶表面处，例如将MOS晶体管406与半导体器件400中的其它组件(未示出)横向隔离。如参考图1A所描述，MOS晶体管406具有延伸到衬底402的顶表面的n型漏极漂移区408。如参考图1A所描述，MOS晶体管406进一步在包括衬底402中与漏极漂移区408邻接的p型体区410。如参考图1A所描述，与体区410的一部分和漏极漂移区408的一部分重叠的MOS晶体管406的栅极介电层412、栅极414和可选的栅极侧壁416形成在衬底402上方。如参考图1A所描述，MOS晶体管406还包括n型源极区418和可能的可选n型漏极接触区420。如图4A所示，漏极接触区420可以由场氧化物404的附加元件横向隔离。
如参考图1B所描述，缓冲电容介电层422形成在漏极漂移区408上方，与栅极414相邻。缓冲电容介电层422可以可选地与在(如果存在的)漏极漂移区408中设置的场氧化物元件404重叠。如参考图1B所描述，缓冲电容板424形成在缓冲电容介电层422上方，以便与漏极漂移区408电隔离。缓冲电容板424、缓冲电容介电层422和漏极漂移区408形成缓冲电容器426。
如参考图1C所描述，PMD层(未示出)形成在半导体器件400的现有顶表面上方。未在图4B中示出PMD层以便更清楚地说明MOS晶体管406的其他元件。如参考图1C所描述，一个或多个缓冲电容接触件428(例如图4A中所示的连续缓冲电容接触件428)通过PMD层形成，以便与缓冲电容板424进行电接触。穿过PMD层形成一个或多个晶体管漏极接触件430(例如连续晶体管漏极接触430)，以便穿过(如果存在的)漏极接触区420与漏极漂移区408进行电接触。穿过PMD层形成一个或多个晶体管源极接触件432(例如连续晶体管源极接触432)，以便与源极区418进行电接触。晶体管漏极接触件430、晶体管源极接触件432和缓冲电容接触件428可以如参考图1C所描述的使用用于连续接触的接触沟槽而形成。
缓冲电阻器434形成在PMD层上方，以便与缓冲电容接触件428和晶体管源极接触件432进行电接触。将缓冲电阻器434被图案化以便与在半导体器件400中的其它组件(未示出)电隔离。缓冲电阻器434的一部分在图4A中移除从而示出晶体管源极接触件432。缓冲电阻器434可以包括如下的一层或多层：例如多晶硅的导电性材料，例如硅化钨、硅化钛、硅化钴或硅化镍的金属硅化物，例如铝、钨、钛、钽的金属，或者例如钛钨、氮化钛、氮化钽、镍铬、硅铬的金属合金，或者例如金属陶瓷的薄膜电阻材料。一个或多个电阻孔436可形成在缓冲电阻器434中，以便增加缓冲电阻器434的电阻。缓冲电阻器434的电阻可以例如处于0.5和20欧姆之间。缓冲电阻器434和缓冲电容器426形成集成缓冲器438。
参考图4B，漏极互连440形成在PMD层上以便与晶体管漏极接触件430进行电接触。源极互连442形成在缓冲电阻器434上，以便穿过缓冲电阻器434与晶体管源极接触件432进行电接触。如参考图1C所描述，漏极互连440和源极互连442可由铝金属化工艺或铜镶嵌金属化工艺形成。
本发明涉及领域的技术人员将理解可以对所描述的实施例进行修改，并且在本发明要求保护的权利要求范围内，许多其他实施例是可能的。

Claims (10)

1.一种半导体器件，其包括：
半导体衬底；
延伸漏极金属氧化物半导体晶体管即延伸漏极MOS晶体管，其包括：
漏极漂移区，其设置在所述衬底中，所述漏极漂移区具有第一导电类型；
体区，其设置在所述衬底中，以便所述体区邻接在所述衬底的顶表面处的所述漏极漂移区，所述体区具有与所述第一导电类型相反的第二导电类型；
栅极，其设置在所述衬底上方，所述栅极与所述漏极漂移区的一部分和所述体区的一部分重叠；以及
源极区，其设置在所述衬底中，与所述栅极相邻并且与所述漏极漂移区相对，所述源极区具有所述第一导电类型；以及
集成缓冲器，其包括：
缓冲电容器，所述缓冲电容器包括所述漏极漂移区，设置在所述漏极漂移区上方的缓冲介电层，以及设置在所述介电层上方的缓冲电容板；以及
缓冲电阻器，其设置在所述栅极上方，所述缓冲电阻器电耦合到所述源极区并且电耦合到所述缓冲电容板。
2.根据权利要求1所述的器件，其中：
所述缓冲介电层的厚度处于10和200纳米之间；以及
所述缓冲电阻器包括：
至少一个缓冲电容接触件，其设置在金属前介电层即PMD层中，所述缓冲电容接触件设置在并且电连接到所述缓冲电容板上；
至少一个缓冲源极接触件，其设置在所述PMD层中，所述缓冲源极接触件设置在并且电连接到所述源极区上；以及
缓冲电阻连接件，其设置在所述PMD层上，所述缓冲电阻连接件与所述缓冲电容接触件以及所述缓冲源极接触件进行电接触。
3.根据权利要求1所述的器件，其中所述缓冲电阻器包括穿过所述缓冲电阻器设置的至少一个电阻孔。
4.根据权利要求1所述的器件，其中：
所述缓冲电容介电层的厚度在10和200纳米之间；
所述缓冲电容介电层进一步设置在所述栅极上方；
所述缓冲电容板是设置在所述漏极漂移区上方的缓冲电阻/电容层的一部分，所述缓冲电阻/电容层设置在所述缓冲电容介电层上，以便所述缓冲电阻/电容层在所述漏极漂移区上面、所述栅极上方和所述源极区上方延伸；
所述缓冲电阻器是设置在所述栅极和所述源极区上方的所述缓冲电阻/电容层的一部分；以及
所述缓冲电阻/电容层通过至少一个晶体管源极接触件而电耦合到所述源极区。
5.根据权利要求4所述的器件，其中所述缓冲电阻/电容层包括穿过所述缓冲电阻/电容层设置的至少一个电阻孔。
6.根据权利要求1所述的器件，其中：
所述漏极漂移区从所述衬底的顶表面向所述衬底的大约5和100微米深度处延伸；
所述MOS晶体管包括设置在所述衬底的所述底表面处的漏极接触区，所述漏极接触区接触所述漏极漂移区，以便所述漏极接触区具有所述第一导电类型；
所述缓冲电容介电层的厚度在10和200纳米之间；
所述缓冲电容介电层进一步设置在所述栅极上方；
所述衬底包括源极沟槽，所述源极沟槽设置穿过所述源极区并且进入所述体区中，与所述栅极相邻但横向分离；
所述缓冲电容板是设置在所述漏极漂移区上方的缓冲电阻/电容层的一部分，所述缓冲电阻/电容层设置在所述缓冲电容介电层上，以便所述缓冲电阻/电容层在所述漏极漂移区上面、所述栅极上方、所述源极区上方以及所述源极沟槽中延伸，以便与所述源极区和所述体区进行电接触；以及
所述缓冲电阻器是设置在所述栅极和所述源极区上方的所述缓冲电阻/电容层的一部分。
7.根据权利要求6所述的器件，其中所述缓冲电阻/电容层包括穿过所述缓冲电阻/电容层设置的至少一个电阻孔。
8.根据权利要求1所述的器件，其中：
所述缓冲电容介电层的厚度为10和200纳米之间；
所述缓冲电阻器设置在金属前介电层即PMD层上方；
所述缓冲电阻器包括至少一层选自包括多晶硅、硅化钨、硅化钛、硅化钴、硅化镍、铝、钨、钛、钽、钛钨、氮化钛、氮化钽、镍铬、硅铬和金属陶瓷的组合中的材料；
所述缓冲电阻器通过至少一个缓冲电容接触件而电连接到所述缓冲电容板，所述缓冲电容接触件设置在所述缓冲电容板上的所述PMD层中；
所述缓冲电阻器通过至少一个晶体管源极接触件而电连接到所述源极区，所述晶体管源极接触件设置在所述缓冲电容板上的所述PMD层中；以及
所述半导体器件包括设置在所述缓冲电阻器上的源极互连，以便穿过所述缓冲电阻器与所述晶体管源极接触件进行电接触。
9.根据权利要求8所述的器件，其中所述缓冲电阻器包括穿过所述缓冲电阻器设置的至少一个电阻孔。
10.一种形成半导体器件的方法，其包括以下步骤：
提供半导体衬底；
通过包括以下步骤的工艺形成延伸漏极金属氧化物半导体晶体管，即延伸漏极MOS晶体管：
在所述衬底中形成漏极漂移区，所述漏极漂移区具有第一导电类型；
在所述衬底中形成体区，以便所述体区邻接所述衬底的顶表面处的所述漏极漂移区，所述体区具有与所述第一导电类型相反的第二导电类型；
在所述衬底上方形成栅极，以便所述栅极与所述漏极漂移区的一部分和所述体区的一部分重叠；以及
在所述衬底中与所述栅极相邻且与所述漏极漂移区相对地形成源极区，所述源极区具有所述第一导电类型；以及
通过包括以下步骤的工艺形成集成缓冲器：
通过包括以下步骤的工艺形成缓冲电容器：
在所述漏极漂移区上方形成缓冲介电层；以及
在所述缓冲介电层上方形成缓冲电容板；
以及
在所述栅极上方形成缓冲电阻器，所述缓冲电阻器电耦合到所述源极区和所述缓冲电容板。
CN201280043011.7A 2011-07-05 2012-07-05 单片集成有源缓冲器 Active CN103782387B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161504624P 2011-07-05 2011-07-05
US61/504,624 2011-07-05
US13/540,813 US8796745B2 (en) 2011-07-05 2012-07-03 Monolithically integrated active snubber
US13/540,813 2012-07-03
PCT/US2012/045554 WO2013006699A2 (en) 2011-07-05 2012-07-05 Monolithically integrated active snubber

Publications (2)

Publication Number Publication Date
CN103782387A true CN103782387A (zh) 2014-05-07
CN103782387B CN103782387B (zh) 2017-06-06

Family

ID=47437691

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280043011.7A Active CN103782387B (zh) 2011-07-05 2012-07-05 单片集成有源缓冲器

Country Status (4)

Country Link
US (2) US8796745B2 (zh)
JP (1) JP6101688B2 (zh)
CN (1) CN103782387B (zh)
WO (1) WO2013006699A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109755240A (zh) * 2017-11-08 2019-05-14 德州仪器公司 在集成电路电阻器中实现更高电流密度的结构

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9362398B2 (en) * 2010-10-26 2016-06-07 Texas Instruments Incorporated Low resistance LDMOS with reduced gate charge
JP5616823B2 (ja) * 2011-03-08 2014-10-29 セイコーインスツル株式会社 半導体装置およびその製造方法
US8859386B2 (en) * 2012-06-08 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and methods of forming resistors
US9230957B2 (en) 2013-03-11 2016-01-05 Alpha And Omega Semiconductor Incorporated Integrated snubber in a single poly MOSFET
US8890223B1 (en) * 2013-08-06 2014-11-18 Texas Instruments Incorporated High voltage hybrid polymeric-ceramic dielectric capacitor
US9461037B2 (en) * 2014-02-06 2016-10-04 Peregrine Semiconductor Corporation Reduced generation of second harmonics of FETs
US9590057B2 (en) * 2014-04-02 2017-03-07 International Business Machines Corporation Reduced parasitic capacitance with slotted contact
US9373712B2 (en) 2014-09-29 2016-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor and method of manufacturing the same
US9633996B1 (en) 2016-03-25 2017-04-25 Qualcomm Incorporated High density area efficient thin-oxide decoupling capacitor using conductive gate resistor
JP6783708B2 (ja) * 2017-06-15 2020-11-11 ルネサスエレクトロニクス株式会社 半導体装置
JP7117260B2 (ja) * 2019-03-18 2022-08-12 ルネサスエレクトロニクス株式会社 半導体装置とその製造方法
US20220278021A1 (en) * 2019-07-31 2022-09-01 Tripent Power Llc Aluminum nitride multilayer power module interposer and method
US11011510B2 (en) 2019-10-04 2021-05-18 Texas Instruments Incorporated Breakdown uniformity for ESD protection device
US11049853B2 (en) 2019-10-04 2021-06-29 Texas Instruments Incorporated ESD protection device with breakdown voltage stabilization
US11876118B2 (en) * 2020-02-14 2024-01-16 Vanguard International Semiconductor Corporation Semiconductor structure with gate metal layer
JP7401416B2 (ja) 2020-09-11 2023-12-19 株式会社東芝 半導体装置
JP6999776B2 (ja) * 2020-10-21 2022-01-19 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
US11664436B2 (en) * 2021-03-01 2023-05-30 Wolfspeed, Inc. Semiconductor devices having gate resistors with low variation in resistance values
US12034033B2 (en) * 2022-01-25 2024-07-09 Ge Aviation Systems Llc Semiconductor device package and method of forming

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030089947A1 (en) * 2001-11-14 2003-05-15 Yusuke Kawaguchi Power MOSFET device
US20070034942A1 (en) * 2005-08-12 2007-02-15 Shuming Xu Power LDMOS transistor
EP1845620A2 (de) * 2006-04-13 2007-10-17 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Integriertes Beschaltungsbauelement auf Halbleiterbasis zur Shaltenlastung, Spannungsbegrenzung bzw. Schwingungsdämpfung
JP2008085117A (ja) * 2006-09-28 2008-04-10 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
CN101630681A (zh) * 2008-06-30 2010-01-20 飞兆半导体公司 具有单片集成的rc缓冲器的功率器件
CN101931005A (zh) * 2009-06-24 2010-12-29 瑞萨电子株式会社 半导体装置及其制造方法和使用它的电源装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137256A (ja) * 1982-02-10 1983-08-15 Hitachi Ltd 絶縁ゲ−ト半導体装置
JPH0514156A (ja) * 1991-07-04 1993-01-22 Toyota Autom Loom Works Ltd 半導体集積回路装置
KR100289049B1 (ko) * 1997-12-17 2001-10-24 정선종 이중필드판구조를갖는전력소자
JP2003203923A (ja) * 2002-01-10 2003-07-18 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2004221344A (ja) * 2003-01-15 2004-08-05 Renesas Technology Corp 半導体装置およびその製造方法
US7382030B1 (en) * 2006-07-25 2008-06-03 Rf Micro Devices, Inc. Integrated metal shield for a field effect transistor
JP4602465B2 (ja) * 2008-12-04 2010-12-22 株式会社東芝 半導体装置
JP5577607B2 (ja) 2009-03-05 2014-08-27 日産自動車株式会社 半導体装置及び半導体装置の製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030089947A1 (en) * 2001-11-14 2003-05-15 Yusuke Kawaguchi Power MOSFET device
US20070034942A1 (en) * 2005-08-12 2007-02-15 Shuming Xu Power LDMOS transistor
EP1845620A2 (de) * 2006-04-13 2007-10-17 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Integriertes Beschaltungsbauelement auf Halbleiterbasis zur Shaltenlastung, Spannungsbegrenzung bzw. Schwingungsdämpfung
EP1845620A3 (de) * 2006-04-13 2008-06-18 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Integriertes Beschaltungsbauelement auf Halbleiterbasis zur Shaltenlastung, Spannungsbegrenzung bzw. Schwingungsdämpfung
JP2008085117A (ja) * 2006-09-28 2008-04-10 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
CN101630681A (zh) * 2008-06-30 2010-01-20 飞兆半导体公司 具有单片集成的rc缓冲器的功率器件
CN101931005A (zh) * 2009-06-24 2010-12-29 瑞萨电子株式会社 半导体装置及其制造方法和使用它的电源装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109755240A (zh) * 2017-11-08 2019-05-14 德州仪器公司 在集成电路电阻器中实现更高电流密度的结构
CN109755240B (zh) * 2017-11-08 2024-04-19 德州仪器公司 在集成电路电阻器中实现更高电流密度的结构

Also Published As

Publication number Publication date
US9385216B2 (en) 2016-07-05
US8796745B2 (en) 2014-08-05
US20130009225A1 (en) 2013-01-10
JP2014523649A (ja) 2014-09-11
WO2013006699A3 (en) 2013-03-21
JP6101688B2 (ja) 2017-03-22
WO2013006699A2 (en) 2013-01-10
US20140308787A1 (en) 2014-10-16
CN103782387B (zh) 2017-06-06

Similar Documents

Publication Publication Date Title
CN103782387A (zh) 单片集成有源缓冲器
TWI738381B (zh) 具有背面源極接觸的立體記憶體元件
KR102670209B1 (ko) 3차원 메모리 디바이스들을 형성하기 위한 방법들
JP5316954B2 (ja) ダイレクトトレンチポリシリコンコンタクトを備える横型トレンチｍｏｓｆｅｔ
US10916468B2 (en) Semiconductor device with buried local interconnects
CN113506809A (zh) 用于形成具有背面源极触点的三维存储器件的方法
CN100524755C (zh) 微电子结构和制造微电子结构的方法
US9941276B2 (en) Method of producing a semiconductor component arrangement comprising a trench transistor
US8501561B2 (en) Method for producing a semiconductor component arrangement comprising a trench transistor
CN102891148A (zh) 用于单栅极非易失性存储器件的结构和方法
CN104319288B (zh) 包括电容器结构的电子设备及其形成工艺
CN1280903C (zh) 具有伪结构的半导体器件
TW200941707A (en) Semiconductor device
TW201140835A (en) Electronic device including a buried insulating layer and a vertical conductive structure extending therethrough and a process of forming the same
US10008560B2 (en) Capacitors in integrated circuits and methods of fabrication thereof
KR20170129269A (ko) 본딩된 반도체 구조체의 에칭 스톱 영역 기반의 제작
US8652855B2 (en) Low resistance stacked annular contact
TWI409948B (zh) 製造具有不同高度接觸線之高密集度ｍｏｓｆｅｔ電路的結構與方法
US6239010B1 (en) Method for manually manufacturing capacitor
JP5616720B2 (ja) 半導体装置およびその製造方法
CN101162718A (zh) 半导体装置及其制造方法
JP2023097349A (ja) デバイスおよび半導体デバイスを製造するための方法（密度スケーリングのための背面電源レールおよび配電網）
US10304839B2 (en) Metal strap for DRAM/FinFET combination
TWI773086B (zh) 用於形成立體（３ｄ）記憶體元件的方法
JP2000228445A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant