CN103745745A - Programmable tracking circuit of SA (sense amplifier) of SRAM (static random access memory) - Google Patents
Programmable tracking circuit of SA (sense amplifier) of SRAM (static random access memory) Download PDFInfo
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- CN103745745A CN103745745A CN201310723128.6A CN201310723128A CN103745745A CN 103745745 A CN103745745 A CN 103745745A CN 201310723128 A CN201310723128 A CN 201310723128A CN 103745745 A CN103745745 A CN 103745745A
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Abstract
The invention discloses a programmable tracking circuit of an SA (sense amplifier) of an SRAM (static random access memory). The programmable tracking circuit comprises a word line driving circuit (WLDRIVER), a programmable timing control circuit and a sense amplifier driving circuit (SA Driver), wherein the WLDRIVER is used for driving word line signals WL and DWL; the programmable timing control circuit is controlled by DWL, and is a programmable array DBL (duplicated bit line) discharging circuit mainly comprising NMOSs (N-channel metal oxide semiconductors); the SA Driver is used for controlling the on and off of the SA. According to the programmable tracking circuit, the influence of process variations, voltage and temperature on the on-off time of the SA is avoided.
Description
Technical field
The present invention relates to integrated circuit, be specifically related to a kind of tracking circuit of programmable SRAM sense amplifier.
Background technology
Along with continuous progress and the high performance requirement of system of integrated circuit technology, SOC product of today is increasing for the demand of storer, and in-line memory shared area and power consumption ratio in SOC also increasing year by year.At several years of future, being greater than 90% chip area will be occupied by various memory circuitries.Wherein, SRAM is because of its quick access, high reliability and played the part of very important role with the compatibility of logical circuit in SOC equipment.
When the continuing of integrated circuit technology size reduced to improve the cost of SRAM storer and integrated level, also to SRAM, development has brought challenge.Along with reducing of device size, the process deviation that the stochastic volatility of doping brings is more and more significant on the impact of performance of integrated circuits, and has increased the difficulty of breadboardin.When technique reaches below 100nm, process deviation becomes very important to the impact of circuit.For the consideration to process deviation influence, in the time of general design, can retain relatively large design margin, although this can increase the complicacy of design, increase design cost, if but ignore these, may cause the reduction of circuit performance, even can make circuit function realize.
In addition, because the difference of temperature and operating voltage, the not equal factor of the leakage current that SRAM storer produces, also has a huge impact the stability of SRAM.
SRAM generally can comprise a tracking circuit of controlling sense amplifier SA.This circuit is for when read operation, and the enable signal SAEN that produces sense amplifier SA controls the break-make of sense amplifier SA, sense data.Yet, if sense amplifier open too early, bit line BL and BLB voltage difference are large not, may cause the mistake of read operation; If it is excessively late that sense amplifier is opened, BL and BLB voltage difference are excessive, will cause the excessive of power consumption loss.Because the impact of process deviation, voltage, temperature (PVT), the data reading speed of different storage unit is different.Therefore, in order to guarantee the correctness of reading result, reduce the loss of power consumption, the tracking circuit of sense amplifier SA, should adapt to different PVT, the in good time sense amplifier SA that opens
Traditional storer method for tracing often only adopts one word line or single bit line to follow the trail of circuit, thereby produces trace signals control store data read operation.Like this impact of process deviation is not played to what effect.In order to address this problem, the invention discloses a kind of sense amplifier tracking circuit that can adapt to different process deviation, voltage, temperature.
Summary of the invention
For overcoming deficiency of the prior art, the invention provides a kind of tracking circuit of programmable SRAM sense amplifier.
For realizing above-mentioned technical purpose, reach above-mentioned technique effect, the present invention is achieved through the following technical solutions:
A kind of tracking circuit of programmable SRAM sense amplifier, comprise word line driving circuit WL DRIVER, sequential control circuit Programmable Timing Control able to programme and sense amplifier driving circuit SA Driver, described word line driving circuit WL DRIVER is used for driving word-line signal WL and DWL, described sequential control circuit Programmable Timing Control able to programme is controlled by DWL, the DBL discharge circuit of the programmable array that described sequential control circuit Programmable Timing Control able to programme is mainly comprised of NMOS, described sense amplifier driving circuit SA Driver is for controlling the break-make of sense amplifier.
Further, described sequential control circuit Programmable Timing Control able to programme is just controlled the break-make of NMOS by the voltage of controlling NMOS grid, thereby realize NMOS number and connected mode in controlled discharge path, realize the programmability of time delay, on DBL, be connected with several NMOS, for simulating the storage unit of closing.
Compared with prior art, the present invention has following beneficial effect:
Adopt technical solution of the present invention, solved process deviation, voltage, the impact of temperature on sense amplifier SA make-and-break time.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of instructions, below with preferred embodiment of the present invention and coordinate accompanying drawing to be described in detail as follows.The specific embodiment of the present invention is provided in detail by following examples and accompanying drawing thereof.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, forms the application's a part, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the sense amplifier tracking circuit schematic diagram of the embodiment of the present invention;
Fig. 2 is the embodiment of Programmable Timing Control module in Fig. 1;
Fig. 3 is the application 1 of the embodiment of Programmable Timing Control module in Fig. 2;
Fig. 4 is the application 2 of the embodiment of Programmable Timing Control module in Fig. 2.
Embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the present invention in detail.
Shown in Fig. 1, a kind of tracking circuit of programmable SRAM sense amplifier, comprise word line driving circuit WL DRIVER, sequential control circuit Programmable Timing Control able to programme and sense amplifier driving circuit SA Driver, described word line driving circuit WL DRIVER is used for driving word-line signal WL and DWL, described sequential control circuit Programmable Timing Control able to programme is controlled by DWL, the DBL discharge circuit of the programmable array that described sequential control circuit Programmable Timing Control able to programme is mainly comprised of NMOS, described sense amplifier driving circuit SA Driver is for controlling the break-make of sense amplifier.
Further, described sequential control circuit Programmable Timing Control able to programme is just controlled the break-make of NMOS by the voltage of controlling NMOS grid, thereby realize NMOS number and connected mode in controlled discharge path, realize the programmability of time delay, on DBL, be connected with several NMOS, for simulating the storage unit of closing.
Embodiment:
Fig. 2 is the embodiment of Programmable Timing Control module in Fig. 1.The NMOS array that the nmos pass transistor that the present embodiment is listed as by 5 row 4 forms.Wherein, the nmos pass transistor of the 1st row, it is upper that source electrode is connected on DBL, and grid is connected on DWL.The grid of the nmos pass transistor of the 2nd row to the 5 row is inputted to control by outside.
Fig. 3 is the application 1 in Programmable Timing Control module embodiment in Fig. 2.By the opt01 in Fig. 2, opt02, opt03, opt11, opt12, opt13, opt21, opt22, opt23, opt31, opt32, opt33 is set to 0, and its corresponding NMOS disconnects, and in Fig. 3, does not illustrate; By the opt00 in Fig. 2, opt10, opt20, opt30 is set to 1, and the NMOS conducting that it is corresponding is shown in Figure 3.
Fig. 4 is the application 2 in Programmable Timing Control module embodiment in Fig. 2.By the opt01 in Fig. 2, opt02, opt03, opt11, opt12, opt13, opt21, opt22, opt23 is set to 0, and its corresponding NMOS disconnects, and in Fig. 3, does not illustrate; By the opt00 in Fig. 2, opt10, opt20, opt30, opt31, opt32, opt33 is set to 1, and the NMOS conducting that it is corresponding is shown in Figure 3.
Principle of the present invention:
A programmable sequential control circuit, the array circuit that it is comprised of NMOS, in controlling array, the height of the grid voltage of NMOS is controlled the break-make of NMOS, thereby controls the number of conducting NMOS and the connected mode of conducting NMOS in sequential control circuit, thereby realizes the control of sequential; Sequential control circuit is controlled sense amplifier driving circuit, sends sense amplifier and drives signal SAEN to control the break-make of sense amplifier SA, guarantee read operation accuracy and reduce power consumption.
Below in conjunction with Fig. 2, Fig. 3, Fig. 4 describes the function of the tracking scheme shown in Fig. 1.Simulation word line DBL by preliminary filling to high level; Be connected in source electrode and the grounded-grid of the NMOS on DBL, now NMOS is closed, is used for simulating the storage unit of not selected generation leakage current.Word line driving circuit activated word line WL and DWL, the storage unit being connected with WL is selected, read operation starts, meanwhile, DWL enables Programmable Timing Control circuit, suppose Programmable Timing Control circuit as shown in Figure 3, DBL starts to start electric discharge by the conductive path of Programmable Timing Control module in Fig. 3, when discharging into, DBL to a certain degree will enable sense amplifier driving circuit SA Driver circuit, then, SA Driver circuit sends SA and drives signal SAEN to open SA, reads storage data.Yet, if the Programmable Timing Control module map in Fig. 1 is as shown in 4, because last 4 and NMOS in parallel will accelerate the velocity of discharge in Fig. 4, so the speed of the embodiment sense data of Fig. 4 is faster than the embodiment in Fig. 3.Application for Fig. 2 embodiment Programmable Timing Control is not limited to the form shown in Fig. 3 and Fig. 4.Can be for the impact of different process deviation, voltage, temperature, by optij(i=0,1,2,3; J=0,1,2,3) be configured, select the conducting form of suitable Programmable Timing Control, thereby control the break-make of sense amplifier, realized able to programmeization.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (2)
1. the tracking circuit of a programmable SRAM sense amplifier, comprise word line driving circuit WL DRIVER, sequential control circuit Programmable Timing Control able to programme and sense amplifier driving circuit SA Driver, it is characterized in that, described word line driving circuit WL DRIVER is used for driving word-line signal WL and DWL, described sequential control circuit Programmable Timing Control able to programme is controlled by DWL, the DBL discharge circuit of the programmable array that described sequential control circuit Programmable Timing Control able to programme is mainly comprised of NMOS, described sense amplifier driving circuit SA Driver is for controlling the break-make of sense amplifier.
2. the tracking circuit of programmable SRAM sense amplifier according to claim 1, it is characterized in that, described sequential control circuit Programmable Timing Control able to programme is just controlled the break-make of NMOS by the voltage of controlling NMOS grid, thereby realize NMOS number and connected mode in controlled discharge path, realize the programmability of time delay, on DBL, be connected with several NMOS, for simulating the storage unit of closing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310723128.6A CN103745745A (en) | 2013-12-25 | 2013-12-25 | Programmable tracking circuit of SA (sense amplifier) of SRAM (static random access memory) |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310723128.6A CN103745745A (en) | 2013-12-25 | 2013-12-25 | Programmable tracking circuit of SA (sense amplifier) of SRAM (static random access memory) |
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| CN103745745A true CN103745745A (en) | 2014-04-23 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1523608A (en) * | 2003-01-16 | 2004-08-25 | 松下电器产业株式会社 | Semiconductor memory device |
| CN102664041A (en) * | 2012-05-22 | 2012-09-12 | 安徽大学 | Programmable SRAM (static random Access memory) time sequence control system based on BIST (built-in self-test) control |
| CN202662294U (en) * | 2012-05-22 | 2013-01-09 | 安徽大学 | Programmable SRAM (static random Access memory) time sequence control circuit based on BIST (built-in self-test) control |
| CN102870160A (en) * | 2010-04-09 | 2013-01-09 | 高通股份有限公司 | Programmable tracking circuit for tracking semiconductor memory read current |
| US20130250659A1 (en) * | 2012-03-21 | 2013-09-26 | Atsushi Kawasumi | Semiconductor memory device |
-
2013
- 2013-12-25 CN CN201310723128.6A patent/CN103745745A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1523608A (en) * | 2003-01-16 | 2004-08-25 | 松下电器产业株式会社 | Semiconductor memory device |
| CN102870160A (en) * | 2010-04-09 | 2013-01-09 | 高通股份有限公司 | Programmable tracking circuit for tracking semiconductor memory read current |
| US20130250659A1 (en) * | 2012-03-21 | 2013-09-26 | Atsushi Kawasumi | Semiconductor memory device |
| CN102664041A (en) * | 2012-05-22 | 2012-09-12 | 安徽大学 | Programmable SRAM (static random Access memory) time sequence control system based on BIST (built-in self-test) control |
| CN202662294U (en) * | 2012-05-22 | 2013-01-09 | 安徽大学 | Programmable SRAM (static random Access memory) time sequence control circuit based on BIST (built-in self-test) control |
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