CN103731224B - Device and method for supporting multi-length-variable-cell time slot multiplexing - Google Patents
Device and method for supporting multi-length-variable-cell time slot multiplexing Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/407—Bus networks with decentralised control
- H04L12/417—Bus networks with decentralised control with deterministic access, e.g. token passing
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Abstract
The invention discloses a device and method for supporting multi-length-variable-cell time slot multiplexing. The method includes the steps that input multiple length-variable cells are respectively cached through an input storage module, the cached length-variable cell data are output to a gating network module according to a first sequential control command sent by a control logic module, the gating network module comprising a plurality of parallel multiplexers carries out gating output on the length-variable cell data read out from the input storage module according to a second sequential control command sent by the control logic module, the length-variable cell data coming from the gating network module are cached through an output storage module, and the length-variable cell data after time-slot multiplexing are output according to a third sequential control command sent by the control logic module. According to the device and method, time slot multiplexing of the multiple length-variable cells under any relative relation can be processed in real time, use of the bandwidth of each input port is guaranteed, and the processing flexibility is improved.
Description
Technical field
The present invention relates to communication technical field, in particular to a kind of dress supporting the elongated cell time slot multiplexing of multichannel
Put and method, specifically, it can be applicable to the input interface section of router or switch.
Background technology
In modern communication networks, based on cell（Fixed length grouped data）Exchange and processing mode become more and more general
Time, this is due to being had efficiency of transmission height, processing simple feature as the communicating circuit of primitive using cell, its
In, it is a kind of structure that exchange chip is commonly used based on shared storage, its internal multiple input/output port shares a piece of storage
Space, has the high advantage of memory utilization rate.
Number of patent application is that 200520078701.3 Chinese patent application discloses a kind of multiplexing point of synchronous digital signal
Solution circuit, in this patent formula, the timeslot multiplex of multichannel cell uses and first carries out serioparallel exchange, then is entered by multiplexer
The method of row gating, the method presence has a disadvantage that：
1st, in input and output clock synchronization and in the case of on input link, signal is continuous, the method requires in each input chain
Cell on road reaches the time and offsets one from another, and the cell on each bar link can not reach simultaneously, limits the motility of input.
2nd, in the case that cell length is larger, the circuit scale of multiplexer and time delay can become very big, increased design
Complexity.
In addition, the Chinese patent application that number of patent application is 200910209696.8 discloses a kind of multichannel cell time slot again
Apparatus and method, described device includes inputting memory module, for the cell inputting is entered row cache and exported；Gating net
Network module, for carrying out gating output by the cell from input memory module；Output memory module, for from gating net
The cell of network module enters row cache parallel output cell；And control logic module, for having cell to input to defeated in determination
Enter and send read output signal to input memory module during memory module, and gate output for controlling with predetermined tempo signal, and
For the control output memory module when determining that gating output completes by input data parallel output, in this patent formula,
Although its can receive simultaneously or stochastic inputs cell and by its parallel output, and using multiple multiplexers and memorizer
Module, to substitute single big multiplexer, reduces scale and the circuit design difficulty of multiplexer.
But in the method, it still only supports the process of fixed length cell, then cannot process for elongated cell.Using fixed
The mode of long cell in some data transfers can greatly waste bandwidth, affect efficiency, so, how to provide and a kind of support to become
The method of long cell time slot multiplexing just becomes current industry needs one of key technology point of solution.
Content of the invention
In order to overcome prior art can not process the problem of elongated cell input, the invention provides a kind of support that multichannel becomes
The device and method of long cell time slot multiplexing.
The present invention employs the following technical solutions：
A kind of device supporting the elongated cell time slot multiplexing of multichannel, including：
Input memory module, for being cached respectively to the elongated cell of multichannel inputting, and according to control logic module
The the first sequencing contro order sending exports the elongated cell data caching to gating network module；
Gating network module, it includes multiple parallel multiplexers, for according to control logic module send second when
Sequence control command, the elongated cell data reading from input memory module is carried out gating output；
Output memory module, for entering row cache to the elongated cell data from gating network module, and according to control
The 3rd sequencing contro order that logic module sends, the elongated cell data that timeslot multiplex is completed is exported；
Control logic module, exports the elongated cell data caching to gating network mould for control input memory module
Block；It is further used for controlling gating network module that the elongated cell data reading from input memory module is carried out gating output；
And be further used for controlling output memory module to be exported the elongated cell data that timeslot multiplex completes.
Preferably, described input memory module includes multiple sub-module stored, for the elongated cell of multichannel of caching input；
Wherein,
When there being cell input, described sub-module stored is by non-NULL indication signal set.
Preferably, described output memory module includes multiple parallel memory RAM immediately（Random Access
Memory, random access memory）Or depositor, it is derived from the elongated cell data of gating network module for caching, and according to control
The 3rd sequencing contro order that logic module processed sends, will complete the elongated cell data of timeslot multiplex in RAM or depositor
Exported.
Preferably, described control logic module includes：
Internal control signal generation module, for producing rhythm control signal, and is respectively sent to input storage mould
Block, gating network module and output memory module；
Output control signal generation module, under the rhythm control signal generating for control signal generation module internally,
Non-null states in input memory module are carried out gating output.
Preferably, the control of the rhythm control signal that the multiplexer in gating network module sends in control logic module
Under, the elongated cell data receiving is carried out gating and exports and be sent to output memory module.
A kind of method supporting the elongated cell time slot multiplexing of multichannel, including：
Input memory module is cached respectively to the elongated cell of multichannel of input, and send according to control logic module
First sequencing contro order exports the elongated cell data caching to gating network module；
The second sequencing contro sending according to control logic module including the gating network module of multiple parallel multiplexers
Order, the elongated cell data reading from input memory module is carried out gating output；
Output memory module enters row cache to the elongated cell data from gating network module, and according to control logic mould
The 3rd sequencing contro order that block sends, the elongated cell data that timeslot multiplex is completed is exported.
Preferably, described input memory module includes multiple sub-module stored, for the elongated cell of multichannel of caching input；
Wherein, before the step that execution input memory module is cached respectively to the elongated cell of multichannel of input, methods described is also
Including：
When there being cell input, described sub-module stored is by non-NULL indication signal set.
Preferably, described output memory module includes multiple parallel memory RAM immediately or depositor, for caching
From the elongated cell data of gating network module, and the 3rd sequencing contro order sending according to control logic module, will be
The elongated cell data completing timeslot multiplex in RAM or depositor is exported.
Preferably, described control logic module includes：
Internal control signal generation module, for producing rhythm control signal, and is respectively sent to input storage mould
Block, gating network module and output memory module；
Output control signal generation module, under the rhythm control signal generating for control signal generation module internally,
Non-null states in input memory module are carried out gating output.
Preferably, the described gating network module including multiple parallel multiplexers send according to control logic module the
Two sequencing contro orders, the elongated cell data reading from input memory module is carried out in the step gating output：
Multiplexer in gating network module, under the control of the rhythm control signal that control logic module sends, will receive
To elongated cell data carry out gating and export and be sent to output memory module.
The present invention be can be seen that by the technical scheme of the invention described above and carry out multichannel change long letter using input memory module
Unit caches, jointly completes using gating network module and output memory module the timeslot multiplex of the elongated cell of multichannel, can be real-time
The timeslot multiplex processing the elongated cell of multichannel under Arbitrary Relative relation, it is ensured that the bandwidth usage of each input port, improves
Process motility.
In addition, the present invention is applied to the elongated cell of various length, the depth to storage is only needed on circuit, each
The timeslot multiplex number of times of port cell and multiplexer are modified design, thus improve setting with the quantity of sub-module stored
The motility of meter.
Brief description
Fig. 1 is the apparatus structure schematic diagram of the elongated cell time slot multiplexing of support multichannel in the embodiment of the present invention；
Fig. 2 is the input storage internal structure schematic diagram in the embodiment of the present invention；
Fig. 3 is the gating network internal structure schematic diagram in the embodiment of the present invention；
Fig. 4 is the output storage internal structure schematic diagram in the embodiment of the present invention；
Fig. 5 is the control logic internal structure schematic diagram in the embodiment of the present invention；
Fig. 6 is the data transmission method schematic diagram in the embodiment of the present invention；
Fig. 7 is the data processing method flow chart in the embodiment of the present invention.
The realization of the object of the invention, functional characteristics and excellent effect, below in conjunction with specific embodiment and accompanying drawing do into
The explanation of one step.
Specific embodiment
With specific embodiment, technical scheme of the present invention is described in further detail below in conjunction with the accompanying drawings, so that this
The technical staff in field can be better understood from the present invention and can be practiced, but illustrated embodiment is not as the limit to the present invention
Fixed.
As shown in figure 1, a kind of device supporting the elongated cell time slot multiplexing of multichannel provided in an embodiment of the present invention, including：
Input memory module 101, for being cached respectively to the elongated cell of multichannel inputting, and according to control logic mould
The first sequencing contro order that block 104 sends exports the elongated cell data caching to gating network module 102.
When being embodied as, it includes several FIFO submodules, each port one data storage.In order to each
Input data on link enters row cache, and under certain port polling, by internal data read-out to gating network module
102.
Under preferred implementation, described input memory module 101 includes multiple sub-module stored（For example, FIFO
FIFO submodule）, for the elongated cell of multichannel of caching input；Wherein, when there being cell input, described sub-module stored will be non-
Empty indication signal set.
Gating network module 102, it includes multiple parallel multiplexers, for send according to control logic module 104
Second sequencing contro order, the elongated cell data reading from input memory module 101 is carried out gating output.
When being embodied as, it includes several multiplexers, in order to by the data in the input reading storage, to be transferred to correspondence
Output memory module 103 spatial cache.
Under preferred implementation, the beat control that the multiplexer in gating network module 102 sends in control logic module 104
Under the control of signal processed, the elongated cell data receiving is carried out gating and exports and be sent to output memory module 103.
Output memory module 103, for row cache is entered to the elongated cell data from gating network module 102, and according to
The 3rd sequencing contro order sending according to control logic module 104, the elongated cell data that timeslot multiplex is completed is exported.
When being embodied as, it includes several sub-module stored, can be made up of RAM or depositor.In order to receive gating
The data of corresponding multiplexer input in mixed-media network modules mixed-media 102, and exported being multiplexed the data completing after certain sequential.
Under preferred implementation, described output memory module 103 includes multiple parallel memory RAM immediately or deposits
Device, for caching from gating network module 102 elongated cell data, and the sending according to control logic module 104
Three sequencing contro orders, the elongated cell data completing timeslot multiplex in RAM or depositor is exported.
Control logic module 104, exports the elongated cell data caching to gating for control input memory module 101
Mixed-media network modules mixed-media 102；It is further used for the elongated cell number controlling gating network module 102 will to read from input memory module 101
Export according to carrying out gating；And it is further used for the elongated cell data controlling output memory module 103 to complete timeslot multiplex
Exported.
When being embodied as, in order to provide input memory module 101, gating network module 102, to export memory module 103
Control information.
Under preferred implementation, described control logic module 104 includes：
Internal control signal generation module 501, for producing rhythm control signal, and is respectively sent to input storage
Module 101, gating network module 102 and output memory module 103；
Output control signal generation module 502, the rhythm control letter generating for control signal generation module 501 internally
Under number, the non-null states in input memory module 101 are carried out gating output.
As shown in Fig. 2 being made up of several sub-module stored inside input memory module 101, each sub-module stored
Depth is the length of 1 maximum cell, and input is connected with the input of whole device.Sub-module stored is receiving data
After being inputted, by non-NULL indication signal set.When carrying out data read-out to sub-module stored, control logic module 104 is led to
Cross beat control signal successively the non-NULL indication signal of sub-module stored to be inquired about according to the order of 0 ~ m, non-NULL is indicated
Signal is supplied to control logic module 104.
As shown in figure 3, by several mux inside gating network module 102（Multiplexer, multiplexer）Constitute, each
The input number of mux is identical with the sub-module stored quantity in input memory module 101, and quantity n of mux and parallel output are total
Line k bit or sub-module stored output bus j bit is identical.When being controlled to mux, control logic module 104 passes through section
Clap control signal and start mux successively according to the order of 0 ~ n.Each mux presses the order of 0 ~ m after start-up successively to input signal
Carry out gating output.
As shown in figure 4, output memory module 103 is made up of several RAM or depositor, in the present embodiment, each RAM's
Input is connected with gating network module 102, and the outfan of all RAM binds together, and constitutes the device of cell multiplexing
Output.The number of output memory module 103RAM is identical with output bus kbit/64bit, the input that depth is stored with input
Port number is identical.After the data receiving gating network module 102,0# ~（n-1）#RAM is by control logic module 104 certain
Time after its internal data is exported together, complete timeslot multiplex.Wherein, the control of read access time can basis
This time needing the valid data write time of output to determine needs to export kbit data output time delay output, tool it is also possible to regard
Body design can flexibly be used.
As shown in figure 5, control logic module 104 is generated by internal control signal generation module 501 and output control signal
Module 502 forms.Internal control signal generation module 501 comprises enumerator and some control circuits, for producing rhythm control
Signal, exports input memory module 101, gating network module 102 and output memory module 103, thus realizing to this 3 moulds
Block is controlled.
Internally cadence signal produced by control signal generation module 501 controls output control signal generation module 502
Under, the input control unit non-null states in input memory module 101 are carried out gating output, and generates output control signal.
Device using the elongated cell time slot multiplexing of above-mentioned support multichannel carries out being embodied as of elongated cell time slot multiplexing
Step is as follows：
Step A, input memory module 101 receives the elongated cell of multichannel from input port.
Step B, input memory module 101 in caching row cache is entered to elongated cell data, and be given caching non-NULL refer to
Show.
Step C, control logic module 104 is to input memory module 1010 ~ m（Wherein, m is that input memory module 101 is parallel
The way of caching）Elongated cell data in number caching is polled, if this caching is non-NULL, just reads interior data, reads
The number of slices going out data determines according to the length information of elongated cell, if length information exceedes parallel output bus number k
Bit, then only read k bit data, provide the configured information of first count, remaining data reads in next polling cycle simultaneously,
At most read k bit data, poll reads successively；If it is empty, then do not carry out data read-out.
Step D, the multiplexer within gating network module 102 is according to 0 ~ n（Wherein, n is inside gating network module 102
Multiplexer quantity）Number order open successively, each multiplexer in a circulating manner by 0 ~ No. m cache in data respectively
It is sent to corresponding output sub-module stored.
Step E, the output sub-module stored in output memory module 103 is kept in elongated cell data, is controlling
Under the control of logic module 104 enumerator, cyclically by the data output in 0 ~ n address in all output sub-module stored,
Complete the timeslot multiplex of multiple passage cells.
Adaptably, the embodiment of the present invention additionally provides a kind of method supporting the elongated cell time slot multiplexing of multichannel, including：
S101, input memory module 101 are cached respectively to the elongated cell of multichannel of input, and according to control logic mould
The first sequencing contro order that block 104 sends exports the elongated cell data caching to gating network module 102；
S102, include that the gating network module 102 of multiple parallel multiplexers sends according to control logic module 104 the
Two sequencing contro orders, the elongated cell data reading from input memory module 101 is carried out gating output；
S103, output memory module 103 enter row cache to the elongated cell data from gating network module 102, and according to
The 3rd sequencing contro order sending according to control logic module 104, the elongated cell data that timeslot multiplex is completed is exported.
When being embodied as, described input memory module 101 includes multiple sub-module stored, and the multichannel for caching input becomes
Long cell；Wherein, before the step that execution input memory module 101 is cached respectively to the elongated cell of multichannel of input,
Methods described also includes：
S100, when there being cell input, described sub-module stored is by non-NULL indication signal set.
When being embodied as, the gating network module 102 of the multiple parallel multiplexer of described inclusion is according to control logic module
Second sequencing contro order of 104 transmissions, the elongated cell data reading from input memory module 101 is carried out gating output
In step：Multiplexer in gating network module 102 under the control of the rhythm control signal that control logic module 104 sends,
The elongated cell data receiving is carried out gating export and be sent to output memory module 103.
Described output memory module 103 includes multiple parallel memory RAM immediately or depositor, free for caching
The elongated cell data of open network module 102, and the 3rd sequencing contro order sending according to control logic module 104, will
The elongated cell data completing timeslot multiplex in RAM or depositor is exported.
For the device of the support multichannel elongated cell time slot multiplexing corresponding with methods described, its control logic including
Module 104 includes：
Internal control signal generation module 501, for producing rhythm control signal, and is respectively sent to input storage
Module 101, gating network module 102 and output memory module 103；
Output control signal generation module 502, the rhythm control letter generating for control signal generation module 501 internally
Under number, the non-null states in input memory module 101 are carried out gating output.
The data transmission method of the elongated cell time slot multiplexing device of multichannel provided in an embodiment of the present invention as shown in fig. 6, on
The initial time slot_0 moment after reset, by the data read-out on No. 0 address in input memory module 101#0
Afterwards, store in No. 0 address on ram#0；In the time slot_1 moment, by No. 1 in input memory module 101#0
Two data read-out on the 0th address on address and input memory module 101#1, store No. 0 address on ram#1
And in No. 1 address on ram#0；Each reading data of each input memory module 101 is less than kbit；In time
After slot_m, data will be read in each input memory module 101 in each clock cycle, wherein input memory module
Data in h address in 101#m will store ram#h（h≤n-1）In in m address.
As shown in fig. 7, for the device entering the support elongated cell time slot multiplexing of multichannel provided in an embodiment of the present invention
Elongated cell data, as follows for its handling process：
Step 1, the elongated cell data of the input memory element receives input in input memory module 101.
Step 2, the input memory element of input memory module 101 enters row cache to elongated cell, and waits read output signal.
Step 3, the input memory element of input memory module 101 receives read output signal, and data output is given gating net
Network module 102, wherein, each data reading is less than kbit, carries out 0,1,2 to each kbit data reading ... and marks
Note, is recombinated by subsequent module.
Step 4, under the control of the cadence signal in control logic module 104 for the multiplexer in gating network module 102, will
The signal receiving carries out gating output, is sent to output memory module 103.
Step 5, output memory module 103 receives the data in gating network module 102, row cache of going forward side by side.
Step 6, judges to output time, if reaching, the data in output memory module 103 is carried out defeated
Go out.
Step 7, exports to the elongated cell after the completion of timeslot multiplex.
The foregoing is only the preferred embodiments of the present invention, not thereby limit the scope of the claims of the present invention, every utilization
Equivalent structure or equivalent flow conversion that description of the invention and accompanying drawing content are made, or it is related to be directly or indirectly used in other
Technical field, be included within the scope of the present invention.
Claims (8)
1. a kind of device supporting the elongated cell time slot multiplexing of multichannel is it is characterised in that include：
Input memory module, for being cached respectively to the elongated cell of multichannel inputting, and sends according to control logic module
The first sequencing contro order by cache elongated cell data export to gating network module；
Gating network module, it includes multiple parallel multiplexers, for the second sequential control sending according to control logic module
System order, the elongated cell data reading from input memory module is carried out gating output；
Output memory module, for entering row cache to the elongated cell data from gating network module, and according to control logic
The 3rd sequencing contro order that module sends, the elongated cell data that timeslot multiplex is completed is exported；
Wherein said output memory module includes multiple parallel memory RAM immediately or depositor, and the number of RAM is total with output
Line number amount is identical, is derived from the elongated cell data of gating network module for caching, and according to control logic module transmission
3rd sequencing contro order, the elongated cell data completing timeslot multiplex in RAM or depositor is exported；
Control logic module, exports the elongated cell data caching to gating network module for control input memory module；
It is further used for controlling gating network module that the elongated cell data reading from input memory module is carried out gating output；And
It is further used for controlling output memory module to be exported the elongated cell data that timeslot multiplex completes；
Control logic module is polled to the elongated cell data in input memory module caching, if this caching is non-NULL, just
Read interior data, the number of slices reading data determines according to the length information of elongated cell, if length information exceedes simultaneously
Row output bus quantity, then only read and output bus quantity identical data, provide the configured information of first count simultaneously, remaining
Data read in next polling cycle, at most read to fetch data with output bus quantity identical, successively poll reading；If
Sky, then do not carry out data read-out.
2. the device supporting the elongated cell time slot multiplexing of multichannel as claimed in claim 1 is it is characterised in that described input stores
Module includes multiple sub-module stored, for the elongated cell of multichannel of caching input；Wherein,
When there being cell input, described sub-module stored is by non-NULL indication signal set.
3. the device supporting the elongated cell time slot multiplexing of multichannel as claimed in claim 2 is it is characterised in that described control logic
Module includes：
Internal control signal generation module, for producing rhythm control signal, and is respectively sent to input memory module, choosing
Open network module and output memory module；
Output control signal generation module, under the rhythm control signal generating for control signal generation module internally, will be defeated
Enter the non-null states in memory module and carry out gating output.
4. the device supporting the elongated cell time slot multiplexing of multichannel as claimed in claim 1 is it is characterised in that gating network module
Interior multiplexer, under the control of the rhythm control signal that control logic module sends, the elongated cell data receiving is carried out
Gating exports and is sent to output memory module.
5. a kind of method supporting the elongated cell time slot multiplexing of multichannel is it is characterised in that include：
Input memory module is cached respectively to the elongated cell of multichannel of input, and first sending according to control logic module
Sequencing contro order exports the elongated cell data caching to gating network module；
Wherein, control logic module is polled to the elongated cell data in input memory module caching, if this caching is non-
Sky, just reads interior data, and the number of slices reading data determines according to the length information of elongated cell, if length information surpasses
Cross parallel output bus number, then only read and output bus quantity identical data, provide the configured information of first count simultaneously,
Remaining data reads in next polling cycle, at most reads to fetch data with output bus quantity identical, poll reads successively；If
For sky, then do not carry out data read-out；
The the second sequencing contro order sending according to control logic module including the gating network module of multiple parallel multiplexers,
The elongated cell data reading from input memory module is carried out gating output；
Output memory module enters row cache to the elongated cell data from gating network module, and sends out according to control logic module
The 3rd sequencing contro order sent, the elongated cell data that timeslot multiplex is completed is exported；
Wherein said output memory module includes multiple parallel memory RAM immediately or depositor, and the number of RAM is total with output
Line number amount is identical, is derived from the elongated cell data of gating network module for caching, and according to control logic module transmission
3rd sequencing contro order, the elongated cell data completing timeslot multiplex in RAM or depositor is exported.
6. the method supporting the elongated cell time slot multiplexing of multichannel as claimed in claim 5 is it is characterised in that described input stores
Module includes multiple sub-module stored, for the elongated cell of multichannel of caching input；Wherein, in execution input memory module to defeated
Before the step that the elongated cell of multichannel entering is cached respectively, methods described also includes：
When there being cell input, described sub-module stored is by non-NULL indication signal set.
7. the method supporting the elongated cell time slot multiplexing of multichannel as claimed in claim 6 is it is characterised in that described control logic
Module includes：
Internal control signal generation module, for producing rhythm control signal, and is respectively sent to input memory module, choosing
Open network module and output memory module；
Output control signal generation module, under the rhythm control signal generating for control signal generation module internally, will be defeated
Enter the non-null states in memory module and carry out gating output.
8. the method supporting the elongated cell time slot multiplexing of multichannel as claimed in claim 5 is it is characterised in that described inclusion is multiple
The second sequencing contro order that the gating network module of parallel multiplexer sends according to control logic module, will be from input storage
The elongated cell data that module reads is carried out in the step gate output：
Multiplexer in gating network module under the control of the rhythm control signal that control logic module sends, by receive
Elongated cell data carries out gating and exports and be sent to output memory module.
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| CN201210384420.5A CN103731224B (en) | 2012-10-11 | 2012-10-11 | Device and method for supporting multi-length-variable-cell time slot multiplexing |
| PCT/CN2013/082493 WO2014056362A1 (en) | 2012-10-11 | 2013-08-28 | Device and method for supporting time-slot multiplexing of multichannel variable-length cells |
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| CN201210384420.5A CN103731224B (en) | 2012-10-11 | 2012-10-11 | Device and method for supporting multi-length-variable-cell time slot multiplexing |
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| CN101741720A (en) * | 2009-11-06 | 2010-06-16 | 中兴通讯股份有限公司 | Device and method for multichannel cell time slot multiplexing |
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| CN1819523A (en) * | 2006-02-20 | 2006-08-16 | 中国人民解放军国防科学技术大学 | Parallel interchanging switching designing method |
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| CN1422508A (en) * | 2000-03-23 | 2003-06-04 | 西门子移动通讯公司 | Telecommunication process and system handling data organized in cells of variable length |
| US7162034B1 (en) * | 2000-12-29 | 2007-01-09 | Cisco Technology, Inc. | Method and apparatus for multi-session time-slot multiplexing |
| CN101741720A (en) * | 2009-11-06 | 2010-06-16 | 中兴通讯股份有限公司 | Device and method for multichannel cell time slot multiplexing |
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| WO2014056362A1 (en) | 2014-04-17 |
| CN103731224A (en) | 2014-04-16 |
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