CN103731098A - Ring oscillator for frequency feedback - Google Patents
Ring oscillator for frequency feedback Download PDFInfo
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- CN103731098A CN103731098A CN201210390930.3A CN201210390930A CN103731098A CN 103731098 A CN103731098 A CN 103731098A CN 201210390930 A CN201210390930 A CN 201210390930A CN 103731098 A CN103731098 A CN 103731098A
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Abstract
The invention provides a ring oscillator for frequency feedback. The circuit comprises a current source control unit and a plurality of sets of delay units connected in series as a ring, wherein the current source control unit contains an output signal frequency feedback part, and the circuit converts the frequency of an output signal into a voltage to control a current signal; each delay unit is connected with an output signal of the front stage and outputs a delay signal after a period of time is delayed; each stage of delay unit is connected with a current source control signal to control the current of the delay unit, and thus the delay time of the delay unit can be controlled. Finally, the frequency of the output signal of the circuit is kept stable.
Description
Invention field
The present invention relates to integrated circuit fields, relate in particular to the ring oscillator that frequency stabilization is provided under various temperature voltage conditions.
Background technology
General current-control type ring oscillator needs a constant current bias techniques to carry out charge or discharge to the delay-level of Current Control, and in feedback ring loop, forms delay cell to produce vibration.Fig. 1 is the circuit diagram of this kind of current-control type ring oscillator.As shown in the drawing, this ring oscillator 100 is by odd number (>=3) the delay cell 101 rear feedback ring loops that form of annular serial connection.Each delay cell 101 is formed by serving as the transistor P102 of current source and transistor N103 and transistor P104 and transistor N105.This circuit also comprises the current source control unit 106 being connected with ring oscillator 100, for suitable current source is provided.This ring oscillator is subject to the impact of temperature and supply voltage and can produces larger frequency shift (FS), even by regulating current source to carry out the temperature coefficient of transistor P104 in compensating delay unit 101, N105 threshold value to certain temperature coefficient, this circuit still can produce because of the skew of supply voltage larger frequency shift (FS).In the higher circuit of some required precisions, be difficult to meet design requirement.
Summary of the invention
In view of the above problems, the object of the invention is to propose a kind ofly can not produce the ring oscillator of frequency shift (FS) with temperature voltage skew.
For achieving the above object, the current source control unit that frequency feedback annular oscillator of the present invention comprises a clock signal frequency feedback, it connects clock signal CLK, and converts its frequency of oscillation to voltage signal, relatively produces at least one current source control signal with a reference voltage; And the delay cell of many group annulars series connection, each delay cell is exported an inhibit signal after connecting the output signal of previous stage and postponing certain hour, wherein every grade of delay cell connects current source control signal, and by this current source control signal, carried out the electric current of control lag unit, decide the time of delay of each unit.
By said frequencies feedback mechanism, the frequency of clock signal determines the characteristic by feedback circuit, be no longer subject to annular series connection delay cell temperature coefficient and connect the impact of supply voltage.And frequency feedback circuit is stabilized in the charging interval of internal current source to electric capacity by output frequency, the two has very little temperature coefficient and supply voltage impact, thereby can produce the highly stable oscillator signal of frequency.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of conventional current control type ring oscillator;
Fig. 2 is circuit structure block diagram of the present invention;
Fig. 3 is that frequency of the present invention turns voltage sequential control circuit figure;
Fig. 4 is that frequency of the present invention turns voltage sequential control circuit output signal timing diagram;
Fig. 5 is that frequency of the present invention turns voltage generating circuit figure;
Fig. 6 is constant biasing circuit for generating figure of the present invention;
Fig. 7 is current-control type ring oscillator circuit figure of the present invention.
Embodiment
Below with reference to accompanying drawing, describe frequency feedback annular oscillator of the present invention in detail.
Fig. 2 is the block diagram of frequency feedback annular oscillator of the present invention.Fig. 2 by shown in constant current control unit 1 and current limit type annular oscillation circuit 2 form, wherein constant current control unit 1 comprises that frequency turns voltage sequential control circuit 3, frequency turns voltage generating circuit 4 and constant biasing circuit for generating 5.
Fig. 3 represents that frequency turns voltage sequential control circuit 3, the oscillator output of current limit type ring oscillator 2 is transfused to clock end and the inverter I301 of d type flip flop I302, anti-phase output-Q1 of d type flip flop I302 is connected with its data input pin D1, its forward output Q1 is through buffer I304 output control signal SW1, and the output of buffer I304 is through inverter I306 output control signal SW0.The output of inverter I301 is imported into the clock end of d type flip flop I303, its anti-phase output-Q2 is connected with its data input pin D2, its forward output Q2 is through buffer I305 output control signal SW3, and the output of buffer I305 is through inverter I307 output control signal SW2.The forward output Q1 of d type flip flop I302 and I303 and Q2 export through four branch roads, one for Q1 is imported into NAND door I316 through the output of buffer I308 and the output of Q2 process inverter I312, and the output of NAND door I316 is through inverter I320 output control signal SW4.One output and Q1 for Q2 process buffer I309 is imported into NAND door I317, and the output of NAND door I317 is through inverter I321 output control signal SW5.One output and Q2 for Q1 process buffer I310 and inverter I313 is imported into NAND door I318, and the output of NAND door I318 is through inverter I322 output control signal SW6.One for Q2 is imported into NAND door I319 through the output of buffer I311 and inverter I315 and the output of Q2 process inverter I314, and the output of NAND door I319 is through inverter I323 output control signal SW7.
Figure 4 shows that frequency turns the sequential relationship of voltage sequential control circuit output signal.
Fig. 5 represents that frequency turns voltage generating circuit 4, has four paths between power vd D and output node Vout: one is transistor P501, transistor P502, transistor N501 three series connection; One is transistor P503, transistor P504, transistor N503 three series connection; One is transistor P505, transistor P506, transistor N505 three series connection; One is transistor P507, transistor P508, transistor N507 three series connection; The node that wherein transistor P502 is connected with transistor N501 is A, and between node A and GND, transistor N502 is in parallel with capacitor C 501; The node that wherein transistor P504 is connected with transistor N503 is B, and between Node B and GND, transistor N504 is in parallel with capacitor C 502; The node that wherein transistor P506 is connected with transistor N505 is C, and between node C and GND, transistor N506 is in parallel with capacitor C 503; The node that wherein transistor P508 is connected with transistor N507 is D, and between node D and GND, transistor N508 is in parallel with capacitor C 504; Between output node Vout and GND, be connected capacitor C 505.The grid of transistor P501, P503, P505, P507 connects external reference current source control signal, makes transistor P501, P503, P505, the P507 of same size obtain identical On current.The grid of transistor P502 connects input signal SW<0>; The grid of transistor N501 connects input signal SW<6>; The grid of transistor N502 connects input signal SW<7>; The grid of transistor P504 connects input signal SW<1>; The grid of transistor N503 connects input signal SW<4>; The grid of transistor N504 connects input signal SW<5>; The grid of transistor P506 connects input signal SW<2>; The grid of transistor N505 connects input signal SW<7>; The grid of transistor N506 connects input signal SW<4>; The grid of transistor P508 connects input signal SW<3>; The grid of transistor N507 connects input signal SW<5>; The grid of transistor N508 connects input signal SW<6>.
Fig. 6 represents amplifier feedback constant current bias generation circuit 5, and the output Vout signal that its medium frequency turns voltage generating circuit 4 is connected the negative input end that is input to amplifier I601, and external reference voltage signal Vref is connected to the positive input terminal of amplifier I601; The output of amplifier I601 is directly exported with Pbias as the gate bias of the P transistor npn npn of subsequent current restricted type ring oscillator, and signal Pbias is imported into the grid of transistor P602, and the source electrode of transistor P602 connects VDD; The drain and gate of transistor N603 together connects the drain electrode of transistor P602, and exports with Nbias as the gate bias of subsequent conditioning circuit P transistor npn npn.The source class of transistor N603 connects GND.
To Fig. 5, Fig. 6, frequency turns voltage generating circuit 4 and amplifier feedback constant current bias generation circuit 5 is described in detail below.The function that frequency turns voltage generating circuit 4 is in every half period of clock signal clk, by switching transistor N501, N503, N505, N507 makes respectively capacitor C 501, C502, C503, electric charge on C504 and C505 carry out electric charge distribution, and capacitor C 501, C502, C503, electric charge on C504 is by switching transistor P502, P504, P506, P508 opens and makes current source P501, P503, P505, P507 is respectively to capacitor C 501, C502, C503, the C504 acquisition of charging, because each charging interval is the cycle (T=1/f) of a clock CLK, its magnitude of voltage is V=Iref/(C0*f), wherein Iref is input constant-current source electric current, C0 is C501, C502, C503, the capacitance of C504, f is the output frequency of current limit type annular oscillation circuit 2.Through several voltage distribution, to make the voltage on C505 charge to Vout=V=Iref/(C0*f), and the amplifier feedback effect of Vout voltage by constant biasing circuit for generating 5 is stabilized in Vref by Vout, so can obtain Vref=Iref/(C0*f), be output frequency f=Iref/(C0*Vref), because parameter I ref, C0 wherein, Vref are irrelevant with external condition temperature, VDD, therefore can access high-precision oscillator.
According to Figure 4 shows that frequency turns the sequential relationship of voltage sequential control circuit output signal, come analysis frequency to turn the concrete action of potential circuit.If the cycle time that T is clock signal clk.Suppose a 0 trailing edge arriving of signal SW1 constantly, Iref charges to capacitor C 502 by transistor P503.After T/2, signal SW3 trailing edge arrives, and Iref charges to capacitor C 504 by transistor P507.After T, signal SW0 trailing edge arrives, and Iref charges to capacitor C 501 by transistor P502.And the rising edge of signal SW1 arrives, and the charging of C502 is finished, and the charging interval is one-period T, the voltage VB=Iref*T/C502=Iref/(C0*f on C502)=Vinit.The time delay of elapsed time t, signal SW4 rising edge arrives, and C501 and C505 are carried out to electric charge distribution by transistor N503, and establishing C505 is Cout, and distributing afterwards Vout rising value is ((Vinit-Vout) * C0)/(C0+Cout).Before 3T/2, the trailing edge of signal SW6 arrives, and electric charge distributes end.After 3T/2, signal SW2 trailing edge arrives, and Iref charges to capacitor C 503 by transistor P506.And the rising edge of signal SW3 arrives, and the charging of C504 is finished to the voltage VD=Iref*T/C504=Iref/(C0*f on C504)=Vinit.And the time delay of elapsed time t, signal SW5 rising edge arrives, C504 and C505 are carried out to electric charge distribution by transistor N507, after distributing, Vout rising value is again ((Vinit-Vout) * C0)/(C0+Cout), just because Vout before has had certain voltage, so the voltage rising value of Vout once has decline before comparing.And signal SW5 drains the electric charge in capacitor C 502 by transistor N504, make VB=0V.Then again wait for charging next time.Before 2T, signal SW5 trailing edge arrives.So circulation, respectively by distributing to the charging of capacitor C 501, C502, C503, C504 with to the electric charge of C505, make Vout rise ((Vinit-Vout) * C0) at every turn/(C0+Cout), and finally reach Vinit.
Fig. 7 represents current limit type annular oscillation circuit 2, adopts annular oscillation circuit part traditional in Fig. 1, i.e. annular oscillation circuit in Fig. 1 100 in present embodiment.This circuit has only played the function that produces adjustable clock signal clk, and the size of concrete frequency is determined by feedback circuit above, also just eliminated due to the impact of transistor threshold temperature coefficient on frequency.In other execution mode, also can adopt the ring oscillator of other structure, as differential configuration ring oscillator.
The foregoing is only exemplary embodiment of the present invention.Any modification of having done within spirit of the present invention and improvement, within all should being included in claim protection range of the present invention.
Claims (10)
1. a ring oscillator for frequency feedback, comprising:
The current source control unit that comprises output signal frequency feedback, it connects clock signal CLK, and converts frequency of oscillation to voltage signal, relatively produces at least one current source control signal with the first reference voltage; With
The delay cell of many group ring-types series connection, output delay signal after each delay cell connects the output signal of previous stage and postpones certain hour;
Wherein, every grade of delay cell connects described current source control signal, and by described current source control signal, is controlled the electric current of described each delay cell, decides the time of delay of described each delay cell.
2. ring oscillator as claimed in claim 1, wherein, described current source control unit comprises:
Frequency turns potential circuit, and its input connects clock signal clk, output output feedback voltage signal;
Operational amplifier, its positive input terminal connects described the first reference voltage, and its negative input end connects the feedback voltage signal that turns potential circuit from described frequency, and the output of described operational amplifier is exported the first current source control signal;
Bias unit, it connects described the first current source control signal, and exports the second current source control signal.
3. ring oscillator as claimed in claim 2, wherein, described frequency turns potential circuit and comprises:
Sequential logical circuit, its input connects clock signal clk, following 8 sequential logic signal: the SW0 of output output, SW1, SW2, SW3, SW4, SW5, SW6, SW7;
Switched-capacitor circuit, its input is from described 8 sequential logic signals of described sequential logical circuit, and reference current source control signal Iref, is output as described feedback voltage signal Vout.
4. ring oscillator as claimed in claim 3, wherein, described sequential logical circuit comprises:
The first not gate, its input terminal connects described clock signal clk;
The first d type flip flop, its input clock terminal connects described clock signal clk, D1 input terminal and reverse output-Q1 terminal is connected;
The second d type flip flop, its input clock terminal connects the lead-out terminal of described the first not gate, D2 input terminal and reverse output-Q2 terminal is connected;
The first buffer cell, its input connects the forward lead-out terminal Q1 of described the first d type flip flop, and output is SW0 signal;
The second not gate, its input terminal connects the output of described the first buffer cell, and output is SW1 signal;
The second buffer cell, its input connects the forward lead-out terminal Q2 of described the second d type flip flop, and output is SW2 signal;
The 3rd not gate, its input terminal connects the output of described the second buffer cell, and output is SW3 signal;
The 3rd buffer cell, its input connects the forward lead-out terminal Q1 of described the first d type flip flop;
The 4th not gate, its input connects the forward lead-out terminal Q2 of described the second d type flip flop;
The 4th buffer cell, its input connects the forward lead-out terminal Q2 of described the second d type flip flop;
The 5th buffer cell, its input connects the forward lead-out terminal Q1 of described the first d type flip flop;
The 5th not gate, its input connects the output of described the 5th buffer cell;
The 6th not gate, its input connects the forward lead-out terminal Q1 of described the first d type flip flop;
The 6th buffer cell, its input connects the forward lead-out terminal Q2 of described the second d type flip flop;
The 7th not gate, its input connects the output of described the 6th buffer cell;
The first NAND gate, two input connects respectively the output of described the 3rd buffer cell and the output of described the 4th not gate;
The second NAND gate, two input connects respectively the forward lead-out terminal Q1 of described the first d type flip flop and the output of described the 4th buffer cell;
The 3rd NAND gate, two input connects respectively the output of described the 5th not gate and the forward output Q2 of described the second d type flip flop;
The 4th NAND gate, two input connects respectively the output of described the 6th not gate and the output of described the 7th not gate;
The 8th not gate, its input connects the output of described the first NAND gate, and output is SW4 signal;
The 9th not gate, its input connects the output of described the second NAND gate, and output is SW5 signal;
The tenth not gate, its input connects the output of described the 3rd NAND gate, and output is SW6 signal;
The 11 not gate, its input connects the output of described the 4th NAND gate, and output is SW7 signal.
5. ring oscillator as claimed in claim 4, wherein, described first, the second d type flip flop is identical d type flip flop, wherein said first, second, the 3rd, the 4th, the 5th, the 6th, the 7th, the 8th, the 9th, the tenth, the 11 not gate is all identical not gate, the wherein said the 3rd, the 4th, the 5th, the 6th buffer cell is all identical buffer cell, wherein said first, the second buffer cell is all identical buffer cell, and described first, the buffer time of the second buffer cell is half of described the 3rd buffer cell, wherein said first, second, the 3rd, the 4th NAND gate is all identical NAND gate.
6. the ring oscillator as described in any one in claim 3-5, wherein, described switched-capacitor circuit comprises:
The first field-effect transistor, its grid connects described reference current source control signal, and source class connects power vd D, forms a current source circuit;
The second field-effect transistor, its grid connects described SW0 signal, and source class connects the drain electrode of described the first field-effect transistor, forms a switch;
The 3rd field-effect transistor, its grid connects described SW6 signal, and source class connects the drain electrode of described the second field-effect transistor, and grounded drain forms a switch;
The first electric capacity, its one end connects the drain electrode of described the first field-effect transistor, other end ground connection;
The 4th field-effect transistor, its grid connects described SW7 signal, and source class connects the drain electrode of described the second field-effect transistor, forms a switch;
The 5th field-effect transistor, its grid connects described reference current source control signal, and source class connects power vd D, forms a current source circuit;
The 6th field-effect transistor, its grid connects described SW1 signal, and source class connects the drain electrode of described the 5th field-effect transistor, forms a switch;
The 7th field-effect transistor, its grid connects described SW4 signal, and source class connects the drain electrode of described the 6th field-effect transistor, and grounded drain forms a switch;
The second electric capacity, its one end connects the drain electrode of described the 5th field-effect transistor, other end ground connection;
The 8th field-effect transistor, its grid connects described SW5 signal, and source class connects the drain electrode of described the 6th field-effect transistor, forms a switch;
The 9th field-effect transistor, its grid connects described reference current source control signal, and source class connects power vd D, forms a current source circuit;
The tenth field-effect transistor, its grid connects described SW2 signal, and source class connects the drain electrode of described the 9th field-effect transistor, forms a switch;
The 11 field-effect transistor, its grid connects described SW7 signal, and source class connects the drain electrode of described the tenth field-effect transistor, and grounded drain forms a switch;
The 3rd electric capacity, its one end connects the drain electrode of described the 9th field-effect transistor, other end ground connection;
The 12 field-effect transistor, its grid connects described SW4 signal, and source class connects the drain electrode of described the tenth field-effect transistor, forms a switch;
The 13 field-effect transistor, its grid connects described reference current source control signal, and source class connects power vd D, forms a current source circuit;
The 14 field-effect transistor, its grid connects described SW3 signal, and source class connects the drain electrode of described the 13 field-effect transistor, forms a switch;
The 15 field-effect transistor, its grid connects described SW5 signal, and source class connects the drain electrode of described the 14 field-effect transistor, and grounded drain forms a switch;
The 4th electric capacity, its one end connects the drain electrode of described the 13 field-effect transistor, other end ground connection;
The 16 field-effect transistor, its grid connects described SW6 signal, and source class connects the drain electrode of described the 14 field-effect transistor, forms a switch;
The 5th electric capacity, that its one end connects is described second, the 6th, the tenth, the drain electrode of the 14 field-effect transistor, other end ground connection, for preserving the electric charge of described feedback voltage signal Vout.
7. ring oscillator as claimed in claim 6, wherein, described first, the 5th, the 9th, the source class of the 13 field-effect transistor, grid connects identical voltage and is identical field-effect transistor, wherein said second, the 6th, the tenth, the 14 field-effect transistor is identical field-effect transistor, the wherein said the 3rd, the 7th, the 11, the 15 field-effect transistor is identical field-effect transistor, the wherein said the 4th, the 8th, the 12, the 16 field-effect transistor is identical field-effect transistor, wherein said first, second, the 3rd, the 4th electric capacity is identical electric capacity.
8. ring oscillator as claimed in claim 2, wherein, described bias unit comprises:
The 16 field-effect transistor, its grid connects described the first current source control signal, and source class connects power vd D;
The 17 field-effect transistor, its drain electrode connects the drain electrode with described the 16 field-effect transistor, source class ground connection, grid is connected with drain electrode.
9. ring oscillator as claimed in claim 1, wherein, each delay unit comprises:
The 18 field-effect transistor, its grid connects described the first current source control signal, and source class connects power vd D, with the framework of described the 16 field-effect transistor formation current mirror;
The 19 field-effect transistor, its grid connects the output signal of previous stage delay cell, and source class connects power vd D;
The 20 field-effect transistor, its grid connects the output signal of previous stage delay cell, and drain electrode connects the drain electrode of described the 19 field-effect transistor;
The 21 field-effect transistor, its grid connects described the second current source control signal, and drain electrode connects the source class of described the 20 field-effect transistor, and source class ground connection, with the framework of described the 17 field-effect transistor formation current mirror.
10. ring oscillator as claimed in claim 9, wherein, described the 18, the grid of the 16 field-effect transistor, source class connect identical voltage and are identical field-effect transistors, and described the 21, the grid of the 17 field-effect transistor, source class connect identical voltage and be identical field-effect transistor.
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| CN201210390930.3A CN103731098A (en) | 2012-10-15 | 2012-10-15 | Ring oscillator for frequency feedback |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106888004A (en) * | 2017-01-10 | 2017-06-23 | 西安紫光国芯半导体有限公司 | A kind of ring oscillator |
| CN114545807A (en) * | 2020-11-25 | 2022-05-27 | 长鑫存储技术有限公司 | Control circuit and delay circuit |
| CN117097307A (en) * | 2023-07-17 | 2023-11-21 | 北京思凌科半导体技术有限公司 | Loop oscillator circuit |
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| CN1848667A (en) * | 2005-04-04 | 2006-10-18 | 凌阳科技股份有限公司 | Ring oscillator for compensating voltage source offset |
| US20080068091A1 (en) * | 2006-05-19 | 2008-03-20 | Broadcom Corporation | Frequency-locked clock generator |
| CN101807920A (en) * | 2010-03-10 | 2010-08-18 | 东南大学 | Self-adaptive frequency calibration frequency synthesizer |
| CN102571081A (en) * | 2011-12-31 | 2012-07-11 | 上海贝岭股份有限公司 | Delay lock loop circuit |
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| US20060076992A1 (en) * | 2004-10-12 | 2006-04-13 | Samsung Electronics Co., Ltd. | Delay locked loops and methods using ring oscillators |
| CN1848667A (en) * | 2005-04-04 | 2006-10-18 | 凌阳科技股份有限公司 | Ring oscillator for compensating voltage source offset |
| US20080068091A1 (en) * | 2006-05-19 | 2008-03-20 | Broadcom Corporation | Frequency-locked clock generator |
| CN101807920A (en) * | 2010-03-10 | 2010-08-18 | 东南大学 | Self-adaptive frequency calibration frequency synthesizer |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106888004A (en) * | 2017-01-10 | 2017-06-23 | 西安紫光国芯半导体有限公司 | A kind of ring oscillator |
| CN114545807A (en) * | 2020-11-25 | 2022-05-27 | 长鑫存储技术有限公司 | Control circuit and delay circuit |
| CN114545807B (en) * | 2020-11-25 | 2024-03-26 | 长鑫存储技术有限公司 | Control circuit and delay circuit |
| CN117097307A (en) * | 2023-07-17 | 2023-11-21 | 北京思凌科半导体技术有限公司 | Loop oscillator circuit |
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