CN103728827B - 光掩膜、薄膜晶体管元件及制作薄膜晶体管元件的方法 - Google Patents

光掩膜、薄膜晶体管元件及制作薄膜晶体管元件的方法 Download PDF

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CN103728827B
CN103728827B CN201310733217.9A CN201310733217A CN103728827B CN 103728827 B CN103728827 B CN 103728827B CN 201310733217 A CN201310733217 A CN 201310733217A CN 103728827 B CN103728827 B CN 103728827B
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CN103728827A (zh
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衣志光
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Abstract

本发明实施例公开了一种用于定义薄膜晶体管元件的数据层及半导体层的图案的光掩膜。该光掩膜上开设有贯穿该光掩膜的多条狭缝，该多条狭缝彼此平行并等间距排列。该光掩膜上除该多条狭缝以外的区域被定义为遮光图案区，该遮光图案区将该多条狭缝包围起来。另外，本发明实施例还公开了一种薄膜晶体管元件及一种制作薄膜晶体管元件的方法。

Description

光掩膜、薄膜晶体管元件及制作薄膜晶体管元件的方法
技术领域
本发明涉及液晶显示领域，尤其涉及一种薄膜晶体管元件、一种用于制作该薄膜晶体管元件的光掩膜以及一种制作该薄膜晶体管元件的方法。
背景技术
在薄膜晶体管液晶显示器(ThinFilmTransistorLiquidCrystalDisplay，TFT-LCD)内，薄膜晶体管元件是作为控制各像素电极的开关元件。
在利用光掩膜制作薄膜晶体管元件时需要对残留的半导体层的厚度进行测量以监控整个制程有无异常，其中，测量残留半导体层的厚度是在薄膜晶体管上的沟道处进行的。目前，制作薄膜晶体管元件用到的光掩膜通常是单狭缝结构，只有对与狭缝处对应的基板进行两次湿蚀刻及一次干蚀刻才能使与狭缝处对应的半导体层裸露，再经过第二次干蚀刻，才能在该半导体层上形成沟道。由于光掩膜的单狭缝的长度较小，因此，被蚀刻出的沟道的长度也较小，致使测量工具无法准确测量出残留半导体层的厚度，由此薄膜晶体管元件的品质难以得到有效管控。
因此，有必要提供能够解决上述问题的光掩膜、薄膜晶体管元件及制作薄膜晶体管元件的方法。
发明内容
为了解决上述技术问题，本发明实施例提供了一种用于定义薄膜晶体管元件的数据层及半导体层的图案的光掩膜。该光掩膜上开设有贯穿该光掩膜的多条狭缝，该多条狭缝彼此平行并等间距排列。该光掩膜上除该多条狭缝以外的区域被定义为遮光图案区，该遮光图案区将该多条狭缝包围起来。
其中，每条狭缝均为细长的长方形。
其中，每条狭缝的宽度介于1.5微米至2.5微米之间。
其中，该遮光图案区由完全不透光材料构成。
为了解决上述技术问题，本发明实施例还提供了一种使用上述光掩膜制造的薄膜晶体管元件，该薄膜晶体管元件包括基板、栅极、栅极绝缘层、半导体层、掺杂层以及数据层。该栅极设置在该基板上。该栅极绝缘层设置在该基板上并覆盖该栅极。该半导体层设置在该栅极绝缘层上并包括一个平坦部及多个自该平坦部垂直向上突出的突出部。该多个突出部彼此平行并等间距排列。该平坦部与该光掩膜上的遮光图案区对应，该多个突出部与该光掩膜上的多个狭缝对应。该掺杂层设置在该多个突出部上。该数据层被划分为多个彼此平行并等间距排列的数据条，每个数据条均位于该掺杂层上并与该多个突出部对应，该数据层的图案由该光掩膜定义。
其中，该半导体层为非晶硅半导体层。
其中，该多个突出部及该多个数据条均呈细长的长方形。
其中，该多个突出部的宽度及该多个数据条的宽度均介于1.5微米至2.5微米之间。
为了解决上述技术问题，本发明实施例还提供了一种制作薄膜晶体管元件的方法，该方法包括：提供一个基板，并在该基板上依序形成栅极、栅极绝缘层、半导体层、掺杂层及数据层；在该数据层上形成原始光致抗蚀剂层；通过湿蚀刻的方式去除一定厚度的原始光致抗蚀剂层以得到一个中间光致抗蚀剂层；提供一个光掩膜，该光掩膜上开设有贯穿该光掩膜的多条狭缝，该多条狭缝彼此平行并等间距排列，该光掩膜上除该多条狭缝以外的区域被定义为遮光图案区，该遮光图案区将该多条狭缝包围起来；通过干蚀刻的方式去除与该遮光图案区对应的中间光致抗蚀剂层以得到一个剩余光致抗蚀剂层；通过湿蚀刻的方式去除未被该剩余光致抗蚀剂层遮盖的数据层；通过干蚀刻的方式去除未被该剩余光致抗蚀剂层遮盖的掺杂层及部分未被该剩余光致抗蚀剂层遮盖的半导体层；及去除该剩余光致抗蚀剂层。
其中，通过干蚀刻的方式去除与该遮光图案区对应的中间光致抗蚀剂层以得到一个剩余光致抗蚀剂层包括以下步骤：光线通过该光掩膜照射在该中间光致抗蚀剂层上以对该中间光致抗蚀剂层进行曝光；及对该中间光致抗蚀剂层进行显影工艺，以去除未被曝光的中间光致抗蚀剂层，而保留被曝光的中间光致抗蚀剂层，得到一个剩余光致抗蚀剂层。
本发明所提供的薄膜晶体管元件及利用该光掩膜制作薄膜晶体管元件的方法将半导体层完全裸露出来，如此便可以直接测量半导体层的厚度，而不会因为被蚀刻出的沟道的长度较小而受到限制，因而能够保证半导体层厚度测量的准确性，薄膜晶体管元件的品质便能够较容易地被管控。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明第一实施例提供的光掩膜的剖面示意图。
图3至图7是本发明第二实施例提供的利用图1中的光掩膜制作薄膜晶体管元件的方法的示意图。
图8是图7中的薄膜晶体管元件的俯视图。
具体实施例
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例一
请参阅图1，本发明第一实施例提供的光掩膜10呈矩形，其可为灰阶光掩膜(graytonemask，GTM)、半色调光掩膜(halftonemask，HTM)或其他在不同区域可具有不同透光率的光掩膜。本实施例中的光掩膜10上开设有贯穿该光掩膜10的多条狭缝12。该多条狭缝12彼此平行并等间距排列而形成一个阵列，每条狭缝12均为细长的长方形，每条狭缝12的宽度最佳介于1.5微米至2.5微米之间。该光掩膜10上除该多条狭缝12以外的区域被定义为遮光图案区14，该遮光图案区14将该多条狭缝12包围起来。该遮光图案区14由完全不透光材料构成，其透光率为0％，也即完全不透光。
请结合图7及图8，本实施例中的光掩膜10是用于定义薄膜晶体管元件100的数据层70及半导体层50的图案，其中，该多条狭缝12用于定义该数据层70的图案，该遮光图案区14用于定义沟道52的宽度。
第二实施例
请一并参阅图2至图7，本发明第二实施例提供的利用该光掩膜10制作薄膜晶体管元件100(图8示)的方法，包括以下步骤：
第一步，请参阅图2，提供一个基板20，并依序在该基板20上形成栅极30、栅极绝缘层40、半导体层50、掺杂层(或称欧姆接触层)60、数据层70。其中，该基板20由玻璃或者塑胶制成。本实施例中，该基板20由玻璃制成。该栅极30为钼层、铝层、钛层或铜层，或者是任意两层的堆叠。该栅极绝缘层40一般为SiNx层。该半导体层50为非晶硅(a-Si)半导体层。
第二步，请参阅图2，在该数据层70上形成原始光致抗蚀剂层80。该原始光致抗蚀剂层80的厚度为D。本实施例中，该原始光致抗蚀剂层80为负型光刻胶，即，进行曝光显影程序后，被光照到的原始光致抗蚀剂层80被保留下来，而未被光照到的原始光致抗蚀剂层80就会被去除。
第三步，请参阅图3，通过湿蚀刻的方式去除一定厚度的原始光致抗蚀剂层80。如此，得到一个中间光致抗蚀剂层82，其厚度小于D。
第四步，请参阅图3，提供一个光掩膜10，该光掩膜10的特征与第一实施例中所描述一致，在此不再赘述。
第五步，请参阅图3及图4，通过干蚀刻的方式去除与该遮光图案区14对应的中间光致抗蚀剂层82。具体为：首先，光线通过该光掩膜10照射在该中间光致抗蚀剂层82上以对该中间光致抗蚀剂层82进行曝光。接着，对该中间光致抗蚀剂层82进行显影工艺，以去除未被曝光的中间光致抗蚀剂层82，而保留被曝光的中间光致抗蚀剂层82。即，经过显影工艺后，该中间光致抗蚀剂层82上与该多条狭缝12对应的区域被保留，该中间光致抗蚀剂层82上与该遮光图案区14对应的区域被去除。如此，得到一个剩余光致抗蚀剂层84。
第六步，请一并参阅图4及图5，通过湿蚀刻的方式去除未被该剩余光致抗蚀剂层84遮盖的数据层70。
第七步，请一并参阅图5及图6，通过干蚀刻的方式去除未被该剩余光致抗蚀剂层84遮盖的掺杂层60及部分未被该剩余光致抗蚀剂层84遮盖的半导体层50。如此，沟道52被蚀刻出来，而且半导体层50也完全裸露出来。
第八步，去除该剩余光致抗蚀剂层84，以得到薄膜晶体管元件100。
第三实施例
请一并参阅图7及图8，本发明第三实施例提供的薄膜晶体管元件100包括基板20、栅极30、栅极绝缘层40、半导体层50、掺杂层60以及数据层70。
该基板20由玻璃或者塑胶制成。本实施例中，该基板20由玻璃制成。该栅极30设置在该基板20上，其为钼层、铝层、钛层或铜层，或者是任意两层的堆叠。该栅极绝缘层40设置在该基板20上并覆盖该栅极30，且该栅极绝缘层40一般为SiNx层。该半导体层50为非晶硅(a-Si)半导体层，位于该栅极绝缘层40上。该半导体层50包括一个平坦部54及多个自该平坦部54垂直向上突出的突出部56，每两个突出部56之间的平坦部54与该两个突出部56共同形成一个沟道52。该平坦部54的形状及位置与该光掩膜10上的遮光图案区14的形状及位置对应，该多个突出部56的形状及位置与该光掩膜10上的多个狭缝12的形状及位置对应。具体地，该多个突出部56彼此平行并等间距排列而形成一个阵列，每个突出部56均呈细长的长方形，每个突出部56的宽度最佳介于1.5微米至2.5微米之间。该掺杂层60位于该多个突出部56上。该数据层70位于该掺杂层60上，该数据层70的图案与该多个突出部56对应，即该数据层70被划分为多个彼此平行并等间距排列的数据条72，每个数据条72均呈细长的长方形。
本发明的薄膜晶体管元件100及利用该光掩膜10制作薄膜晶体管元件100的方法将半导体层50完全裸露出来，如此便可以直接测量半导体层50的厚度，而不会因为被蚀刻出的沟道52的长度较小而受到限制，因而能够保证半导体层50厚度测量的准确性，薄膜晶体管元件100的品质便能够较容易地被管控。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (6)

1.一种薄膜晶体管元件，其特征在于，该薄膜晶体管元件包括：
基板(20)；
栅极(30)，设置在该基板(20)上；
栅极绝缘层(40)，设置在该基板(20)上并覆盖该栅极(30)；
半导体层(50)，设置在该栅极绝缘层(40)上并包括一个平坦部(54)及多个自该平坦部(54)垂直向上突出的突出部(56)，该多个突出部(56)彼此平行并等间距排列，该平坦部(54)与光掩膜(10)上的遮光图案区(14)对应，该多个突出部(56)与该光掩膜(10)上的多个狭缝(12)对应；所述光掩膜，用于定义薄膜晶体管元件(100)的数据层(70)及半导体层(50)的图案，该光掩膜(10)上开设有贯穿该光掩膜(10)的多条狭缝(12)，该多条狭缝(12)彼此平行并等间距排列，该光掩膜(10)上除该多条狭缝(12)以外的区域被定义为遮光图案区(14)，该遮光图案区(14)将该多条狭缝(12)包围起来；
掺杂层(60)，设置在该多个突出部(56)上；及
数据层(70)，被划分为多个彼此平行并等间距排列的数据条(72)，每个数据条(72)均位于该掺杂层(60)上并与该多个突出部(56)对应，该数据层(60)的图案由该光掩膜(10)定义。
2.如权利要求1所述的薄膜晶体管元件，其特征在于，该半导体层(50)为非晶硅半导体层。
3.如权利要求1所述的薄膜晶体管元件，其特征在于，该多个突出部(56)及该多个数据条(72)均呈细长的长方形。
4.如权利要求1所述的薄膜晶体管元件，其特征在于，该多个突出部(56)的宽度及该多个数据条(72)的宽度均介于1.5微米至2.5微米之间。
5.一种制作薄膜晶体管元件的方法，其特征在于，该方法包括：
提供一个基板(20)，并在该基板(20)上依序形成栅极(30)、栅极绝缘层(40)、半导体层(50)、掺杂层(60)及数据层(70)；
在该数据层(70)上形成原始光致抗蚀剂层(80)；
通过湿蚀刻的方式去除一定厚度的原始光致抗蚀剂层(80)以得到一个中间光致抗蚀剂层(82)；
提供一个光掩膜(10)，该光掩膜(10)上开设有贯穿该光掩膜(10)的多条狭缝(12)，该多条狭缝(12)彼此平行并等间距排列，该光掩膜(10)上除该多条狭缝(12)以外的区域被定义为遮光图案区(14)，该遮光图案区(14)将该多条狭缝(12)包围起来；
通过干蚀刻的方式去除与该遮光图案区(14)对应的中间光致抗蚀剂层(82)以得到一个剩余光致抗蚀剂层(84)；
通过湿蚀刻的方式去除未被该剩余光致抗蚀剂层(84)遮盖的数据层(70)；
通过干蚀刻的方式去除未被该剩余光致抗蚀剂层(84)遮盖的掺杂层(60)及部分未被该剩余光致抗蚀剂层(84)遮盖的半导体层(50)；及
去除该剩余光致抗蚀剂层(84)。
6.如权利要求5所述的制作薄膜晶体管元件的方法，其特征在于，通过干蚀刻的方式去除与该遮光图案区(14)对应的中间光致抗蚀剂层(82)以得到一个剩余光致抗蚀剂层(84)包括以下步骤：
光线通过该光掩膜(10)照射在该中间光致抗蚀剂层(82)上以对该中间光致抗蚀剂层(82)进行曝光；及
对该中间光致抗蚀剂层(82)进行显影工艺，以去除未被曝光的中间光致抗蚀剂层(82)，而保留被曝光的中间光致抗蚀剂层(82)，得到一个剩余光致抗蚀剂层(84)。
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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
CN106125500B (zh) * 2016-08-31 2020-02-07 深圳市华星光电技术有限公司 光掩模及黑色光阻间隔层的制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101872114B (zh) * 2009-04-24 2012-03-28 中芯国际集成电路制造(上海)有限公司 用于制造金属互连线的掩模板版图
CN102651402A (zh) * 2011-02-24 2012-08-29 三星电子株式会社 布线、薄膜晶体管、薄膜晶体管面板及其制造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1174359C (zh) * 1999-03-04 2004-11-03 三星电子株式会社 反射型液晶显示器及其制造方法
KR100750872B1 (ko) * 2001-01-18 2007-08-22 엘지.필립스 엘시디 주식회사 액정표장치용 어레이기판과 그 제조방법
US6573163B2 (en) * 2001-01-29 2003-06-03 Sharp Laboratories Of America, Inc. Method of optimizing channel characteristics using multiple masks to form laterally crystallized ELA poly-Si films
KR100379684B1 (ko) * 2001-04-20 2003-04-10 엘지.필립스 엘시디 주식회사 박막 트랜지스터 액정표시소자 제조방법
KR20030002947A (ko) * 2001-07-03 2003-01-09 엘지전자 주식회사 풀칼라 유기 ｅｌ 표시소자 및 제조방법
US6787831B2 (en) * 2002-01-15 2004-09-07 Infineon Technologies Aktiengesellschaft Barrier stack with improved barrier properties
US7192479B2 (en) * 2002-04-17 2007-03-20 Sharp Laboratories Of America, Inc. Laser annealing mask and method for smoothing an annealed surface
US7687917B2 (en) * 2002-05-08 2010-03-30 Nec Electronics Corporation Single damascene structure semiconductor device having silicon-diffused metal wiring layer
US20040224241A1 (en) * 2003-02-03 2004-11-11 Samsung Electronics Co., Ltd. Thin film transistor array panel, manufacturing method thereof, and mask therefor
KR101160823B1 (ko) * 2004-08-24 2012-06-29 삼성전자주식회사 박막 트랜지스터 표시판과 그 제조 방법
TWI285433B (en) * 2005-12-16 2007-08-11 Innolux Display Corp Method of manufacturing thin film transistor substrate
TWI300272B (en) * 2005-12-23 2008-08-21 Innolux Display Corp Method of fabricating tft substrate
KR20080028640A (ko) * 2006-09-27 2008-04-01 삼성전자주식회사 박막 트랜지스터 제조용 마스크, 이에 의해 제조된 박막트랜지스터 기판 및 이를 이용한 박막 트랜지스터 기판의제조방법
TWI339410B (en) * 2008-07-09 2011-03-21 Au Optronics Corp Mask and fabricating method of a polysilicon layer using the same
TWI444758B (zh) * 2009-06-19 2014-07-11 Au Optronics Corp 薄膜電晶體元件與用於定義薄膜電晶體元件之光罩及薄膜電晶體元件之製作方法
CN101598894B (zh) * 2009-07-07 2011-07-27 友达光电股份有限公司 光掩膜、薄膜晶体管元件及制作薄膜晶体管元件的方法
CN202522841U (zh) * 2012-04-20 2012-11-07 京东方科技集团股份有限公司 掩膜版

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101872114B (zh) * 2009-04-24 2012-03-28 中芯国际集成电路制造(上海)有限公司 用于制造金属互连线的掩模板版图
CN102651402A (zh) * 2011-02-24 2012-08-29 三星电子株式会社 布线、薄膜晶体管、薄膜晶体管面板及其制造方法

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