CN103699355A - Variable-order pipeline serial multiply-accumulator - Google Patents
Variable-order pipeline serial multiply-accumulator Download PDFInfo
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- CN103699355A CN103699355A CN201310738598.XA CN201310738598A CN103699355A CN 103699355 A CN103699355 A CN 103699355A CN 201310738598 A CN201310738598 A CN 201310738598A CN 103699355 A CN103699355 A CN 103699355A
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Abstract
The invention relates to a variable-order pipeline serial multiply-accumulator comprising a group of multipliers, three groups of accumulators and corresponding control circuits. The group of multipliers is used for multiplying of two channels of input data and outputting multiplying results. The first group of the three groups of accumulators is used for accumulating the multiplying results, the other two of the three groups of accumulators are used for accumulating pipeline results of the first group of accumulators after the accumulating process of the first group of accumulators, and thus, the first group of accumulators can continue to process data of the next stage. The corresponding control circuits are used for adding extra control signals and control logics and eliminating the head-tail zero padding process of algorithms. The variable-order pipeline serial multiply-accumulator has the advantage that, in application, the head-tail zero padding process of the algorithms and redundant multiplying and accumulating caused by the head-tail zero padding process can be omitted during computing, and accordingly performance index approaching the theoretical estimation can be acquired.
Description
Technical field
The present invention relates to multiply accumulating device, relate in particular to a kind of change rank flowing water serial multiply accumulating device.
Background technology
All the time, Digital Signal Processing, is widely used in all kinds of field of engineering technology as important technological means.In recent years, the development along with scientific and technical, becomes again one of theoretical foundation of the new branch of science such as artificial intelligence, and the popularity of its importance and application is huge.
Mostly the main algorithm that Digital Signal Processing is used is data to carry out filtering, convolution, relevant and analysis of spectrum computing etc.These algorithms have similar framework, i.e. multiply accumulating structure.The N rank FIR wave filter of take is example, and its function expression may be defined as: (filter coefficient is)
Conventionally there is several different methods to realize FIR wave filter, single multiplication serial wave filter for example, serial wave filter, parallelism wave filter and semi-parallelism wave filter based on symmetry coefficient FIR.
General serial filter construction is multiply accumulating structure, only comprises a multiplier and a totalizer can realize, and average flow time is N cycle, as Fig. 1.Parallelism wave filter needs N multiplier, and N-1 totalizer enters into first filtering output from first data, needs N+logN cycle, and flow time is only 1 clk afterwards, as shown in Figure 2.Half parallel wave filter is by parallel architecture and multiply accumulating architecture combined, makes compromise between Area and Speed, so its area and performance also must fall between.
Summary of the invention
The object of the invention is to overcome the deficiency of above prior art, and a kind of change rank flowing water serial multiply accumulating device is provided, and specifically has following technical scheme to realize:
Described change rank flowing water serial multiply accumulating device, comprises
One group of multiplier, for carrying out the multiplication operations of two-way input data, and exports multiplication result;
Three groups of totalizers, first group of totalizer carried out the cumulative of multiplication result, and second group and the 3rd group adds hair device and after cumulative end, the result on first group of totalizer pipelining-stage is added successively, thereby has guaranteed that first group of totalizer can continue to process the data of next stage;
Corresponding control circuit, for increasing extra control signal and steering logic, for saving the head and the tail zero padding operation of algorithm.
The further design of described change rank flowing water serial multiply accumulating device is, described each totalizer and a corresponding connection of data selector.
The further design of described change rank flowing water serial multiply accumulating device is, described corresponding control circuit comprises
Exponent number register, for recording multiply accumulating exponent number, and exports multiply accumulating exponent number;
Counter module, for receiving the enabling signal of multiply accumulating exponent number and multiply accumulating operation, adds up multiply accumulating exponent number, and enabling signal is transmitted;
Four controllers, three controllers are wherein for controlling the gating of described data selector, and a remaining controller is for controlling the output of multiply accumulating device;
Steering logic unit, receives the signal of depositing that comes from the multiply accumulating exponent number of counter module and exponent number register by controller, output multiply accumulating Output rusults and output useful signal.
The further design of described change rank flowing water serial multiply accumulating device is, described data selector is connected with counter module by corresponding controller, makes the gating of the complete paired data selector switch of counter module.
The further design of described change rank flowing water serial multiply accumulating device is, described output useful signal enables input signal as writing of multiply accumulating Output rusults storage.
Advantage of the present invention is as follows:
The realization of change factorial totalizer provided by the invention make can save when computing head and the tail zero padding in algorithm operation and by the unnecessary multiply accumulating of generation, thereby obtain the performance index that approach theoretical calculation.
Accompanying drawing explanation
Fig. 1 is basic multiply accumulating structure.
Fig. 2 is parallel FIR wave filter framework.
Fig. 3 is flowing water serial multiply accumulating device schematic diagram.
Fig. 4 becomes rank flowing water serial multiply accumulating device designed holder composition.
Fig. 5 is the interconnected figure of system emulation basic module.
Embodiment
Below in conjunction with accompanying drawing, the present invention program is elaborated.
The change rank flowing water serial multiply accumulating device that the present embodiment provides, comprises one group of multiplier, three groups of totalizers and corresponding control circuit.One group of multiplier, for carrying out the multiplication operations of two-way input data, and exports multiplication result.Three groups of totalizers, first group of totalizer carried out the cumulative of multiplication result, and second group and the 3rd group adds hair device and after cumulative end, the result on first group of totalizer pipelining-stage is added successively, thereby has guaranteed that first group of totalizer can continue to process the data of next stage.Corresponding control circuit, for increasing extra control signal and steering logic, for saving the head and the tail zero padding operation of algorithm.Each totalizer and a corresponding connection of data selector.
Corresponding control circuit comprises exponent number register, counter module, steering logic unit and four controllers.Exponent number register, for recording multiply accumulating exponent number, and exports multiply accumulating exponent number.Counter module, for receiving the enabling signal of multiply accumulating exponent number and multiply accumulating operation, adds up multiply accumulating exponent number, and enabling signal is transmitted.Four controllers, three controllers are wherein for controlling the gating of data selector, and a remaining controller is for controlling the output of multiply accumulating device.Steering logic unit, receives the signal of depositing that comes from the multiply accumulating exponent number of counter module and exponent number register by controller, output multiply accumulating Output rusults and output useful signal.Data selector is connected with counter module by corresponding controller, makes the gating of the complete paired data selector switch of counter module.
Become rank flowing water serial multiply accumulating device design architecture, referring to Fig. 4.Suppose that the inner flowing water progression of each computing ip is three grades, at output terminal, deposit one-level (consideration timing closure), be equivalent to level Four pipeline.As shown in the figure, start signal is the enabling signal of multiply accumulating operation, and order_mul_accu is for recording the signal of exponent number, din0, din1 is two paths of data input, dout is multiply accumulating Output rusults, wen, for output useful signal, enables input as writing of memory simultaneously.Inside modules mainly comprises a multiplier, three totalizers and each self-corresponding mux, four controll blocks, counter module and depositing signal.Its middle controller 1 ~ 3 is controlled respectively three totalizers mux gating separately, and controller 4 is responsible for output.The input signal of steering logic all comes from the signal of depositing of " count " (counter) and " order_mul_accu ".
In order to verify function and the performance of multiply accumulating module, need other submodule complete systems of collocation, as shown in Figure 5.System mainly comprises: multiply accumulating module, AGU(address generator), memory, top-level module and testbench.
Multiply accumulating module
A single-precision floating point multiplication ip and three addition ip (inside is three grades of flowing water) have been called, design is mainly carried out RTL coding to logics such as four controll blocks, counter, output controls, input signal order_mul_accu and counter is carried out to shift LD simultaneously.
Memory module
First define a submodule, with verilog, write register group, data width 64b, degree of depth 8K.Then at three bank of this submodule exampleization for memory top layer, be respectively used to deposit two-way source data and multiply accumulating result.
AGU module
For special algorithm, for generation of required vector address sequence.Mainly comprise read through model and writing module.Read through model is according to algorithm requirements, address sequence corresponding to design source data, and collocation chip selection signal and read enable signal and send to bank1 and bank2 to peek, the number reading is passed to multiply accumulating module and is carried out computing, i.e. rdata1 and rdata2; Writing module is exported by multiply accumulating device " wen " to control address cumulative, and simultaneously by this address signal, the wen signal of multiply accumulating module, wdata signal are exported to bank3 and are carried out data storage.
Top-level module
By multiply accumulating module, it is interconnected that memory module and AGU module are carried out top layer.
Testbench module
Define clock, reset signal and each parameter of algorithm, data file is imported to the bank1 of memory, bank2 carries out initialization, sends the computing of start signal enabling, after receiving the finish signal of module top layer, finishes emulation.
System testing
Operating system adopts linux system, by VCS simulation validation tool and Design Compiler synthesis tool, carries out functional simulation.
(1) basic module test: carry out the design of multiply accumulating device submodule with multiplicaton addition unit, mainly test each steering logic sequential; Test AGU module, determines whether the address sequence of its generation is expection situation.
(2) integration testing: to specifying memory to import test source operand, generate start signal enabling algorithm by testbench and carry out, transmit each configuration parameter simultaneously.After finishing, algorithm top layer is beamed back finish signal.Operation result obtains by checking corresponding memor, and contrasts with matlab operation result.
(3) DC is comprehensive: further carry out code detection; Whether adopt the 40nm technology library of TSMC to carry out logic synthesis, observing multiply accumulating device module has slack.
In sum, the realization of the change factorial totalizer that the present embodiment provides make can save when computing head and the tail zero padding in algorithm operation and by the unnecessary multiply accumulating of generation, thereby obtain the performance index that approach theoretical calculation.
Claims (5)
1. become a rank flowing water serial multiply accumulating device, it is characterized in that comprising
One group of multiplier, for carrying out the multiplication operations of two-way input data, and exports multiplication result;
Three groups of totalizers, first group of totalizer carried out the cumulative of multiplication result, and second group and the 3rd group adds hair device and after cumulative end, the result on first group of totalizer pipelining-stage is added successively, thereby has guaranteed that first group of totalizer can continue to process the data of next stage;
Corresponding control circuit, for increasing extra control signal and steering logic, for saving the head and the tail zero padding operation of algorithm.
2. change according to claim 1 rank flowing water serial multiply accumulating device, is characterized in that, described each totalizer and a corresponding connection of data selector.
3. change according to claim 2 rank flowing water serial multiply accumulating device, is characterized in that described corresponding control circuit comprises
Exponent number register, for recording multiply accumulating exponent number, and exports multiply accumulating exponent number;
Counter module, for receiving the enabling signal of multiply accumulating exponent number and multiply accumulating operation, adds up multiply accumulating exponent number, and enabling signal is transmitted;
Four controllers, three controllers are wherein for controlling the gating of described data selector, and a remaining controller is for controlling the output of multiply accumulating device;
Steering logic unit, receives the signal of depositing that comes from the multiply accumulating exponent number of counter module and exponent number register by controller, output multiply accumulating Output rusults and output useful signal.
4. change according to claim 3 rank flowing water serial multiply accumulating device, is characterized in that described data selector is connected with counter module by corresponding controller, makes the gating of the complete paired data selector switch of counter module.
5. change according to claim 4 rank flowing water serial multiply accumulating device, is characterized in that, described output useful signal enables input signal as writing of multiply accumulating Output rusults storage.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104504205A (en) * | 2014-12-29 | 2015-04-08 | 南京大学 | Parallelizing two-dimensional division method of symmetrical FIR (Finite Impulse Response) algorithm and hardware structure of parallelizing two-dimensional division method |
| CN106325812A (en) * | 2015-06-15 | 2017-01-11 | 华为技术有限公司 | Processing method and device for multiplication and accumulation operation |
| CN109976707A (en) * | 2019-03-21 | 2019-07-05 | 西南交通大学 | A kind of variable bit width multiplier automatic generating method |
| CN117555515A (en) * | 2024-01-11 | 2024-02-13 | 成都市晶蓉微电子有限公司 | Digital ASIC serial-parallel combined multiplier for balancing performance and area |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104504205A (en) * | 2014-12-29 | 2015-04-08 | 南京大学 | Parallelizing two-dimensional division method of symmetrical FIR (Finite Impulse Response) algorithm and hardware structure of parallelizing two-dimensional division method |
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| CN109976707A (en) * | 2019-03-21 | 2019-07-05 | 西南交通大学 | A kind of variable bit width multiplier automatic generating method |
| CN117555515A (en) * | 2024-01-11 | 2024-02-13 | 成都市晶蓉微电子有限公司 | Digital ASIC serial-parallel combined multiplier for balancing performance and area |
| CN117555515B (en) * | 2024-01-11 | 2024-04-02 | 成都市晶蓉微电子有限公司 | Digital ASIC serial-parallel combined multiplier for balancing performance and area |
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