CN102045078B - FPGA (Field Programmable Gate Array) based software receiver system and implementation method - Google Patents
FPGA (Field Programmable Gate Array) based software receiver system and implementation method Download PDFInfo
- Publication number
- CN102045078B CN102045078B CN 201010567994 CN201010567994A CN102045078B CN 102045078 B CN102045078 B CN 102045078B CN 201010567994 CN201010567994 CN 201010567994 CN 201010567994 A CN201010567994 A CN 201010567994A CN 102045078 B CN102045078 B CN 102045078B
- Authority
- CN
- China
- Prior art keywords
- module
- signal
- dll
- pll
- adopted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000012360 testing method Methods 0.000 claims abstract description 34
- 230000004927 fusion Effects 0.000 claims abstract description 4
- 238000009825 accumulation Methods 0.000 claims description 8
- 238000005070 sampling Methods 0.000 claims description 5
- 238000013481 data capture Methods 0.000 claims description 2
- 238000012545 processing Methods 0.000 abstract description 5
- 238000012795 verification Methods 0.000 abstract description 2
- 230000006870 function Effects 0.000 description 7
- 230000018109 developmental process Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000011161 development Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000033772 system development Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Landscapes
- Logic Circuits (AREA)
- Stored Programmes (AREA)
Abstract
The invention discloses an FPGA (Field Programmable Gate Array) based software receiver system and an implementation method. The system comprises a signal acquisition module, a signal tracking module and a PVT (Process Verification Test) calculating module, wherein the signal acquisition module comprises three FFT (Fast Fourier Transform) modules and a complex conjugate module; and the signal tracking module comprises a PLL (Phase Locked Loop) module and a DLL (Dynamic Link Library) module. The method comprises the following steps of: finishing a data acquisition test of an input signal by the signal acquisition module; finishing a tracking test of the acquired data by the signal tracking module; finishing a calculating test of the data subjected to the tracking test by the PVT calculating module; and finishing the fusion of the signal acquisition module, the signal tracking module and the PVT calculating module by utilizing a clock signal. The reliability of the system is improved, the clock frequency of a CPU (Central Processing Unit) and the byte digit of data processing can be changed within an allowed range, and the flexibility of the system can be greatly improved.
Description
Technical field
The present invention relates generally to the FPGA application of System Generator in software receiver is realized that develop software, and is applicable to the exploitation debugging that the actual software receiver is concrete, is specially a kind of software receiver system based on FPGA and implementation method.
Background technology
Software receiver is realized its signal capture by software and follow the tracks of to be handled, changed traditional receiver structure: radio-frequency front-end, be used for the application-specific integrated circuit (ASIC) (ASIC) that signal handles and the CPU that carries out location compute.With software replacement middle signal processing ASIC circuit, compare with traditional ASIC hardware receiver, software receiver has characteristics such as opening, comprehensive programmability and flexibility, do not needing to change under the prerequisite of hardware, needs by just satisfying different user to adjustment and the upgrading of software module have greatly reduced the required cost of system upgrade.
FPGA can realize complex logic circuit by writing code, and its inside is made up of the logic array of rule on the other hand, so just can develop the special chip of adaptation.In recent years, FPGA closely becomes the core devices of digital information processing system, especially in digital communication, network, video and image applications field.FPGA of today not only comprises look-up table, register, multiplexer, distributed block memory, and has embedded special-purpose mimimum adder, multiplier and input-output apparatus.The more prior FPGA of being has the ability that realizes the high-speed parallel computing, this just makes FPGA become the desirable device of high performance Digital Signal Processing aspect, as at aspects such as digital filtering, fast fourier transform, FPGA has re-programmable advantage, and is more practical than ASIC.
System Generator is that a desirable FPGA develops software, PHPs such as traditional C language are to Hardware Description Language VHDL or Verilog and be unfamiliar with, and finally to convert in the hard-wired process at hardware description language, this just requires the engineer that hardware is had certain understanding, the application of System Generator software can make the problems referred to above be readily solved, for software engineers such as traditional C language provide an excellent development platform.
Summary of the invention
Technology of the present invention is dealt with problems and is: significantly reduced traditional F PGA development difficulty in signal capture, tracking module, strengthened the flexibility of module parameter test, reduced module upgrade or revised cost.With the PVT computing module of System Generator structure fixed function, substituted traditional DSP computing module fully at last.
Technical solution of the present invention is: a kind of software receiver system based on FPGA, resolve module and form by signal capture module, signal trace module, PVT, wherein the signal capture module comprises 3 FFT modules and a complex conjugate module, and the signal trace module comprises PLL module and DLL module; The input termination front end input signal of the one FFT module, the input termination local code input signal of the 2nd FFT module, connect the input of the 3rd FFT module after the output serial connection complex conjugate module of the 2nd FFT module respectively with the output of a FFT module, the output of the 3rd FFT module connects the input that PVT resolves module after being connected in series PLL module and DLL module respectively.
A kind of implementation method of the software receiver system based on FPGA may further comprise the steps:
(1) signal capture module is finished the data capture test of input signal;
(2) signal trace module is finished the tracking and testing of step (1) being caught data;
(3) PVT resolves module, finishes the test of resolving to the data behind step (2) tracking and testing;
(4) utilize clock signal to finish the fusion that signal capture module, signal trace module, PVT are resolved module.
The signal capture module has adopted the FFT module in the storehouse among the System Generator in the described step (1), and the sampling number of setting is 1024 ~ 16384, and corresponding clock frequency is the integral multiple of sampling number inverse; The plural number module is built by System Generator basic module; Local code generates the LUT look-up table mode that mainly adopted.
The PLL phase discriminator has adopted I road and Q road product in described step (2) the signal trace module,-30
0~ 30
0Be linearisation in the scope; The DLL phase discriminator has mainly adopted
, E and L represent integral accumulation after the related operation of sign indicating number early and the integral accumulation after the sign indicating number related operation late respectively; The NCO module has mainly adopted the LUT look-up table to finish, and tabling look-up as offset address with the NCO input obtains corresponding output; Filter order is chosen as 2 ~ 3.
In steps the data test in (1) to (3) all adopted FromWorkspace module in the Simulink platform, concrete array is modeled to concrete signal tests.
The present invention's advantage compared with prior art is:
(1) greatly reduce the FPGA development difficulty, traditional existing technology realizes developing based on substrate HDL substantially, but on signal was handled, difficulty was very big.The application of System Generator has significantly reduced development difficulty, especially at aspects such as digital filtering, fast fourier transform, NCO.Improved system development efficient.
(2) introduced the LUT(look-up table) technology, utilize address lookup memory space technology to replace traditional mathematical operation, improved system speed greatly, for system real time has been laid good basis.
(3) system development is near concrete theoretical model, and the procedural model that System Generator exploitation is built all is based on corresponding theoretical model, and about the same, can carry out system testing etc. so very bluntly.
(4) the PVT computing module that makes up with System Generator has replaced DSP, has realized the parallel work-flow of calculating, and has improved arithmetic speed.And can carry out the setting of data store byte figure place simultaneously, improved flexibility and the space availability ratio of this computing module greatly.
Description of drawings
Fig. 1 is system construction drawing of the present invention.
Fig. 2 is the trapping module structural representation of system.
Fig. 3 is the PLL of system modular structure schematic diagram.
Fig. 4 is the DLL of system modular structure schematic diagram.
Embodiment
Core concept of the present invention is to adopt the FPGA System Generator that develops software, and according to from simple to complexity, carries out system's programming from bottom to the upper strata thinking according to Theoretical Framework, and specific implementation method is as follows:
1 at first be familiar with developing software System Generator each carry parameter and the performance index of module, as FFT module, Postponement module, input/output module etc.
2 carry out algorithm according to theoretical acquisition algorithm structure with System Generator realizes, test with concrete data, adopt the FromWorkspace module in the Simulink platform to simulate actual signal with concrete array, a function that module is likened in the software development such as C language carries out data test.Like this can be to finishing the contrast verification of module.
3 carry out algorithm according to theoretical track algorithm structure with System Generator realizes, finish the independent programming of PLL and DLL respectively, test mainly is divided into the NCO test, the test of PLL phase discriminator, the test of DLL phase discriminator, filters to test, the method for test also are to utilize FromWorkspace module in the Simulink platform that a certain concrete array in the platform is modeled to actual signal to test, and are similar to the function test in the C language.
4 usefulness System Generator construct concrete PVT and calculate CPU, according to concrete theoretical formula, finish the structure of system, mainly finish the mathematical operation function, can work done in the manner of a certain author become simple fixation computing function CPU to test, the also test of the function in similar and the C language.FromWorkspace module in the same employing Simulink platform is come simulation test.
5 last main 3 standalone modules to system carry out fusion treatment, comprise the consistency of utilizing clock signal to coordinate each module.Finish last test and analysis with actual signal at last.
Concrete scheme is as follows:
Referring to Fig. 1, a kind of software receiver system based on FPGA of the present invention, resolved module and formed by signal capture module, signal trace module, PVT, wherein the signal capture module comprises 3 FFT modules and a complex conjugate module, and the signal trace module comprises PLL module and DLL module; The input termination front end input signal of the one FFT module, the input termination local code input signal of the 2nd FFT module, connect the input of the 3rd FFT module after the output serial connection complex conjugate module of the 2nd FFT module respectively with the output of a FFT module, the output of the 3rd FFT module connects the input that PVT resolves module after being connected in series PLL module and DLL module respectively.
The inventive method comprises the steps:
(1) makes up the acquisition algorithm module with System Generator
Referring to Fig. 2, be input as the digital medium-frequency signal of front end output, local source mainly is divided into local carrier and local pseudo noise code, module mainly is made up of 3 FFT modules, wherein finish the FFT function for 2, last finishes the IFFT function, the FFT module is the FFT module among the DSP that adopts among the Xilinx Blockset, concrete sampling number can be set to 8 ~ 65536, arrange according to concrete precision needs (also depending on the front end data form simultaneously), take advantage of basic module to build complex multiplication module with the plus-minus among the System Generator at last, concrete figure place can freely arrange.
(2) make up the acquisition and tracking module with System Generator, the concrete steps of this method are:
(a) design PLL(Phase lock loop), referring to Fig. 3, mainly by the PLL phase discriminator, filter, NCO(digital controlled oscillator) form.Wherein the PLL phase discriminator does not adopt accurate Costas phase discriminator, has adopted I road and Q road product, though phase discriminator is only-30
0~ 30
0Linearisation, but can on FPGA, realize easily.Filter can be selected 2 rank or 3 rank, and the result produces corresponding phase error.Input as the NCO module.The NCO module has mainly adopted the LUT(look-up table) finish.Table look-up as offset address with NCO input and to obtain corresponding output.
(b) design DLL(Delay lock loop), referring to Fig. 4, this loop is divided into 3 the tunnel, mainly by the DLL phase discriminator, filter, NCO(digital controlled oscillator) form, wherein the DLL phase discriminator has mainly adopted
, E and L represent integral accumulation after the related operation of sign indicating number early and the integral accumulation after the sign indicating number related operation late respectively, are conducive to FPGA like this and realize, and be similar in filter and NCO structure and the PLL loop design.Wherein 3 road C/A generate also by the LUT(look-up table in this link) realize.
(3) make up the PVT computing module with System Generator, existing most DSP of employing carries out PVT and calculates, in the present invention, having adopted System Generator self-control CPU to finish last PVT calculates, corresponding clock frequency can be regulated in allowed band, the ready-made multiplier and the abundant memory space that utilize FPGA to carry, wherein some multiplication link has adopted parallel processing, has significantly reduced operation time like this.Simultaneously, in the whole process of calculating, the byte figure place of data can be adjusted, and has saved the space greatly.
The principle of the invention is: the basic module that carries by the System Generator that develops software, form signal capture module, tracking module and PVT computing module, with the software receiver through engineering approaches, finish the whole system actual implementation by independent establishment, the test of each module.Carry out co-ordination between each module by the clock resource of system simultaneously.The basic module that System Generator carries can upgrade, and also can generate with substrate oneself, and this optimizes for whole receiver system upgrading provides convenience.
Claims (4)
1. software receiver system based on FPGA, it is characterized in that: resolve module and form by signal capture module, signal trace module, PVT, wherein the signal capture module comprises 3 FFT modules and a complex conjugate module, and the signal trace module comprises PLL module and DLL module; The input termination front end input signal of the one FFT module, the input termination local code input signal of the 2nd FFT module, connect the input of the 3rd FFT module after the output serial connection complex conjugate module of the 2nd FFT module respectively with the output of a FFT module, the output of the 3rd FFT module connects the input that PVT resolves module after being connected in series PLL module and DLL module respectively; Wherein the PLL module is made up of PLL phase discriminator, filter, NCO, and the PLL phase discriminator has adopted I road and Q road product, is linearisation in-30 °～30 ° scopes; The DLL module is made up of DLL phase discriminator, filter, NCO, and the DLL phase discriminator has adopted
E and L represent integral accumulation after the related operation of sign indicating number early and the integral accumulation after the sign indicating number related operation late respectively; The NCO module has adopted the LUT look-up table to finish, and tabling look-up as offset address with the NCO input obtains corresponding output; Filter order is chosen as 2～3.
2. implementation method based on the software receiver system of FPGA is characterized in that may further comprise the steps:
(1) signal capture module is finished the data capture test of input signal;
(2) signal trace module is finished the tracking and testing of step (1) being caught data; Described signal trace module comprises PLL module and DLL module; Wherein the PLL module is made up of PLL phase discriminator, filter, NCO, and the PLL phase discriminator has adopted I road and Q road product, is linearisation in-30 °～30 ° scopes; The DLL module is made up of DLL phase discriminator, filter, NCO, and the DLL phase discriminator has adopted
E and L represent integral accumulation after the related operation of sign indicating number early and the integral accumulation after the sign indicating number related operation late respectively; The NCO module has adopted the LUT look-up table to finish, and tabling look-up as offset address with the NCO input obtains corresponding output; Filter order is chosen as 2～3;
(3) PVT resolves module, finishes the test of resolving to the data behind step (2) tracking and testing;
(4) utilize clock signal to finish the fusion that signal capture module, signal trace module, PVT are resolved module.
3. the implementation method of a kind of software receiver system based on FPGA according to claim 2, it is characterized in that the signal capture module has adopted the FFT module in the storehouse among the System Generator in the described step (1), the sampling number that arranges is 1024～16384, and corresponding clock frequency is the integral multiple of sampling number inverse; The plural number module is built by System Generator basic module; Local code generates the LUT look-up table mode that adopted.
4. the implementation method of a kind of software receiver system based on FPGA according to claim 2, it is characterized in that in steps the data test in (1) to (3) all adopted FromWorkspace module in the Simulink platform, concrete array is modeled to concrete signal tests.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010567994 CN102045078B (en) | 2010-12-01 | 2010-12-01 | FPGA (Field Programmable Gate Array) based software receiver system and implementation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010567994 CN102045078B (en) | 2010-12-01 | 2010-12-01 | FPGA (Field Programmable Gate Array) based software receiver system and implementation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102045078A CN102045078A (en) | 2011-05-04 |
| CN102045078B true CN102045078B (en) | 2013-07-03 |
Family
ID=43910922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010567994 Expired - Fee Related CN102045078B (en) | 2010-12-01 | 2010-12-01 | FPGA (Field Programmable Gate Array) based software receiver system and implementation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102045078B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106027047B (en) * | 2016-05-18 | 2019-01-22 | 中国电子科技集团公司第四十一研究所 | The Linearization Method of non-linear analog/digital conversion based on FPGA control |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007118327A1 (en) * | 2006-04-18 | 2007-10-25 | Sige Semiconductor Inc. | Methods and systems for shared software and hardware correlators |
| CN101320084A (en) * | 2008-06-25 | 2008-12-10 | 中国科学院上海技术物理研究所 | Real-time processing method of satellite positioning signal |
| CN101762818A (en) * | 2009-12-11 | 2010-06-30 | 东南大学 | GPS software receiver baseband signal real-time tracking method based on code memory |
-
2010
- 2010-12-01 CN CN 201010567994 patent/CN102045078B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007118327A1 (en) * | 2006-04-18 | 2007-10-25 | Sige Semiconductor Inc. | Methods and systems for shared software and hardware correlators |
| CN101320084A (en) * | 2008-06-25 | 2008-12-10 | 中国科学院上海技术物理研究所 | Real-time processing method of satellite positioning signal |
| CN101762818A (en) * | 2009-12-11 | 2010-06-30 | 东南大学 | GPS software receiver baseband signal real-time tracking method based on code memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102045078A (en) | 2011-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105915241A (en) | Method and system for realizing ultrahigh-speed digital orthogonal down conversion and decimation filtering in FPGA | |
| CN105262503B (en) | A kind of multidiameter delay generation device and method based on group delay calibration | |
| CN102789512B (en) | Method and device for design of electronic design automation (EDA) tool of multi-field programmable gate array (FPGA) system | |
| CN103178815B (en) | Pulse wavelength modulation (PWM) generator based on field programmable gate array (FPGA) | |
| Patel et al. | VHDL implementation of UART with status register | |
| CN1996975A (en) | A signal measurement device, system and method | |
| CN107819456B (en) | High-precision delay generator based on FPGA carry chain | |
| US9553600B1 (en) | Skew detection and correction in time-interleaved analog-to-digital converters | |
| CN105553443A (en) | Weak signal extraction and digital processing system under strong noise condition | |
| CN102006069A (en) | Multichannel parallel high-speed A/D sampling circuit board based on low cost | |
| CN105701294B (en) | Realize the method and system of chip complex engineering modification | |
| CN204989893U (en) | Small signal draws and digital process system under very noisy condition | |
| CN104375006A (en) | Rapid synchronous phasor correction method | |
| CN102565751A (en) | Device for developing programmable single-phase electric energy metering chip | |
| CN107169244A (en) | A kind of electromechanical electromagnetic transient hybrid simulation interface system and method | |
| CN206060731U (en) | Multichannel digital signal processing platform | |
| CN103944660A (en) | Clock synchronization device and method | |
| CN101777939A (en) | DDS-based Doppler compensation device in real-time water sound communication | |
| CN102364456A (en) | 64-point fast Fourier transform (FFT) calculator | |
| CN102045078B (en) | FPGA (Field Programmable Gate Array) based software receiver system and implementation method | |
| CN104113304A (en) | Two-phase mutually non-overlap clock circuit and method thereof | |
| CN103837878A (en) | Method for acquiring GNSS satellite signal | |
| CN101834818B (en) | GMSK (Guassian Minimum Shift Keying) modulation device and method | |
| CN105306058A (en) | High-speed digital signal acquisition system based on clock phase modulation | |
| US10924096B1 (en) | Circuit and method for dynamic clock skew compensation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130703 |