CN103681360A - 封装器件及方法 - Google Patents

封装器件及方法 Download PDF

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Publication number
CN103681360A
CN103681360A CN201310024373.8A CN201310024373A CN103681360A CN 103681360 A CN103681360 A CN 103681360A CN 201310024373 A CN201310024373 A CN 201310024373A CN 103681360 A CN103681360 A CN 103681360A
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China
Prior art keywords
tsv
substrate
intermediary
conducting sphere
expose portion
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CN201310024373.8A
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English (en)
Inventor
梁世纬
吴凯强
何明哲
吴逸文
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN103681360A publication Critical patent/CN103681360A/zh
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Abstract

公开了封装器件和封装方法。在一些实施例中，一种制造封装器件的方法包括在中介衬底中形成多个衬底通孔(TSV)。使中介衬底凹陷或者增加多个TSV的厚度以暴露出多个TSV的一部分。将导电球连接到多个TSV中的每一个TSV的暴露部分。

Description

封装器件及方法
技术领域
本发明涉及封装器件及其制造方法和封装方法。
背景技术
半导体器件用在各种电子应用中，举例来说，诸如个人电脑、手机、数码相机以及其他电子设备。通常通过在半导体衬底上方相继沉积材料的绝缘层或介电层、导电层以及半导体层并且使用光刻图案化各种材料层以在其上形成电路部件和元件来制造半导体器件。
半导体行业通过不断减小最小部件尺寸，从而使得更多部件被集成到给定面积上，进而不断提高各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度。在一些应用中，这些更小的电子元件也需要比过去的封装件更小的利用更少面积的封装件。
近来已开发出来的一种用于半导体器件的更小型封装技术是堆叠式封装(PoP)器件，其中将两个或多个集成电路管芯单独封装并且在单个PoP器件中将封装的集成电路管芯连接到一起。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种制造封装器件的方法，所述方法包括：在中介衬底中形成多个衬底通孔(TSV)；使所述中介衬底凹陷或者增加所述多个TSV的厚度以暴露出所述多个TSV的一部分；以及将导电球连接到所述多个TSV中的每一个TSV的暴露部分。
在所述的方法中，将所述导电球连接到所述多个TSV中的每一个TSV的暴露部分包括：使用落球工艺将所述导电球接合到所述多个TSV中的每一个TSV的暴露部分，以及回流所述导电球的共晶材料。
在所述的方法中，将所述导电球连接到所述多个TSV中的每一个TSV的暴露部分包括：在所述中介衬底和所述多个TSV的暴露部分上方形成在模板材料内设置的导电膏，去除所述模板材料以及回流所述导电膏的共晶材料。在一个实施例中，形成在所述模板材料内设置的导电膏包括形成模板材料，所述模板材料包含选自基本上由聚合物、钢、Al合金、Mg合金以及它们的组合所组成的组中的材料。
在所述的方法中，增加所述多个TSV的厚度包括选自基本上由镀层工艺、沉积工艺以及它们的组合所组成的组中的方法。
在所述的方法中，连接所述导电球包括将一个所述导电球连接至多个所述TSV。
在所述的方法中，连接所述导电球包括将一个所述导电球连接至所述多个TSV中的每一个TSV。
根据本发明的另一方面，提供了一种封装器件，包括：中介衬底；多个衬底通孔(TSV)，设置在所述中介衬底中，其中所述中介衬底被凹陷至所述多个TSV顶面的下方；以及导电球，与所述多个TSV的每一个TSV连接。
在所述的封装器件中，与所述多个TSV连接的导电球设置在所述中介衬底的第一面上，所述封装器件进一步包括设置在所述中介衬底的第二面上的再分配层(RDL)，并且所述RDL包括设置在其表面上的多个接触件。所述的封装器件进一步包括：与所述RDL的多个接触件中的每一个接触件连接的导电凸块。在一个实施例中，所述导电凸块包括可控塌陷芯片连接(C4)凸块。
在所述的封装器件中，所述导电球包括焊料球。
在所述的封装器件中，所述TSV包括从所述中介衬底的顶面伸出约10至20μm的暴露TSV(eTSV)。
根据本发明的又一方面，提供了一种将多个焊料球连接到封装衬底的方法，所述方法包括：提供所述封装衬底，所述封装衬底包括中介衬底和设置在所述中介衬底内的多个衬底通孔(TSV)；使所述中介衬底凹陷或者增加所述多个TSV的厚度以暴露出所述多个TSV的一部分；在所述多个TSV的暴露部分上方形成晶种层；以及将焊料球连接到位于所述多个TSV中的每一个TSV的暴露部分上方的晶种层。
在所述的方法中，形成所述晶种层包括形成选自基本上由Ti、Cu、Ni和它们的组合所组成的组中的材料。
在所述的方法中，形成所述晶种层包括：在所述多个TSV的暴露部分上方以及在所述中介衬底的表面上方形成第一层，以及在所述第一层上方形成第二层。所述的方法进一步包括：在将所述焊料球连接到位于所述多个TSV中的每一个TSV的暴露部分上方的晶种层之后，从所述中介衬底上方去除所述晶种层。在一个实施例中，从所述中介衬底上方去除所述晶种层包括使用所述焊料球作为蚀刻掩模蚀刻所述晶种层。
在所述的方法中，在所述多个TSV的暴露部分上方形成所述晶种层包括将所述晶种层镀到所述多个TSV的暴露部分上。
在所述的方法中，使所述中介衬底凹陷包括选自基本上由蚀刻工艺、化学机械抛光(CMP)工艺以及它们的组合所组成的组中的方法。
附图说明
为更充分地理解本发明及其优点，现在将结合附图所作的以下描述作为参考，其中：
图1至图6是根据本发明的一些实施例在示出制造封装器件的方法的各个制造阶段中的封装器件的截面图；
图7是根据其他实施例示出制造封装器件的方法的封装器件的截面图；
图8至图10是根据其他实施例示出制造封装器件的方法的各个阶段的封装器件的截面图；
图11是根据一些实施例制造封装器件的方法的流程图；
图12和图13是示出将集成电路管芯接合到本文所描述的封装器件的方法的截面图；以及
图14和图15是根据一些实施例示出在PoP器件中使用本文所描述的封装器件的方法的截面图。
除非另有说明，不同附图中相应的编号和符号通常指相应的部件。绘制附图以便清楚地示出实施例的相关方面并且不必按比例绘制。
具体实施方式
以下详细描述本发明实施例的制造和使用。然而，应该理解，本发明提供许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例仅仅是制造和使用本发明的示例性具体方式，而不用于限制本发明的范围。
本发明的实施例涉及用于半导体器件的封装器件和方法。本文将描述新的封装方法、器件以及将焊料球连接至封装衬底的方法。
图1至图6是根据本发明的一些实施例示出制造封装器件100的方法的各个制造阶段的封装器件100的截面图。
用于封装器件100的制造方法包括首先提供中介衬底102。注意，每幅附图中仅包括一个封装器件100；然而，可以在中介衬底102的整个表面上同时形成多个封装器件100，之后在制造工艺流程中分离(singulate)单独的封装器件100。
如图1所示，中介衬底102包括在其中形成的多个衬底通孔(TSV)104。TSV104是导电的并且提供中介衬底102的第一面106与中介衬底102的第二面108的电连接，其中第二面108与第一面106相反。TSV104为封装器件100提供垂直连接。例如，中介衬底102可以包含硅或其他半导电材料。可选地，中介衬底102可以包含其他材料。
通过图案化或者钻孔得到完全穿过中介衬底102的多个孔或口，并且用导电材料填充孔来形成TSV 104。作为实例，在一些实施例中，在一面上形成部分穿过中介衬底102的孔，用导电材料填充孔，以及减薄中介衬底102的相反面直至到达TSV 104从而使得TSV 104完全延伸穿过中介衬底102。可选地，可以使用其他方法在中介衬底102中形成TSV 104。
在一些实施例中，TSV 104可以包括一层或多层衬层以及填充材料(未在图中示出)。作为实例，TSV 104可以包括包含Ta、TaN、Ti、TiN、其他材料或者这些的组合或多层的一层或多层衬层。在一些实施例中，衬层可以包括Ta/TaN或者Ti/TiN的双层。例如，TSV 104可以包括设置在(一层或多层)衬层上方的包含Cu的填充材料。可选地，TSV 104可以包括其他材料并且可以不包括衬层。在一些实施例中，例如，在沉积或形成(一层或多层)衬层和填充材料之前，在用于形成TSV 104的孔的侧壁上形成包含绝缘材料的衬层。在其他实施例中，中介衬底102中不包括绝缘衬层。作为实例，在中介衬底102的俯视图中，TSV 104的直径为约10至20μm，但是可选地，TSV 104可以具有其他尺寸。
如图2所示，在中介衬底102的第二面108上方形成再分配层(RDL)110。RDL 110包括设置在绝缘材料114内的引线112。作为实例，引线112包括多条诸如Cu、Al、其他金属或者它们的多层或组合的导电材料的迹线。作为实例，绝缘材料114包括二氧化硅、氮化硅、其他绝缘体或它们的多层或组合。可选地，引线112和绝缘材料114可以包括其他材料。将至少一些引线112连接至TSV 104从而为封装器件100的第二面108提供电连接。例如，在一些实施例中，部分引线112可以包括用于封装器件100电连接的引线的扇出区。
RDL 110包括设置在其表面上的多个接触件120。接触件120包括第一导电材料116和设置在第一导电材料116上方的第二导电材料118。在一些实施例中，第一导电材料116包括Cu，第二导电材料118包括Sn。可选地，接触件120、第一导电材料116和第二导电材料118可以包括其他材料。在一些实施例中不包括第二导电材料118。通过绝缘材料114将至少一些接触件120连接至RDL 110的引线112。RDL 110为封装器件100提供水平连接。
作为实例，可以使用金属蚀刻技术(subtractive etch technique)、镶嵌技术和/或其他方法形成RDL110的各个部分，即RDL110的引线112、绝缘材料114以及接触件120。
根据本发明的一些实施例，如图3所示，使中介衬底102凹陷以暴露出多个TSV 104的部分122。作为实例，TSV 104的部分122在本文中也被称为顶部122和暴露部分122。例如，将中介衬底102反转从而使得第一面106面朝上，使用蚀刻工艺来去除中介衬底102顶面的一部分并暴露出TSV 104的顶部122。在其他实施例中，使用化学机械抛光(CMP)工艺来去除中介衬底102顶面的一部分，从而暴露出TSV 104的顶部122。例如，还可以使用蚀刻工艺和CMP工艺的组合来使中介衬底102凹陷以暴露出多个TSV 104的部分122。
在其他实施例中，增加TSV 104的厚度从而使中介衬底102的顶面凹陷至TSV 104的顶面下方。例如，可以通过镀层工艺增加TSV 104的厚度。最初，TSV 104的顶面123可以基本上与中介衬底102的顶面共面，如图3中的虚线所示。将诸如Cu的导电材料镀到最初的共面顶面123上以形成远离中介衬底102的顶面向上延伸的TSV 104的部分122。在镀层工艺中，将导电材料镀到导电TSV 104上，但不镀到中介衬底102的顶面上。在其他实施例中，使用沉积工艺增加TSV 104的厚度。例如，可以在中介衬底102的第一面106上方沉积另外的导电材料，并且可以使用光刻或者直接图案化方法图案化导电材料以从中介衬底102的第一面106的顶面去除导电材料，留下位于TSV 104上方的导电材料并且增加TSV 104的厚度，从而使得TSV 104的顶部暴露部分122远离中介衬底102的顶面向上延伸。还可以使用沉积方法和镀层方法的组合以使在中介衬底102的第一面106上方暴露出TSV 104的顶部122。可选地，可以使用其他方法增加TSV 104的厚度。
例如，在一些实施例中，使用本文所描述的一种或多种方法来增加TSV104的厚度并且还使中介衬底102凹陷以暴露出TSV 104的顶部122。
在使中介衬底102凹陷和/或增加多个TSV 104的厚度之后，TSV 104的暴露部分122远离中介衬底102的顶面延伸具有尺寸d1的量，其中作为实例，d1为约10至20μm。举例来说，在一些实施例中，尺寸d1为约30μm或更小。可选地，作为实例，根据各种因素诸如特定应用、导电球140(未在图3中示出；见图5)的期望尺寸或者期望的焊点互连高度(stand-offheight)(例如，导电球140最终接合到终端应用中远离表面的高度)以及其他因素，尺寸d1可以包含其他值。例如，尺寸d1还表示中介衬底102的顶面凹陷至TSV 104的暴露部分122顶面下方的量。作为另一实例，在一些实施例中，TSV 104包括具有从中介衬底102的表面伸出尺寸d1的端部的暴露TSV(eTSV)，其中尺寸d1为约10至20μm。
然后如图4所示，在TSV 104的暴露部分122上方以及在中介衬底102的第一面106的顶面上方形成晶种层130。注意，在晶种层130形成在TSV104的暴露部分122上方之后，TSV 104实际上不再暴露；而是TSV 104被晶种层130覆盖。然而，为了使本文的论述一致，在本发明的下文中继续将TSV 104的暴露部分122称为“暴露部分122”，因为它们在先前的制造工艺步骤中被暴露出来。
在一些实施例中，如图4所示，晶种层130包括两层：第一层126和设置在第一层126上方的第二层128。作为实例，在一些实施例中，第一层126包含约1,000埃至3,000埃的Ti，第二层128包含约5,000埃至10,000埃的Cu。可选地，晶种层130的第一层126和第二层128可以包含其他材料和尺寸。作为实例，晶种层130可以可选地包括单材料层或者三层或更多的材料层。在一些实施例中，使用溅射工艺形成晶种层130的一层或多层126或128。可以可选地使用其他方法形成晶种层130。例如，在一些实施例中，晶种层130在中介衬底102的顶面上方基本上是共形的并且符合TSV 104的暴露部分122的形貌。可选地，晶种层130可以是非共形的(未在图中示出)。注意，为了简化附图，在本文后面的附图中晶种层130以单层示出。
然后如图5所示，在TSV 104的暴露部分122上方的晶种层130的上方形成多个导电球140。例如，使用落球工艺(ball drop process)将导电球140连接到位于TSV 104的暴露部分122上方的晶种层130。作为实例，可以使用直接落球工艺，但是可选地，可以使用其他方法将导电球140连接到位于TSV 104的暴露部分122上方的晶种层130。例如，在一些实施例中，导电球140包含诸如焊料的共晶材料。导电球140在本文中(例如在一些权利要求中)也被称为焊料球。导电球140可以可选地包含其他材料、其他共晶材料或者这些的多层或组合。然后通过升高温度至共晶材料的共晶点来回流导电球140的共晶材料，从而将导电球140接合到位于TSV 104的暴露部分122上方的晶种层130。例如，在导电球140包含焊料的实施例中，可以将导电球140的焊接材料升高到约260℃的峰值温度。可选地，回流工艺可以包含其他温度。
如图6所示，在将导电球140连接到位于TSV 104的暴露部分122上方的晶种层130之后，从中介衬底102的顶面上方去除晶种层130。有利的是，在一些实施例中，导电球140用作蚀刻掩模来去除晶种层130，从而不需要光刻工艺来去除晶种层130。例如，在一些实施例中，在蚀刻工艺期间采用蚀刻工艺使用导电球140作为蚀刻掩模来蚀刻晶种层130。
在图1至图6示出的实施例中，使用落球工艺将导电球140连接到中介衬底102。根据本发明的其他实施例，如图7所示，以及还如图9所示，使用导电膏152形成导电球140。
图7是根据其他实施例示出制造封装器件100的方法的封装器件100的截面图。在如图4所示形成晶种层130之后，如图7所示，在晶种层130的上方形成在模板材料(stencil material)150内设置的导电膏152。作为实例，在一些实施例中，导电膏152包括焊膏。在一些实施例中，模板材料150包括聚合物、钢、Al合金、Mg合金或它们的多层或组合。可选地，模板材料150和导电膏152可以包括其他材料。模板材料150和导电膏152的厚度为尺寸d2，在一些实施例中，尺寸d2为约60至100μm。可选地，模板材料150和导电膏152的尺寸d2可以包含其他材料和尺寸。例如，模板材料150包括牺牲材料并且适合于控制导电膏152的形状和图案。
将模板材料150去除，并且使导电膏152经受回流工艺以引起导电膏152的共晶材料回流并且在TSV 104的暴露部分122上方(例如，在暴露部分122上方的晶种层130的上方)形成导电球140，得到图5所示的结构。在一些实施例中，在用于另一批次的封装器件100的后续制造工艺中可以重复使用模板材料150。可选地，可以丢弃模板材料150。在一些实施例中，在导电膏152的回流工艺期间去除模板材料150。在其他实施例中，使用单独的蚀刻工艺或去除工艺来去除模板材料150。然后，如先前的实施例所述的以及如图6所示，使用导电球140作为蚀刻掩模从中介衬底102的顶面上方去除晶种层130。
图8至图10是根据其他实施例示出制造封装器件100的方法的各个阶段的封装器件100的截面图。不是如本文先前描述的实施例在中介衬底102的整个表面上方形成覆盖晶种层130，在如图3所示使中介衬底102凹陷和/或增加TSV 104的厚度之后，如图8所示将晶种层130’镀到TSV 104的暴露部分122上。镀层工艺使得晶种层130’只形成在TSV 104的暴露部分122的上方。晶种层130’未形成在中介衬底102的顶面上方。作为实例，在一些实施例中，晶种层130’包含约10至20μm的Cu或Ni，但是可选地，晶种层130’可以包括其他尺寸和材料。例如，在一些实施例中，用于形成晶种层130’的镀层工艺可以包括化学镀工艺。可选地，其他类型的镀层工艺可以用于形成镀上的晶种层(plated-on seed layer)130’。
如图9所示，在晶种层130’上方形成在模板材料150内设置的导电膏152。使用回流工艺来回流导电膏152的共晶材料并形成导电球140，如图10所示，然后去除模板材料150。有利的是，在这些实施例中不需要单独的蚀刻工艺来从中介衬底102的顶面上方去除过量的晶种层130’。
在其他实施例中，在如图8所示将晶种层130’镀到TSV 104的暴露部分122上之后，如图10所示，使用直接落球工艺将导电球140连接到位于TSV 104的暴露部分122上方的晶种层130’。
图11是根据一些实施例制造封装器件100的方法的流程图160。在步骤162中，在中介衬底102中形成TSV 104。在步骤164中，使中介衬底102凹陷以暴露出TSV 104的部分122。在步骤166中，将焊料球140连接到TSV 104的暴露部分122。
图12和图13是示出将集成电路管芯172接合到本文所描述的封装器件100的方法的截面图。在使用本文参考图1至图10所描述的方法在TSV104的部分122上形成导电球140之后，如图12所示，在位于中介衬底102的第二面108上的每一个接触件120上形成导电凸块170。举例来说，通过倒装芯片工艺形成导电凸块170，其中将导电凸块170接合到另一管芯并且由另一管芯中得到导电凸块170，以及使用回流工艺将导电凸块170与接触件120连接。可选地，可以使用其他方法形成导电凸块170。例如，在一些实施例中，导电凸块170包括可控塌陷芯片连接(C4)凸块。在一些实施例中，导电凸块170包含焊料。可选地，导电凸块170可以包含其他类型的连接和材料。
然后将集成电路管芯172连接到封装器件100上的导电凸块170，从而形成封装后半导体器件176，如图13所示。将集成电路管芯172上的接触件174与封装器件100上的导电凸块170对准，并且靠着导电凸块170放置接触件174。例如，使用回流工艺将导电凸块170接合到集成电路管芯172上的接触件174。在一些实施例中，可以将底部填充材料(未示出)分配到管芯172和封装器件100之间，例如导电凸块170之间。在一些实施例中，通过将导电凸块140连接到衬底、印刷电路板(PCB)、支撑件或者其他物件，封装后半导体器件176可以用于终端应用。
在一些实施例中，可以将封装后半导体器件176连接到另一封装后半导体器件178以形成PoP器件198，如图14所示，图14是示出在PoP器件198中使用本文所描述的封装器件100的方法的PoP器件198的一部分的截面图。包含本文所描述的新封装器件100的封装后半导体器件176包括第一封装后半导体器件或者底部封装后半导体器件。例如，将封装后半导体器件176连接到包括第二封装后半导体器件或者顶部封装后半导体器件的另一封装后半导体器件178。通过设置在封装后半导体器件176和178的周边的多个焊接头184将封装后半导体器件176和178连接到一起。设置在封装后半导体器件176和178之间的焊接头184被布置成一行或多行。如本文中先前描述的，底部封装后半导体器件176包括连接到导电凸块170的集成电路管芯172a。顶部封装后半导体器件178包括集成电路管芯172b。顶部封装后半导体器件178的封装件182包括设置在其底面周边附近的多个接触件180。焊接头184将顶部封装后半导体器件178上的接触件180连接到底部封装后半导体器件176上的接触件120。
在图15中以截面图示出实施本文所描述的新封装器件100的PoP器件198的详视图。在形成焊接头184(例如在底部封装后半导体器件176和顶部封装后半导体器件178之间形成)之后，在封装器件100上方设置包含绝缘材料的模塑料186。在一些实施例中，PoP器件198中不包括模塑料186。
示出顶部封装后半导体器件178的另一实例，其包括垂直堆叠在封装件182上方的两个集成电路管芯172b和172c。可选地，在顶部封装后半导体器件178中可以仅包括一个集成电路管芯172b或172c。封装件182包括衬底190和在衬底中形成的多个TSV 188，TSV 188为顶部封装后半导体器件178提供垂直连接。封装件182包括位于其底面上的第一RDL 192a和位于其顶面上的第二RDL 192b。RDL 192a和RDL 192b为顶部封装后半导体器件178提供水平连接。将集成电路管芯172b接合到封装件182的顶面。焊线194a将封装件182上的接合焊盘与集成电路管芯172b上的接合焊盘连接起来。将集成电路管芯172c接合到集成电路管芯172b的顶面。焊线194b将封装件182上的接合焊盘与集成电路管芯172c上的接合焊盘连接起来。在集成电路管芯172c和封装件182的暴露部分的上方形成模塑料196。例如，模塑料196包括保护焊线194a和194b的绝缘材料。
举例来说，在一些实施例中，使用倒装芯片晶圆级封装(WLP)技术和引线接合工艺将集成电路管芯172b和172c封装在顶部封装后半导体器件178的衬底182上。可选地，顶部封装后半导体器件178可以包括封装在其他类型的封装***或配置中的一个或多个集成电路管芯172b或172c。
在本文示出和描述的先前实施例中，每一导电球140都与多个TSV 104连接。作为实例，在图10中，导电球140与三个TSV 104的暴露部分122连接。在其他实施例中，可以将每一导电球140连接到两个TSV 104的暴露部分122，或者四个或更多TSV104的暴露部分122(未在图中示出)。在其他实施例中，每一导电球140都只与一个TSV 104的暴露部分122连接，如图15所示。
例如，在一些实施例中，以球栅阵列(BGA)布置的方式布置本发明的导电球140。在一些实施例中，可以以完全填充阵列或矩阵的方式在中介衬底102的第一面106上布置导电球140。可选地，可以仅在中介衬底102的中心区域、仅在中介衬底102的周边区域中以一排或多排的方式、或者在中介衬底102的中心区域和周边区域的组合中布置导电球140。在一些实施例中，可以以随机模式布置导电球140。可以可选地以其他配置或模式布置导电球140。
本发明的实施例包括制造封装器件100的方法，并且还包括使用本文所描述的方法制造的封装器件100。本发明的实施例还包括使用本文所描述的新封装器件100的已经过封装的封装后半导体器件176。本发明的实施例还包括包含本文所描述的新封装器件100的PoP器件198。本发明的实施例进一步包括将焊料球140连接到封装衬底的方法。
本发明实施例的优点包括提供在其表面上形成焊料球时不需要球下金属化(UBM)结构的新封装器件100，这大幅减少了制造成本和时间，并且提供了成本相当低的封装器件100。制造传统的封装***所用的UBM结构是昂贵的，并且需要昂贵的加工步骤，诸如光刻、沉积和若干材料层的图案化。有利的是，将导电球140连接到本文所描述的封装器件100的TSV104的暴露部分122的方法不需要光刻工艺步骤，因此降低了成本。由于在封装器件100的导电球140侧不需要UBM结构，减小了封装器件100的厚度，从而能够生产出总体厚度减小并节约空间的PoP器件198。
在一些实施例中，在去除晶种层130期间使用导电球140作为蚀刻掩模，进一步消除了在封装器件100的制造工艺流程中对光刻工艺的需要。而且，新封装器件100的结构和制造方法在制造工艺流程中易于实施。
根据本发明的一些实施例，一种制造封装器件的方法包括在中介衬底中形成多个TSV。该方法包括使中介衬底凹陷或者增加多个TSV的厚度以暴露出多个TSV的一部分。将导电球连接到多个TSV中的每一个TSV的暴露部分。
根据其他实施例，一种封装器件包括中介衬底和设置在中介衬底中的多个TSV。中介衬底被凹陷至多个TSV的顶面下方。导电球与多个TSV中的每一个TSV连接。
根据其他实施例，一种将多个焊料球连接到封装衬底的方法包括提供封装衬底，封装衬底包括中介衬底和设置在中介衬底内的多个TSV。该方法包括使中介衬底凹陷或者增加多个TSV的厚度以暴露出多个TSV的一部分，并且在多个TSV的暴露部分上方形成晶种层。将焊料球连接到位于多个TSV中的每一个TSV的暴露部分上方的晶种层。
尽管已经详细地描述了本发明实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明的构思和范围的情况下，进行各种改变、替换和更改。例如，本领域技术人员将容易理解，本文中所描述的许多部件、功能、工艺和材料是可以变化的，并且仍然保留在本发明的范围内。而且，本申请的范围并不仅限于说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明的发明内容应很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (10)

1.一种制造封装器件的方法，所述方法包括：
在中介衬底中形成多个衬底通孔(TSV)；
使所述中介衬底凹陷或者增加所述多个TSV的厚度以暴露出所述多个TSV的一部分；以及
将导电球连接到所述多个TSV中的每一个TSV的暴露部分。
2.根据权利要求1所述的方法，其中，将所述导电球连接到所述多个TSV中的每一个TSV的暴露部分包括：使用落球工艺将所述导电球接合到所述多个TSV中的每一个TSV的暴露部分，以及回流所述导电球的共晶材料。
3.根据权利要求1所述的方法，其中，将所述导电球连接到所述多个TSV中的每一个TSV的暴露部分包括：在所述中介衬底和所述多个TSV的暴露部分上方形成在模板材料内设置的导电膏，去除所述模板材料以及回流所述导电膏的共晶材料。
4.根据权利要求3所述的方法，其中，形成在所述模板材料内设置的导电膏包括形成模板材料，所述模板材料包含选自基本上由聚合物、钢、Al合金、Mg合金以及它们的组合所组成的组中的材料。
5.根据权利要求1所述的方法，其中，增加所述多个TSV的厚度包括选自基本上由镀层工艺、沉积工艺以及它们的组合所组成的组中的方法。
6.根据权利要求1所述的方法，其中，连接所述导电球包括将一个所述导电球连接至多个所述TSV。
7.根据权利要求1所述的方法，其中，连接所述导电球包括将一个所述导电球连接至所述多个TSV中的每一个TSV。
8.一种封装器件，包括：
中介衬底；
多个衬底通孔(TSV)，设置在所述中介衬底中，其中所述中介衬底被凹陷至所述多个TSV顶面的下方；以及
导电球，与所述多个TSV的每一个TSV连接。
9.根据权利要求8所述的封装器件，其中，所述TSV包括从所述中介衬底的顶面伸出约10至20μm的暴露TSV(eTSV)。
10.一种将多个焊料球连接到封装衬底的方法，所述方法包括：
提供所述封装衬底，所述封装衬底包括中介衬底和设置在所述中介衬底内的多个衬底通孔(TSV)；
使所述中介衬底凹陷或者增加所述多个TSV的厚度以暴露出所述多个TSV的一部分；
在所述多个TSV的暴露部分上方形成晶种层；以及
将焊料球连接到位于所述多个TSV中的每一个TSV的暴露部分上方的晶种层。
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