CN103678771A - Automatic layout method for power/ground TSV positions in 3D integrated circuit - Google Patents
Automatic layout method for power/ground TSV positions in 3D integrated circuit Download PDFInfo
- Publication number
- CN103678771A CN103678771A CN201310562639.4A CN201310562639A CN103678771A CN 103678771 A CN103678771 A CN 103678771A CN 201310562639 A CN201310562639 A CN 201310562639A CN 103678771 A CN103678771 A CN 103678771A
- Authority
- CN
- China
- Prior art keywords
- tsv
- chip
- integrated circuit
- signal tsv
- layout
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to an automatic layout method for power/ground TSV positions in a 3D integrated circuit. An input unit is used for establishing a rectangular coordinate system of the 3D integrated circuit and initially determining coordinates of TSVs. A linear layout unit is used for horizontally moving signal TSVs to the closest straight lines. A shield unit is used for inserting ground TSVs and reducing noise between the signal TSVs. A grid distribution unit is used for establishing a secondary grid in a TSV layout chart. A power supply layout unit is used for inserting power TSVs to supply power to chips. According to the TSV layout chart with the given initial layout, capacitive noise may be produced between every two TSVs. Through the method of inserting the power TSVs and the ground TSVs, the electric field intensity between the TSVs can be effectively reduced, so that the purpose of shielding is achieved. Consequently, the capacitive noise caused by capacity coupling between the TSVs is reduced, and power can be supplied to the chips ceaselessly.
Description
Technical field
The autoplacement method that the present invention relates to a kind of 3D integrated circuit, belongs to circuit design field, relates in particular to power/groundTSV position autoplacement method in a kind of 3D integrated circuit.
Background technology
In recent years, day by day wide along with integrated circuit technique develop rapidly and development prospect, the encapsulation of integrated circuit is gradually to miniaturization, high speed, high-power, many pins, high density, the development of high reliability aspect, nowadays, the assembling of the two dimensional surface of traditional integrated circuit is more and more difficult to meet this demand.In order to solve the needs of problems of market and technology, people begin one's study and use micro-package technique to set about developing from two dimensional surface package technique to 3 D stereo package technique.Therefore, three-dimensional (3D) encapsulation has broken through conventional planar encapsulation concept, and packaging efficiency is increased substantially.It makes in single package body can stacking a plurality of chips, and by chip direct interconnection, interconnect length significantly shortens like this, and signal transmits sooner and institute is disturbed less; Secondly, it is together chip-stacked by a plurality of difference in functionalitys, makes single package body realize more function, thereby forms System on Chip/SoC encapsulation new approaches; Finally, the chip that adopts 3D encapsulation is low in energy consumption, the advantage such as speed is fast, number of pins is many in addition, and this makes the size of electronics and IT products and weight reduce decades of times.
For 3D integrated antenna package technology, silicon through hole technology (TSV) is a kind of emerging technical solution, and it can be accelerated device three-dimensional lamination and interconnection product clock frequency, reduces device power consumption, improve over all Integration degree.In order to catch up with Moore's Law paces, three-dimensional interconnection technology becomes inevitable especially.TSV technology has promotion Moore's Law development ground potentiality, and it has little profile factor and high performance 3 d chip system ability in addition, has been subject to gradually the extensive approval of industry member.3D-TSV is by between chip and chip, make vertical conducting between wafer and wafer, realizes the state-of-the-art technology interconnecting between chip.Different with the superimposing technique of use salient point from the bonding of IC encapsulation in the past, TSV can make chip minimum in three-dimensional stacking density maximum, physical dimension, greatly improve chip speed and low power capabilities, in the design of main flow device and production run TSV technology, will become inevitable.
Integrated circuit is after entering deep-submicron, and noise effect is increasing, makes it more and more become the problem that people pay close attention to.Between any a pair of adjacent closer network, all can have noise, two TSV are no exception.This be because signal when propagating, a part of electric field of signal path and return path extends to the space of closing on around and has formed fringing field, continues wiring and can produce the coupled noise of electric field, thereby disturbed circuit in this place, edge.The coupling capacitance producing between two TSV can make signal produce unnecessary interference noise, thereby affects effective work of 3D integrated circuit.For effectively solving the impact that this capacitive noise producing by being coupled brings, the present invention proposes power/groundTSV position autoplacement method in a kind of 3D integrated circuit, the present invention directly solves the capacitive noise problem between TSV with simple method, do not destroy ifq circuit structure, the TSV domain of preliminary placement is inserted to groundTSV and powerTSV, thereby reach the object of noise decrease and circuit supply.
Summary of the invention
The object of the present invention is to provide power/groundTSV position autoplacement method in a kind of 3D integrated circuit, it by inserting groundTSV in rational layout situation in 3D integrated circuit, thereby by inserting groundTSV, reach the object that reduces capacity coupled impact noise decrease, and powerTSV is in order to give chip power supply; In this 3D integrated circuit, powerTSV and groundTSV position autoplacement system comprise input block, straight line layout units, screen unit, grid distribution unit and power supply layout units five parts; Input block is used for setting up 3D integrated circuit rectangular coordinate system, tentatively determines TSV place coordinate; Straight line layout units is for moving to nearest straight line by signal TSV; Screen unit is used for inserting groundTSV, reduces noise between signal TSV; Grid distribution unit is for setting up a secondary grid at described TSV domain, and grid is for powerTSV layout; It is chip power supply that power supply layout units is used for inserting powerTSV.
For achieving the above object, the technical solution used in the present invention is power/groundTSV position autoplacement method in a kind of 3D integrated circuit, model 3D integrated circuit diagram coordinate system, and then tentatively definite TSV carries out straight line layout by signal TSV in position; Adopt subsequently the method for picture circle to insert groundTSV in the position that may produce circuit capacitive noise; Then setting up grid and inserting a powerTSV every two net points is chip power supply.Concrete steps are as follows:
S
1。set up 3D integrated circuit diagram rectangular coordinate system A, through in the TSV domain of Primary Location, setting up rectangular coordinate system A, coordinate system A sets up along the edge of domain, and its transverse axis is set up along the horizontal direction of domain, and the longitudinal axis is set up along the vertical direction of domain.
S
2。set up horizontal linear, signal TSV is moved to nearest straight line, the noise margin distance of take is spacing, sets up the parallel linear system B perpendicular to the longitudinal axis, utilizes plane right-angle coordinate mid point to the range formula of straight line, to calculate the distance of upper and lower two lines of each TSV distance; Each signal TSV is projected on nearest line, and move on this aspect, mobile if certain some signal TSV just in time on straight line, does not need.
S
3。in 3D integrated circuit diagram, insert groundTSV, each TSV of take successively in domain is the center of circle, the noise margin distance of TSV of take is done circle as radius, if there is TSV on circle or in circle, for there is the situation of capacitive noise in this, now, the TSV on circle or in circle and the line mid point of center of circle TSV insert a groundTSV, if two TSV line mid points have had groundTSV, do not insert.
S
4。set up a secondary grid C, the mesh lines of grid C vertical direction is perpendicular to the parallel linear system D of coordinate transverse axis, and its spacing equals noise margin distance; The mesh lines of grid C horizontal direction is perpendicular to the parallel linear system E of the coordinate longitudinal axis, and spacing equals noise margin distance and in horizontally-arranged TSV middle point midway between two; The intersection point of parallel lines series D and parallel lines series E forms the lattice point of grid B; The distance of above-mentioned any two adjacent lattice points equals noise margin distance.
S
5。in the net point of grid C, insert powerTSV, with every two integer lattice, insert a powerTSV, if just there are other TSV in this lattice point, lattice point around this point is numbered clockwise, the powerTSV not placing is put on idle lattice point, finally completes the layout to powerTSV.
For realizing above-mentioned steps, the function of the powerTSV in this 3D integrated circuit and groundTSV position autoplacement system unit is as follows.
Input block is used for setting up 3D integrated circuit rectangular coordinate system, preliminary definite TSV place coordinate, through in the TSV domain of Primary Location, setting up rectangular coordinate system A, coordinate system A sets up along the edge of domain, its transverse axis is set up along the horizontal direction of domain, the longitudinal axis is set up along the vertical direction of domain, by coordinate, tentatively determines qualified TSV position.
Straight line layout units is for moving to nearest straight line by signal TSV, and the noise margin distance of take is spacing, sets up the parallel linear system B perpendicular to the longitudinal axis, utilizes rectangular coordinate system mid point to the range formula of straight line, to calculate the distance of upper and lower two lines of each TSV distance; Each signal TSV is projected on nearest line, and move on this aspect, the TSV being present on line does not need mobile.
Screen unit is used for inserting groundTSV, reduce noise between signal TSV, each TSV of take successively in domain is the center of circle, the noise margin distance of TSV of take is done circle as radius, if there is TSV on circle or in circle, for there is the situation of capacitive noise in this, and now the line mid point of the TSV on circle or in circle and center of circle TSV inserts a ground and meets TSV, if two TSV line mid points have existed TSV, do not need to insert.
Grid distribution unit is for setting up a secondary grid C at described TSV domain, and grid C is for powerTSV layout, and the mesh lines of grid C vertical direction is perpendicular to the parallel linear system D of coordinate transverse axis, and its spacing equals least commitment spacing; The mesh lines of grid C horizontal direction is perpendicular to the parallel linear system E of the coordinate longitudinal axis, and spacing equals noise margin distance and in position, horizontally-arranged TSV middle between two; The intersection point of parallel lines series D and parallel lines series E forms the lattice point of grid C; The distance of above-mentioned any two adjacent lattice points equals least commitment spacing;
Power supply layout units is used for inserting powerTSV, for chip power supply, with every two integer lattice, insert a powerTSV, if just there is TSV in this lattice point, lattice point around this point is numbered clockwise, the powerTSV not placing is put on idle lattice point, finally completes the layout to powerTSV.
Wherein the scale of coordinate system A coordinate axis conforms to the size of actual domain, and is accurate to nanoscale.
Compared with prior art, the present invention can obtain following beneficial effect: the TSV domain for given preliminary placement, may produce capacitive noise between TSV between two; Method by insertion of the present invention powerTSV and groundTSV can reduce the electric field intensity between TSV effectively, reaches the object of shielding, thereby has reduced the capacitive noise that produced by capacitive coupling between TSV, also gives chip continued power simultaneously.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of 3D integrated circuit (IC) chip;
Fig. 2 is the former domain of TSV;
Fig. 3 is the TSV domain inserting after linear system anyhow;
Fig. 4 is that TSV moves schematic diagram;
Fig. 5 is the TSV domain after straight line layout;
Fig. 6 is for inserting the schematic diagram of groundTSV;
Fig. 7 is 3D integrated circuit diagram after insertion groundTSV;
Fig. 8 is the TSV domain after grid layout;
Fig. 9 is domain after insertion powerTSV;
Figure 10 is that powerTSV adjusts schematic diagram.
In figure: 1, signal TSV, 2, powerTSV, 3, groundTSV, 4, noise margin distance, 5, coordinate system, 6, top layer chip, 7, bottom chip, 8, standard block, 9, metal interconnection wire, 10, substrate, 11, horizontal straight line, 12, lattice point, 13, ruling.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
Be illustrated in figure 1 the cross-sectional view of 3D integrated circuit (IC) chip, this 3D integrated circuit (IC) chip comprises signal TSV1, powerTSV2, groundTSV3, top layer chip 6, bottom chip 7, standard block 8, metal interconnection wire 9 and substrate 10; The present invention includes five unit, be respectively input block, straight line layout units, screen unit, grid distribution unit, power supply layout units; 3D integrated circuit in the present invention is a kind of three-dimensional chip structure, and every one deck of 3D integrated circuit is all 2D chip, and is coupled together at vertical direction by TSV; Top layer chip 6 and low layer chip 7 two parts form the general structure of chip; Standard block 8 in chip is in integrated circuit, to realize the interconnected element of signal, and metal interconnection wire 9 completes interconnected to standard block 8; Top layer chip 6 in chip is connected with bottom chip 7 and need to passes through signal TSV1; PowerTSV2 is chip power supply, and groundTSV3 can reduce the capacitive noise between signal TSV1; Autoplacement by powerTSV2 and groundTSV3 completes the optimization to circuit performance, and three kinds of TSV of this in chip are the silicon through holes through adjacent two layers chip.
It is below specific embodiment of the invention step.
Be illustrated in figure 2 the former domain of TSV, input block comprises signal TSV1 and rectangular coordinate system 5, and its function is for preliminary definite signal TSV place coordinate; The first step is set up 3D integrated circuit diagram rectangular coordinate system A, tentatively determines each signal TSV1 position; Black circles in figure is signal TSV1, through in the signal TSV1 domain of Primary Location, is setting up rectangular coordinate system A, and coordinate system A sets up along the edge of domain, and its transverse axis is set up along the horizontal direction of domain, and the longitudinal axis is set up along the vertical direction of domain.
Be illustrated in figure 3 the TSV domain inserting after linear system anyhow, Fig. 4 is that TSV moves schematic diagram, and Fig. 5 is the TSV domain after straight line layout, and straight line layout units comprises signal TSV1 rectangular coordinate system 5 and horizontal straight line 11, its function, for the signal TSV1 of regular domain, is tentatively carried out layout to domain; Second step is set up horizontal system of straight lines B, and signal TSV1 is moved to nearest straight line; In coordinate system A, the noise margin distance 4 of take is spacing, sets up the parallel linear system B perpendicular to the longitudinal axis, utilizes subsequently rectangular coordinate system mid point to the range formula of straight line, to calculate the distance of upper and lower two lines of each signal TSV1 distance; Each signal TSV1 is projected on nearest line, and this signal TSV1 is moved on subpoint, if there is the Already in situation on straight line of a certain signal TSV1, do not need to move processing and finally obtain the domain after straight line layout.
Be illustrated in figure 6 the schematic diagram that inserts groundTSV3, Fig. 7 is 3D integrated circuit diagram after insertion groundTSV3, screen unit comprises signal TSV1, groundTSV3, noise margin distance 4 and rectangular coordinate system 5, and its function is for reducing the capacitive noise between signal TSV1; The 3rd step is inserted groundTSV3 in 3D integrated circuit diagram; Successively with each the signal TSV1 in domain as the center of circle, the noise margin distance of TSV of take is done circle as radius, solid black triangle is groundTSV3, if there is signal TSV1 on circle, for there is the situation of capacitive noise in this, the line mid point of the signal TSV1 on circle and center of circle signal TSV1 inserts a groundTSV3; Signal TSV1 outside circle causes the impact of noise to ignore; During insertion, if two signal TSV1 line mid points have existed a signal TSV1, skip and do not need to insert, finally complete the layout to groundTSV3.
Be illustrated in figure 8 the TSV domain after grid layout, grid layout units comprises rectangular coordinate system 5, lattice point 12 and ruling 13, and its function is for generation of the position of inserting powerTSV2; Generating mesh C in the coordinate system 5 of the 4th step in domain; The mesh lines 13 of grid C vertical direction is perpendicular to the parallel linear system D of coordinate transverse axis, and its spacing equals noise margin distance 4; The mesh lines 13 of grid C horizontal direction is perpendicular to the parallel linear system E of the coordinate longitudinal axis, and its point midway and spacing that is positioned at the every two row signal TSV1 middles after straight line layout equals noise margin distance 4; The intersection point of parallel lines series D and parallel lines series E forms the lattice point 12 of grid C, therefore the distance of above-mentioned any two adjacent lattice points equals noise margin distance 4.
Be illustrated in figure 9 and insert domain after powerTSV2, Figure 10 is that powerTSV2 adjusts schematic diagram, and power supply layout units comprises signal TSV1, powerTSV2, groundTSV3, rectangular coordinate system 5, lattice point 12 and ruling 13, and its function is used to chip power supply; The 5th step is inserted powerTSV2 in the lattice point 12 of grid C, is chip power supply; In the grid that layout is good, every two lattice points 12, insert a powerTSV2; In figure, solid black square is powerTSV2, if just there is signal TSV1 in this lattice point 12, surrounding's lattice point 12 of this lattice point 12 is numbered clockwise, the powerTSV2 of layout is not placed on idle lattice point 12 around, finally complete the layout to powerTSV2; In figure, signal TSV1 straight line is arranged, and groundTSV3 and powerTSV2 are uniformly distributed in domain, has effectively reduced the capacitive noise between each signal TSV1 and has optimized chip power supply structure.
The inventive method model rectangular coordinate system 5, preliminary definite each signal TSV1 position, then set up level linear system B signal TSV1 is moved on nearest straight line anyhow, accomplish linear layout, the noise margin distance 4 of take is subsequently inserted groundTSV3 as radius picture circle and in the position that may produce circuit capacitive noise, then set up a secondary grid C, the coordinate of the intersection point that in grid C, two equidistant serial orthogonal parallel lines form becomes lattice point 12, the intersection point that is ruling 13 is lattice point 12, the spacing size of this two series of parallel line equals the noise margin distance of TSV, finally every two lattice points 12, inserting a powerTSV2 is chip power supply, complete whole layout process.
Claims (5)
1. a power/groundTSV position autoplacement method in 3D integrated circuit, is characterized in that: this 3D integrated circuit (IC) chip comprises signal TSV(1), powerTSV(2), groundTSV(3), top layer chip (6), bottom chip (7), standard block (8), metal interconnection wire (9) and substrate (10); One is divided into five unit, is respectively input block, straight line layout units, screen unit, grid distribution unit, power supply layout units; This 3D integrated circuit is a kind of three-dimensional chip structure, and every one deck of 3D integrated circuit is all 2D chip, and is coupled together at vertical direction by TSV; Top layer chip (6) and low layer chip (7) two parts form the general structure of chip; Standard block in chip (8) is in integrated circuit, to realize the interconnected element of signal, and metal interconnection wire (9) completes interconnected to standard block (8); Top layer chip (6) in chip is connected with bottom chip (7) and need to passes through signal TSV(1); PowerTSV(2) be chip power supply, and groundTSV(3) can reduce signal TSV(1) between capacitive noise; Pass through powerTSV(2) and autoplacement groundTSV(3) complete the optimization to circuit performance, three kinds of TSV of this in chip are the silicon through holes through adjacent two layers chip;
Input block comprises signal TSV(1) and rectangular coordinate system (5), its function is for preliminary definite signal TSV place coordinate; The first step is set up 3D integrated circuit diagram rectangular coordinate system A, tentatively determines each signal TSV(1) position; Signal TSV(1 in process Primary Location) in domain, set up rectangular coordinate system A, coordinate system A sets up along the edge of domain, and its transverse axis is set up along the horizontal direction of domain, and the longitudinal axis is set up along the vertical direction of domain;
Straight line layout units comprises signal TSV1 rectangular coordinate system (5) and horizontal straight line (11), and its function is for the signal TSV(1 of regular domain), tentatively domain is carried out to layout; Second step is set up horizontal system of straight lines B, by signal TSV(1) move to nearest straight line; In coordinate system A, the noise margin distance (4) of take be spacing, sets up the parallel linear system B perpendicular to the longitudinal axis, utilizes subsequently rectangular coordinate system mid point to calculate each signal TSV(1 to the range formula of straight line) apart from the distance of upper and lower two lines; By each signal TSV(1) project on nearest line, and by this signal TSV(1) move on subpoint, if there is a certain signal TSV(1) situation on straight line Already in, do not need to move processing and finally obtain the domain after straight line layout;
Screen unit comprises signal TSV(1), groundTSV(3), noise margin distance (4) and rectangular coordinate system (5), its function is used for reducing signal TSV(1) between capacitive noise; The 3rd step is inserted groundTSV(3 in 3D integrated circuit diagram); Successively with each the signal TSV(1 in domain) as the center of circle, the noise margin distance of TSV of take is done circle as radius, if have signal TSV(1 on circle), for there is the situation of capacitive noise in this, the signal TSV(1 on circle) and center of circle signal TSV(1) a groundTSV(3 of line mid point insertion); Signal TSV(1 outside circle) cause the impact of noise to ignore; Grid layout units comprises rectangular coordinate system (5), lattice point (12) and ruling (13), and its function is for generation of inserting powerTSV(2) position; Generating mesh C in the coordinate system (5) of the 4th step in domain; The mesh lines (13) of grid C vertical direction is perpendicular to the parallel linear system D of coordinate transverse axis, and its spacing equals noise margin distance (4); The mesh lines (13) of grid C horizontal direction is perpendicular to the parallel linear system E of the coordinate longitudinal axis, and it is positioned at the every two row signal TSV(1 after straight line layout) point midway of middle and spacing equal noise margin distance (4);
Power supply layout units comprises signal TSV(1), powerTSV(2), groundTSV(3), rectangular coordinate system (5), lattice point (12) and ruling (13), its function is used to chip power supply; The 5th step is inserted powerTSV(2 in the lattice point (12) of grid C), be chip power supply; In the grid that layout is good, every two lattice points (12), insert a powerTSV(2); If there is signal TSV(1 in this lattice point (12) just, surrounding's lattice point (12) of this lattice point (12) is numbered clockwise, by the powerTSV(2 of layout not) to be placed into idle lattice point (12) around upper, finally complete powerTSV(2) layout.
2. power/groundTSV position autoplacement method in a kind of 3D integrated circuit according to claim 1, it is characterized in that: in 3D integrated circuit diagram, insert groundTSV(3) in process, if there is a signal TSV(1 in line mid point two signal TSV(1)), skip and do not need to insert, finally complete the layout to groundTSV3.
3. power/groundTSV position autoplacement method in a kind of 3D integrated circuit according to claim 1, it is characterized in that: the intersection point of parallel lines series D and parallel lines series E forms the lattice point (12) of grid C, therefore the distance of above-mentioned any two adjacent lattice points equals noise margin distance (4).
4. power/groundTSV position autoplacement method in a kind of 3D integrated circuit according to claim 1, it is characterized in that: signal TSV(1) straight line is arranged, groundTSV(3) and powerTSV(2) be uniformly distributed in domain, effectively reduced each signal TSV(1) between capacitive noise and optimized chip power supply structure.
5. power/groundTSV position autoplacement method in a kind of 3D integrated circuit according to claim 1, is characterized in that: the scale of coordinate system A coordinate axis conforms to the size of actual domain, and is accurate to nanoscale.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310562639.4A CN103678771B (en) | 2013-11-13 | 2013-11-13 | Power/groundTSV position autoplacement method in a kind of 3D integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310562639.4A CN103678771B (en) | 2013-11-13 | 2013-11-13 | Power/groundTSV position autoplacement method in a kind of 3D integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103678771A true CN103678771A (en) | 2014-03-26 |
| CN103678771B CN103678771B (en) | 2016-08-17 |
Family
ID=50316307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310562639.4A Active CN103678771B (en) | 2013-11-13 | 2013-11-13 | Power/groundTSV position autoplacement method in a kind of 3D integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103678771B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106096118A (en) * | 2016-06-06 | 2016-11-09 | 厦门大学 | Three-dimensional circuit automatic wiring method based on rubber band in dynamo-electric integrated products |
| CN106354894A (en) * | 2015-07-15 | 2017-01-25 | 中国科学院微电子研究所 | Distribution method and system of analog circuit |
| CN110377978A (en) * | 2019-06-29 | 2019-10-25 | 苏州浪潮智能科技有限公司 | The method and system of 0402 resistor-capacitor unit is placed in a kind of PCB design under BGA package |
| CN110750950A (en) * | 2019-10-14 | 2020-02-04 | 中国兵器工业集团第二一四研究所苏州研发中心 | Method for automatically shielding layout key signal line |
| CN112258603A (en) * | 2020-10-30 | 2021-01-22 | 西南石油大学 | Three-axis layout drawing method for analyzing rule of three-factor composite influence and application thereof |
| CN114864525A (en) * | 2022-07-08 | 2022-08-05 | 之江实验室 | Standard integrated area wiring structure and method of wafer substrate suitable for on-chip integration |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100058580A1 (en) * | 2008-09-06 | 2010-03-11 | Farhang Yazdani | Stacking Integrated Circuits containing Serializer and Deserializer Blocks using Through Silicon Via |
| US8103996B2 (en) * | 2008-06-24 | 2012-01-24 | Cadence Design Systems, Inc. | Method and apparatus for thermal analysis of through-silicon via (TSV) |
| CN102663204A (en) * | 2012-04-25 | 2012-09-12 | 北京工业大学 | Distance optimizing method of through silicon via (TSV) positions in three-dimensional (3D) integrated circuit automatic layout |
-
2013
- 2013-11-13 CN CN201310562639.4A patent/CN103678771B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8103996B2 (en) * | 2008-06-24 | 2012-01-24 | Cadence Design Systems, Inc. | Method and apparatus for thermal analysis of through-silicon via (TSV) |
| US20100058580A1 (en) * | 2008-09-06 | 2010-03-11 | Farhang Yazdani | Stacking Integrated Circuits containing Serializer and Deserializer Blocks using Through Silicon Via |
| CN102663204A (en) * | 2012-04-25 | 2012-09-12 | 北京工业大学 | Distance optimizing method of through silicon via (TSV) positions in three-dimensional (3D) integrated circuit automatic layout |
Non-Patent Citations (3)
| Title |
|---|
| LIGANG HOU, ET AL.: "Reserch on TSV Positioning in 3D IC Placement", 《ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM(EDAPS), 2011IEEE》, 14 December 2011 (2011-12-14), pages 1 - 4, XP032449734, DOI: doi:10.1109/EDAPS.2011.6213801 * |
| LIGANG HOU, ET AL.: "Signal Integrity Aware TSV Positioning", 《ELECTROMAGNETIC COMPATIBILITY (APEMC), 2012 ASIA-PACIFIC SYMPOSIUM ON》, 24 May 2012 (2012-05-24), pages 825 - 828, XP032199648, DOI: doi:10.1109/APEMC.2012.6237990 * |
| 侯立刚等: "防串扰的3D芯片TSV自动布局", 《计算机辅助设计与图形学学报》, vol. 25, no. 4, 30 April 2013 (2013-04-30), pages 578 - 583 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106354894A (en) * | 2015-07-15 | 2017-01-25 | 中国科学院微电子研究所 | Distribution method and system of analog circuit |
| CN106354894B (en) * | 2015-07-15 | 2019-12-03 | 中国科学院微电子研究所 | A kind of layout method and system of analog circuit |
| CN106096118A (en) * | 2016-06-06 | 2016-11-09 | 厦门大学 | Three-dimensional circuit automatic wiring method based on rubber band in dynamo-electric integrated products |
| CN106096118B (en) * | 2016-06-06 | 2018-12-25 | 厦门大学 | For the three-dimensional circuit automatic wiring method in electromechanical integrated products based on rubber band |
| CN110377978A (en) * | 2019-06-29 | 2019-10-25 | 苏州浪潮智能科技有限公司 | The method and system of 0402 resistor-capacitor unit is placed in a kind of PCB design under BGA package |
| CN110377978B (en) * | 2019-06-29 | 2022-07-08 | 苏州浪潮智能科技有限公司 | Method and system for placing 0402 resistor under BGA package in PCB design |
| CN110750950A (en) * | 2019-10-14 | 2020-02-04 | 中国兵器工业集团第二一四研究所苏州研发中心 | Method for automatically shielding layout key signal line |
| CN110750950B (en) * | 2019-10-14 | 2023-04-18 | 中国兵器工业集团第二一四研究所苏州研发中心 | Method for automatically shielding layout key signal line |
| CN112258603A (en) * | 2020-10-30 | 2021-01-22 | 西南石油大学 | Three-axis layout drawing method for analyzing rule of three-factor composite influence and application thereof |
| CN114864525A (en) * | 2022-07-08 | 2022-08-05 | 之江实验室 | Standard integrated area wiring structure and method of wafer substrate suitable for on-chip integration |
| CN114864525B (en) * | 2022-07-08 | 2022-10-21 | 之江实验室 | Standard integrated area wiring structure and method of wafer substrate suitable for on-chip integration |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103678771B (en) | 2016-08-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103678771A (en) | Automatic layout method for power/ground TSV positions in 3D integrated circuit | |
| CN103268380A (en) | Analogue integrated circuit layout designing method capable of improving layout efficiency | |
| CN110197019A (en) | Process design method, system, medium and equipment based on system encapsulation technology | |
| CN102663204B (en) | Distance optimizing method of through silicon via (TSV) positions in three-dimensional (3D) integrated circuit automatic layout | |
| CN103688353A (en) | Microelectronic device, stacked die package and computing system containing same, method of manufacturing a multi not channel communication pathway in same, and method of enabling electrical communication between components of a stacked-die package | |
| CN104008998B (en) | Multi-chip laminating method for packing | |
| TW201729391A (en) | Ground plane vertical isolation of, ground line coaxial isolation of, and impedance tuning of horizontal data signal transmission lines routed through package devices | |
| US7752587B2 (en) | Vertically tapered transmission line for optimal signal transition in high-speed multi-layer ball grid array packages | |
| CN103324773B (en) | The Trench raceway groove layout method of TSV in 3D integrated circuit | |
| TW201729390A (en) | Ground plane vertical isolation of, ground line coaxial isolation of, and impedance tuning of horizontal data signal transmission lines routed through package devices | |
| CN104810349A (en) | Differential inductor | |
| CN103886148B (en) | Automatic layout method and system for positions of heat through holes in 3D integrated circuit | |
| CN102682163A (en) | Grid optimization method for through silicon via (TSV) positions in automatic layout of three-dimensional (3D) integrated circuit | |
| CN106815380A (en) | A kind of method and system for extracting dead resistance | |
| CN103745069A (en) | Method for establishing TSV (through silicon via) signal transmission and power consumption module of three-dimensional integrated circuit | |
| CN102622481A (en) | Method for designing complementary data redundancy structure type CMOS (Complementary Metal Oxide Semiconductor) standard cell circuit physical library model | |
| CN106815379A (en) | A kind of method and system for extracting parasitic capacitance | |
| Xie et al. | A 3D package design with cavity substrate and stacked die | |
| CN103560097A (en) | Wiring path optimization method for three-dimensional chip | |
| CN204424248U (en) | Through-silicon via structure | |
| Huang et al. | A novel design methodology for hybrid process 3D-IC | |
| CN203562421U (en) | Metal wiring structure of integrated circuit | |
| CN103678770B (en) | TSV position autoplacement method in a kind of 3D integrated circuit based on noise reduction purpose | |
| Pak et al. | Sharing power distribution networks for enhanced power integrity by using through-silicon-via | |
| Pang et al. | Electrical simulation of 3X3 TSV array with different signal and ground patterns |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |