CN102663204B - Distance optimizing method of through silicon via (TSV) positions in three-dimensional (3D) integrated circuit automatic layout - Google Patents
Distance optimizing method of through silicon via (TSV) positions in three-dimensional (3D) integrated circuit automatic layout Download PDFInfo
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- CN102663204B CN102663204B CN201210125773.3A CN201210125773A CN102663204B CN 102663204 B CN102663204 B CN 102663204B CN 201210125773 A CN201210125773 A CN 201210125773A CN 102663204 B CN102663204 B CN 102663204B
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Abstract
The invention discloses a distance optimizing method of through silicon via (TSV) positions in a three-dimensional (3D) integrated circuit automatic layout. The distance optimizing method has wide application to the field of design and manufacture of 3D integrated circuits. In a layout formed after initial locating of common 3D integrated circuit TSVs, the number of the TSVs is big, and distribution of the TSVs in the layout is dense, therefore a problem that the positions of the TSVs are too close occurs. When the 3D integrated circuit is manufactured and produced, manufacturers can not manufacture the layout where gaps of the TSVs are smaller than gap restrain of manufacture process. The method uses a distance method to optimize the gaps of the TSVs, an optimized layout is obtained so as to enable the gaps of the TSVs to meet process manufacture requirements, and manufacture can be finished. In the optimized TSV layout, distance of the TSVs is appropriate, working speed of the circuit can be increased, and crosstalk is reduced.
Description
Invention field
Present invention relates in general to the design and manufacture of 3D integrated circuit, more specifically, the present invention relates to the method for the autoplacement of three dimensional integrated circuits design, belong to circuit design field.
Background technology
The Design and manufacture level of integrated circuit is always in development at full speed, nowadays can be on one single chip integrated several hundred million transistors.More specifically, according to the description of Moore's Law, advanced technological level has reached nanoscale.Due to the increase of number of transistors on one single chip, common 2D integrated circuit can bring the long problem of circuit, and this reduces the arithmetic speed of circuit, and power consumption increases.3D integrated circuit can effectively reduce line length, improves arithmetic speed, reduces power consumption.
3D integrated circuit is a kind of emerging technology, reduces the area of chip by placing in vertical direction a plurality of IC chips.Between multilayer chiop, can make its unit carry out the interconnected of interlayer by TSV (across chip layer silicon hole) simultaneously.As long as it is reasonable that place the position of TSV, this 3D integrated circuit technique based on TSV can effectively reduce gauze length.
Be illustrated in figure 1 3D chip schematic diagram, 3D integrated circuit is by top layer chip 1 and the stacking 3 D stereo circuit structure forming of bottom chip 2.Standard block 4 in circuit is the basic structure of circuit.The 3D circuit chip of certain one deck, its character and common 2D chip are similar.Standard block 4 is undertaken interconnected by metal interconnection wire 6.In 2D circuit, the set of all unit that link together by metal interconnection wire is referred to as gauze.In 3D integrated circuit, the gauze (gauze of similar 2D circuit) that all unit are all in same layer is individual layer gauze.Unit is also interconnected by metal wire.And in 3D circuit, some also needs interconnected in the unit in different layers respectively.The gauze being comprised of the unit in different layers is called cross-layer gauze, and the gauze being comprised of standard block 4 is cross-layer gauze.And unit in different layers needs when interconnected, can utilize TSV5 (silicon through hole) to carry out interconnected.
In 3D integrated circuit, the effect of TSV is mainly two.First, the unit of the upper strata of 3D integrated circuit and the 2D of lower floor chip is undertaken interconnected by TSV, and TSV is for connecting the bridge of cross-layer gauze in unit, the upper and lower; Secondly, because the material of TSV is that the very high materials of thermal conductivity such as copper aluminium are better than the semiconductor materials such as silicon to heat energy power mostly, therefore place the heat radiation that appropriate TSV contributes to circuit in circuit.
Experiment shows, the minimizing degree of gauze length is relevant with the quantity of TSV, and TSV quantity can help the minimizing of gauze length at most, and the quantity of TSV is less than to a certain degree and can increases and outer gauze length on the contrary.And that places in circuit as the TSV of heat sinking function is more, its heat radiation to circuit helps larger.
But under the constraint of technological level, the position of TSV can not be too intensive, and quantity can not be too many.In the situation that meeting processing technology size, the function of completing circuit.
In domain after general 3D integrated circuit TSV Primary Location, the quantity of TSV is more, in domain, distributes and compares comparatively dense.Thereby the too approaching problem in position that there will be TSV.When 3D integrated circuit carries out processing, the spacing that manufacturer can not process TSV is less than the domain of the spacing constraint of processing technology.
Therefore in 3D integrated circuit Automated Design, after TSV location positioning, can meet technological requirement in order to meet its position, complete processing, need to be optimized the position of TSV.
Summary of the invention:
For solve in 3D integrated circuit across the too congestion problem of position, chip layer silicon hole (Through Silicon Via), the present invention proposes the distance optimization of TSV position in a kind of 3D integrated circuit autoplacement.Optimization of the present invention is devoted to optimize tentatively definite domain of TSV.
The present invention adopts following technical scheme:
The distance optimization of TSV position in 3D integrated circuit autoplacement, the TSV that spacing in circuit is less than to processes spacing flicks, and claims this method for flicking method; Arrange one by one the TSV that all spacing are less than processes spacing, make their spacing meet the constraint of processes spacing.。
Concrete steps are as follows:
S1, sets up 3D integrated circuit diagram rectangular coordinate system: in the 3D integrated circuit diagram of TSV Primary Location, set up rectangular coordinate system A, coordinate system A sets up along the edge of domain, and its transverse axis is set up along the horizontal direction of domain, and the longitudinal axis is set up along the vertical direction of domain;
S2, sets up the TSV pair set B that spacing is less than processes spacing: calculate respectively the coordinate of each TSV in coordinate system, obtain the coordinate points of each TSV in domain; Utilize the distance computing formula of plane right-angle coordinate to calculate the coordinate of each TSV and the coordinate of other all TSV and do distance and calculate, try to achieve arbitrarily the distance of TSV between two; Calculate after the distance between all TSV, set up the right set B of TSV that spacing is between two less than processes spacing.Then the TSV that spacing is less than to processes spacing is to putting into set B, and wherein said TSV is to comprising the coordinate of two TSV.The right number of TSV in set of computations B;
S3: when the number that TSV is right in set B equals 0, show, without being optimized again, to jump out optimizing process; When being greater than 0, carries out the number that TSV is right in set B S4;
S4, flicks and processes the TSV couple that spacing is less than processes spacing: the maximum TSV of TSV centering occurrence number that chooses set B is basic point; Using basic point as the center of circle, and the processes spacing of take is drawn circle as radius, will drop on all TSV in this circle on the circumference that radially moves on to this circle of circle.
S2, S3, S4 are carried out in circulation, until TSV is zero to number in set B, jump out optimizing process.
The distance optimization device of TSV position in 3D integrated circuit autoplacement, it includes:
Input block: for setting up 3D integrated circuit diagram rectangular coordinate system: the 3D integrated circuit diagram of TSV Primary Location is set up rectangular coordinate system A, coordinate system A sets up along the edge of domain, its transverse axis is set up along the horizontal direction of domain, and the longitudinal axis is set up along the vertical direction of domain;
TSV is to deposit receipt unit: the TSV pair set B that is less than processes spacing for setting up spacing: calculate respectively each TSV at the coordinate of coordinate system, obtain the coordinate points of each TSV in domain; Utilize the distance computing formula of plane right-angle coordinate to calculate the coordinate of each TSV and the coordinate of other all TSV and do distance and calculate, try to achieve arbitrarily the distance of TSV between two; Calculate after the distance between all TSV, set up the right set B of TSV that spacing is between two less than processes spacing.Then the TSV that spacing is less than to processes spacing is to putting into set B, and wherein said TSV is to comprising the coordinate of two TSV.
Judging unit: carry out when judging that the right number of number TSV in set B that TSV TSV is right is greater than 0 and optimize, when the number that TSV is right in set B equals 0, show without being optimized again.
Flick unit: for flicking, process the TSV couple that spacing is less than processes spacing: the maximum TSV of TSV centering occurrence number that chooses set B is basic point; Using basic point as the center of circle, and the processes spacing of take is drawn circle as radius, will drop on all TSV in this circle on the circumference that radially moves on to this circle of circle.
The present invention can obtain following beneficial effect:
For given TSV domain, TSV has carried out Primary Location, but the spacing position of TSV may not meet the requirement of processes spacing between two.By of the present invention, flick the diagram optimizing mode that method moves TSV position and can be met the TSV domain that processes requires, reach the object of the crowded TSV of dredging, avoid the situation that TSV is too intensive.
By comparison diagram 7 and Fig. 8, can intuitively find out by the domain of gridding method optimization, between TSV, spacing meets processes requirement.
Accompanying drawing explanation:
Fig. 1 is the diagrammatic cross-section of 3D integrated circuit (IC) chip;
Fig. 2 is the former domain of TSV;
Fig. 3 is that crowded TSV moves schematic diagram;
Fig. 4 is TSV domain after optimizing;
Fig. 5 is the process flow diagram of the distance optimization method of TSV position in 3D integrated circuit of the present invention autoplacement;
Fig. 6 is the structural representation of the distance optimization device of TSV position in 3D integrated circuit of the present invention autoplacement;
Fig. 7 is the domain after TSV Primary Location in 3D circuit:
Fig. 8 is the domain for Furthest Neighbor optimization:
In figure: 1, TSV, 2, minimum spacing, 3, coordinate system, 4, moving direction, 5, processes spacing, 6, top layer chip, 7, bottom chip, 8, standard block, 9, metal interconnection wire, 10, substrate.
Embodiment:
3D integrated circuit is a kind of chip structure of 3 D stereo, its every one deck is all the chip of 2D, and as shown in Figure 1, the unit 8 in chip is horizontally disposed in chip for the structure of its any two interlayers, unit is the foundation structure of signal communication in circuit, in chip, by metal interconnection wire, is connected.Wherein the unit in adjacent layers of chips need to connect by TSV1, and TSV1 is the via hole through chip in circuit, thereby makes upper and lower layers of chips UNICOM, therefore TSV1 is the structure that 3D integrated circuit is different from 2D circuit.Wherein, 3D circuit at the middle and upper levels chip be called top layer chip, lower floor's chip is bottom chip.This layers of chips can be any two-layer adjacent chip in 3D circuit.
The present invention is devoted to optimize the 3D integrated circuit diagram of tentatively determining TSV1 coordinate.After TSV1 Primary Location, occur that the spacing of TSV is less than the situation of processing technology constraint, therefore can not processing and manufacturing.Must optimize its position and arrange, make it to meet the constraint of processes spacing, and can processing and manufacturing.The method of its optimization refers to, arranges the TSV1 couple that violates spacing constraint.Increase the spacing of the TSV1 that violates spacing constraint, make them meet spacing constraint.Finally, make the spacing between all TSV in domain meet processes dimension constraint.Concrete performing step below:
S1, sets up in the domain that coordinate lies in TSV1, and determines the coordinate of each TSV1.As Fig. 2, in figure, black circles is TSV1, sets up coordinate axis 3, two coordinate axis of rectangular coordinate system A along the edge direction of domain, and the direction of transverse axis is along the horizontal direction of domain, and the direction of the longitudinal axis is along the vertical direction of domain.Determine the coordinate of each TSV1, and mark in domain.The coordinate of all TSV1 has been determined, the spacing that calculates all TSV1 between two utilizes in rectangular coordinate system 2 apart from computing formula.
S2, set up one by TSV1 to the set B forming, in domain, the distance of any two TSV1 has been violated the numbering that the constraint of technique spacing is about to them and has been put into set B, thus the element in set B can be any two possible TSV1 to and the right spacing of these TSV be less than the requirement of technique teaching and administrative staff spacing.
S3, if the TSV logarithm in set B is 0, illustrates that this domain does not need to arrange, and directly skips arrangement step.TSV logarithm in set B is more than or equal to 1, just carries out S4 step, arranges domain.
S4, moving interval is less than the TSV1 of technique spacing one by one, makes their spacing be greater than processes spacing.Find out in set B, at the maximum TSV of TSV centering occurrence number, its coordinate is a bit in domain, take this coordinate points as the center of circle, and the length of the processing technology spacing of take constraint 5 is that radius is drawn circle, i.e. the scope that TSV processing spacing retrains.Other TSV1 that occur in circle are with center of circle TSV1 and have violated the TSV that spacing requires.Then the central coordinate of circle point of take is benchmark, towards the direction that deviates from central coordinate of circle point, moves other TSV1, and they are moved on circle.Moved after spacing is less than the TSV1 of processing request, completed the arrangement that TSV the most repeatedly appears in TSV in set B.After arrangement completes, delete the TSV couple of the TSV that in set B, occurrence number is maximum.
S2, S3, S4 step are carried out in circulation, until the logarithm of TSV is 0 in set, just jump out Optimization Steps.
Fig. 4 is the domain result after optimizing, and the distance without any two TSV in domain is less than given minimum spacing requirement, and the position of TSV is optimized.
Claims (2)
- The distance optimization method of TSV position in 1.3D integrated circuit autoplacement, is characterized in that: the TSV that spacing in circuit is less than to processes spacing flicks, and claims this method for flicking method; Arrange one by one the TSV that all spacing are less than processes spacing, make their spacing meet the constraint of processes spacing;Concrete steps are as follows:S1, sets up 3D integrated circuit diagram rectangular coordinate system: in the 3D integrated circuit diagram of TSV Primary Location, set up rectangular coordinate system A, coordinate system A sets up along the edge of domain, and its transverse axis is set up along the horizontal direction of domain, and the longitudinal axis is set up along the vertical direction of domain;S2, sets up the TSV pair set B that spacing is less than processes spacing: calculate respectively the coordinate of each TSV in coordinate system, obtain the coordinate points of each TSV in domain; Utilize the distance computing formula of plane right-angle coordinate to calculate the distance of the coordinate of each TSV and the coordinate of other all TSV, try to achieve arbitrarily the distance of TSV between two; Calculate after the distance between all TSV, set up the right set B of TSV that spacing is between two less than processes spacing; Then the TSV that spacing is less than to processes spacing is to putting into set B, and wherein said TSV is to comprising the coordinate of two TSV; The right number of TSV in set of computations B,S3: when the number that TSV is right in set B equals 0, show, without being optimized again, to jump out optimizing process; When being greater than 0, carries out the number that TSV is right in set B S4,S4, flicks and processes the TSV couple that spacing is less than processes spacing: the maximum TSV of TSV centering occurrence number that chooses set B is basic point; Using basic point as the center of circle, and the processes spacing of take is drawn circle as radius, will drop on all TSV in this circle on the circumference that radially moves on to this circle of circle;S2, S3, S4 are carried out in circulation, until TSV is zero to number in set B, jump out optimizing process.
- The distance optimization device of TSV position in 2.3D integrated circuit autoplacement, is characterized in that: it includes:Input block: for setting up 3D integrated circuit diagram rectangular coordinate system: the 3D integrated circuit diagram of TSV Primary Location is set up rectangular coordinate system A, coordinate system A sets up along the edge of domain, its transverse axis is set up along the horizontal direction of domain, and the longitudinal axis is set up along the vertical direction of domain;TSV is to storage unit: the TSV pair set B that is less than processes spacing for setting up spacing: calculate respectively each TSV at the coordinate of coordinate system, obtain the coordinate points of each TSV in domain; Utilize the distance computing formula of plane right-angle coordinate to calculate the distance of the coordinate of each TSV and the coordinate of other all TSV, try to achieve arbitrarily the distance of TSV between two; Calculate after the distance between all TSV, set up the right set B of TSV that spacing is between two less than processes spacing; Then the TSV that spacing is less than to processes spacing is to putting into set B, and wherein said TSV is to comprising the coordinate of two TSV;Judging unit: carry out when judging that the right number of number TSV in set B that TSV TSV is right is greater than 0 and optimize, when the number that TSV is right in set B equals 0, show without being optimized again;Flick unit: for flicking, process the TSV couple that spacing is less than processes spacing: the maximum TSV of TSV centering occurrence number that chooses set B is basic point; Using basic point as the center of circle, and the processes spacing of take is drawn circle as radius, will drop on all TSV in this circle on the circumference that radially moves on to this circle of circle.
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| CN103678770B (en) * | 2013-11-13 | 2016-08-17 | 北京工业大学 | TSV position autoplacement method in a kind of 3D integrated circuit based on noise reduction purpose |
| CN103678771B (en) * | 2013-11-13 | 2016-08-17 | 北京工业大学 | Power/groundTSV position autoplacement method in a kind of 3D integrated circuit |
| CN103560097B (en) * | 2013-11-20 | 2016-04-27 | 中国科学院深圳先进技术研究院 | Routing path optimization method in a kind of three-dimensional chip |
| CN103886148B (en) * | 2014-03-14 | 2017-02-01 | 北京工业大学 | Automatic layout method and system for positions of heat through holes in 3D integrated circuit |
| CN103870652B (en) * | 2014-03-24 | 2017-01-25 | 北京工业大学 | TSV automatic insertion method of three-dimensional integrated circuit |
| CN111865782B (en) * | 2019-04-29 | 2021-08-06 | 清华大学 | Three-dimensional integrated circuit and routing method |
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| US8103996B2 (en) * | 2008-06-24 | 2012-01-24 | Cadence Design Systems, Inc. | Method and apparatus for thermal analysis of through-silicon via (TSV) |
| US8014166B2 (en) * | 2008-09-06 | 2011-09-06 | Broadpak Corporation | Stacking integrated circuits containing serializer and deserializer blocks using through silicon via |
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| CN102414684A (en) * | 2009-04-24 | 2012-04-11 | 新思科技有限公司 | Method and apparatus for placing transistors in proximity to through-silicon vias |
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