CN103676747B - A kind of flat finder communication control system - Google Patents
A kind of flat finder communication control system Download PDFInfo
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- CN103676747B CN103676747B CN201310717463.5A CN201310717463A CN103676747B CN 103676747 B CN103676747 B CN 103676747B CN 201310717463 A CN201310717463 A CN 201310717463A CN 103676747 B CN103676747 B CN 103676747B
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Abstract
The embodiment of the invention discloses a kind of flat finder communication control system, specifically include FPGA system and time-sequence control mode, described FPGA system has been used for the information communication with described PC and data transmission, and control the concrete action executing of described time-sequence control mode, described FPGA system specifically includes: Gigabit Ethernet module, MicroBlaze module, data control interface module and SDRAM control module.This flat panel detector can not only improve the stability of total system, save layout area, improves the reliability and maintainability of code, and can complete collection and the transmission of image within the shorter time, shortens the image waiting time.
Description
Technical field
The present invention relates to X-ray detection technical field, particularly relate to a kind of flat finder communication control system.
Background technology
At present, in X-ray detection technical field, the main circuit of flat panel detector designs commonly used FPGA(Field
Programmable Gate Array, field programmable gate array) combine MCU(Micro Control Unit, microcontroller list
Unit) mechanism realize the control to whole flat panel detector, wherein FPGA is commonly used to and receives the instruction of upper strata MCU and come
Complete the various substantial action of flat panel detector, including the generation of Timing driver pulse, the control of generator exposure of TFT screen
The functions such as the configuration of system, the refreshing of TFT screen, the collection of view data and various depositor；And MCU such as ARM,
Power PC etc. realizes the control of communication transfer, completes the parsing of order various to PC, performs control to and communication device
The foundation etc. of system, completes the action control to lower floor FPGA and status poll, completes the transmission of view data simultaneously.
Although the scheme of prior art can ensure that the acquisition performance of flat panel detector, but adds development cost, and increases
Layout difficulty, extends the development time.
Summary of the invention
It is an object of the invention to provide a kind of flat finder communication control system, can not only improve total system stability,
Save layout area, improve the reliability and maintainability of code, and the collection of image can be completed within the shorter time
And transmission, shorten the image waiting time.
A kind of flat finder communication control system, described communication control system includes FPGA system and time-sequence control mode,
Wherein:
Described FPGA system has been used for the information communication with described PC and data transmission, and controls described sequencing contro mould
The concrete action executing of block, described FPGA system specifically includes:
Gigabit Ethernet module, for reception and the transmission of PC control command, and carries out view data transmission；
MicroBlaze module, for resolving the PC control command that described Gigabit Ethernet module receives, coordinates to control respectively
The priority action of individual module；
Data control interface module, for receiving the instruction of described MicroBlaze module, controls described time-sequence control mode
Action, and inquire about its operating state, and receive the view data from described time-sequence control mode；
SDRAM control module, for caching the view data from described data control interface module, and the figure that will cache
As data are sent to described PC by described Gigabit Ethernet module.
As seen from the above technical solution provided by the invention, this flat panel detector can not only improve stablizing of total system
Property, save layout area, improve the reliability and maintainability of code, and image can be completed within the shorter time
Gather and transmission, shorten the image waiting time.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, required use in embodiment being described below
Accompanying drawing is briefly described, it should be apparent that, the accompanying drawing in describing below is only some embodiments of the present invention, for
From the point of view of those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain according to these accompanying drawings
Other accompanying drawings.
The structural representation of the flat finder communication control system that Fig. 1 is provided by the embodiment of the present invention；
Fig. 2 show the structural representation of MicroBlaze module described in the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly and completely
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on
Embodiments of the invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into protection scope of the present invention.
Method described in the embodiment of the present invention is based on FPGA system, by the soft core of microprocessor of MicroBlaze(Xilinx) embedding
Enter the soft core of formula, and combine gigabit Ethernet, it is achieved that the acquisition controlling of flat panel detector and Communication Control.Below in conjunction with
The embodiment of the present invention is described in further detail by accompanying drawing, is illustrated in figure 1 the flat board detection that the embodiment of the present invention is provided
The structural representation of device communication control system, described communication control system mainly includes FPGA system 1 and time-sequence control mode
3, wherein FPGA system 1 is the core of whole flat panel detector, has been used for the information communication with PC 2 and data
Transmission, and control the concrete action executing of time-sequence control mode 3, described FPGA system 1 specifically includes:
Gigabit Ethernet module 11, for reception and the transmission of PC 2 control command, and carries out view data transmission；
MicroBlaze module 12, for resolving PC 2 control command that described Gigabit Ethernet module 11 receives, coordinates control
The priority action of modules processed；
Data control interface module 13, for receiving the instruction of described MicroBlaze module 12, controls described sequencing contro mould
The action of block 3, and inquire about its operating state, and receive the view data from described time-sequence control mode 3；
SDRAM control module 14, for caching the view data from described data control interface module 13, and will caching
View data be sent to described PC 2 by described Gigabit Ethernet module 11.
During implementing, configuration order parameter and communication command parameter are passed through Gigabit Ethernet module by above-mentioned PC 2
11 are sent to MicroBlaze module 12, and the PC control command that PC 2 is sent by MicroBlaze module 12 solves
Analysis, extract design parameter such as: time of exposure, Exposure mode, data read mode, refresh mode etc., thus realize right
The triggering of the concrete action of time-sequence control mode 3；MicroBlaze module 12 performs concrete according to communication command parameter simultaneously
Operation, operates and informs PC 2 by Gigabit Ethernet module 11 again after being finished, thus realize leading to the mutual of PC 2
News.
It addition, when described MicroBlaze module 12 resolves PC 2 control command, by described data control interface module
13 pairs of described time-sequence control modes 3 initiate a series of trigger action, the configuration of depositor in such as time-sequence control mode 3,
The refreshing of flat panel detector electric charge and the reading etc. of view data, and it is carried out the inquiry of state, it is judged that trigger action
Whether complete.
Above-mentioned MicroBlaze module 12 is when coordinating the priority action controlling modules, and detailed process is:
When time-sequence control mode 3 is implemented digital independent action by data control interface module 13 by MicroBlaze module 12
Time, MicroBlaze module 12 simultaneously closes off the command channel in Gigabit Ethernet module 11, opens Gigabit Ethernet module 11
In data channel；
MicroBlaze module 12 activates the performance of SDRAM control module 14 further, will come from time-sequence control mode 3
View data is cached in SDRAM control module 14 by data control interface module 13, and passes through Gigabit Ethernet module
The view data of caching is sent to PC 2 by the data channel in 11, to complete the collection of view data.
Above-mentioned Gigabit Ethernet module 11, data control interface module 13 and SDRAM control module 14 all use FPGA's
Hardware logic realizes, and MicroBlaze module 12 uses Embedded Soft Core, utilizes EDK(Embedded
Development Kit, embedded development external member) the IP cores that used of environmental selection carrys out the most perfect embedded hardware
Processing system, utilizes SDK environment to write software program to realize each function simultaneously, and the combination of software and hardware completes
The allomeric function of MicroBlaze module 12, is carried out specifically the modules comprised in MicroBlaze module 12 below
Bright, it is illustrated in figure 2 the structural representation of MicroBlaze module described in the embodiment of the present invention, MicroBlaze module in Fig. 2
12 farther include:
Judge the command parameter attribute module 121 of PC, for receiving, by GPIO, the command parameter that described PC is sent,
And distinguish command parameter attribute by the flag bit made an appointment, complete the classification of command parameter；Here, PC with
The command parameter of FPGA is divided into configuration order parameter and communication command parameter, and configuration order parameter comprises various configuration information and uses
In configuring the different state of lower floor and characteristic, communication command parameter represents the different instruction that PC issues；
The parsing module 122 of command parameter, gives different function codes in advance to each bit position of command parameter, is receiving
After command parameter, extract each bit bit function code, and resolve to practical significance；Such as time of exposure, Exposure mode,
Data read mode, refresh mode etc., thus ensure effective execution that PC configures, mentioned order parameter comprise various
Configuration information is for configuring the different state of lower floor and characteristic；
The open and close control module 123 of peripheral module, is used for utilizing GPIO to control each peripheral module in the different acquisition stage
State, and each GPIO control disparate modules different conditions；Such as when PC carries out communication command with FPGA,
SDRAM module to be closed；When FPGA carries out view data transmission with PC, SDRAM module is in out
Opening state, in Gigabit Ethernet module, order transmission channel is closed etc. simultaneously, thus ensures that modules has
What bar was the most disorderly performs operation, it is ensured that carrying out in order of gatherer process；
Action triggers and operating state enquiry module 124, be used for pre-setting address register, and wherein different address correspondence is not
Same operation, and in same address, pre-set different movement contents；And utilize the status register pre-set
Monitor the implementation status of action and record renewal constantly；This module is primarily directed to lower floor's time-sequence control mode, it is ensured that all
The actions such as the reading such as the configuration of depositor in time-sequence control mode, the refreshing of flat panel detector electric charge and view data
Accurately trigger, the implementation status of this action can be understood constantly, it is ensured that the promptness of next action triggers simultaneously；
The execution of communication command parameter and respond module 125, for the different meanings according to predefined communication command parameter
Perform different operations, and the command response receiving respective sense confirms parameter；The execution of this communication command parameter and sound
Answer module raises positioning problems mechanism, it is possible to during orientation problem occurs in the execution of which part operation, reduce debugging
Scope, produced problem in contributing to efficiently solving to gather, this module is to be realized by read-write GPIO, it is ensured that PC
And the high efficiency communication between FPGA.
In sum, the flat panel detector that the embodiment of the present invention is provided can not only improve the stability of total system, saving
Layout area, improves the reliability and maintainability of code, and can complete collection and the biography of image within the shorter time
Defeated, shorten the image waiting time, the lifting for flat panel detector overall performance provides sound assurance.
The above, the only present invention preferably detailed description of the invention, but protection scope of the present invention is not limited thereto,
Any those familiar with the art in the technical scope of present disclosure, the change that can readily occur in or replace
Change, all should contain within protection scope of the present invention.Therefore, protection scope of the present invention should be with claims
Protection domain is as the criterion.
Claims (3)
1. a flat finder communication control system, it is characterised in that described communication control system includes FPGA system
And time-sequence control mode, wherein:
Described FPGA system has been used for the information communication with PC and data transmission, and controls described time-sequence control mode
Concrete action executing, described FPGA system specifically includes:
Gigabit Ethernet module, for reception and the transmission of PC control command, and carries out view data transmission；
MicroBlaze module, for resolving the PC control command that described Gigabit Ethernet module receives, coordinates to control respectively
The priority action of individual module；
Data control interface module, for receiving the instruction of described MicroBlaze module, controls described time-sequence control mode
Action, and inquire about its operating state, and receive the view data from described time-sequence control mode；
SDRAM control module, for caching the view data from described data control interface module, and the figure that will cache
As data are sent to described PC by described Gigabit Ethernet module；
Wherein, described MicroBlaze module, when coordinating the priority action controlling modules, specifically includes:
When described time-sequence control mode is implemented digital independent by described data control interface module by described MicroBlaze module
During action, described MicroBlaze module simultaneously closes off the command channel in described Gigabit Ethernet module, and opens described thousand
Data channel in mbit ethernet module；
Described MicroBlaze module activates the performance of described SDRAM control module further, will come from described sequential control
The view data of molding block is cached in described SDRAM control module by described data control interface module, and passes through institute
The view data of caching is sent to described PC by the data channel stated in Gigabit Ethernet module, to complete view data
Gather.
Flat finder communication control system the most according to claim 1, it is characterised in that
When described MicroBlaze module resolves PC control command, by described data control interface module to time described
Sequence control module initiates a series of trigger action.
Flat finder communication control system the most according to claim 1 or claim 2, it is characterised in that described MicroBlaze
Module farther includes:
Judge the command parameter attribute module of PC, for receiving, by GPIO, the command parameter that described PC is sent, and lead to
Cross the flag bit made an appointment to distinguish command parameter attribute, to complete the classification of command parameter；
The parsing module of command parameter, gives different function codes in advance to each bit position of described command parameter, is connecing
After receiving described command parameter, extract each bit bit function code, and resolve to practical significance；
The open and close control module of peripheral module, for utilizing GPIO to control each peripheral module in the different acquisition stage
State, and the different conditions of each GPIO control disparate modules；
Action triggers and operating state enquiry module, be used for pre-setting address register, and wherein different address correspondence is different
Operation, and in same address, pre-set different movement contents；And utilize the status register pre-set
The implementation status of monitoring action also records renewal constantly；
The execution of communication command parameter and respond module, come for the different meanings according to predefined communication command parameter
Perform different operations, and the command response receiving respective sense confirms parameter.
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| CN201310717463.5A CN103676747B (en) | 2013-12-23 | 2013-12-23 | A kind of flat finder communication control system |
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| CN201310717463.5A CN103676747B (en) | 2013-12-23 | 2013-12-23 | A kind of flat finder communication control system |
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| CN103676747A CN103676747A (en) | 2014-03-26 |
| CN103676747B true CN103676747B (en) | 2017-01-04 |
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| US20010011318A1 (en) * | 1997-02-27 | 2001-08-02 | Vishram P. Dalvi | Status indicators for flash memory |
| CN1920806A (en) * | 2005-08-23 | 2007-02-28 | 成都联星微电子有限公司 | Testing method for programmable equipment and programming method |
| CN100455263C (en) * | 2006-04-26 | 2009-01-28 | 东软飞利浦医疗设备***有限责任公司 | X-ray machine image processing device |
| CN202454068U (en) * | 2011-12-27 | 2012-09-26 | 成都众询科技有限公司 | High-speed data acquisition system based on gigabit Ethernet |
| CN103368663B (en) * | 2012-03-28 | 2015-08-05 | 普天信息技术研究院有限公司 | A kind of commissioning method for testing for radio frequency remote base station and system |
| CN202841350U (en) * | 2012-06-29 | 2013-03-27 | 上海奕瑞光电子科技有限公司 | System on chip for X-ray flat panel detector |
| CN202995032U (en) * | 2012-12-28 | 2013-06-12 | 成都天奥信息科技有限公司 | Platform realizing continuous wave navigation radar data high speed transmission based on Microblaze |
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Address after: 100016 Jiuxianqiao East Road, Beijing, No. 9 A3 Patentee after: Beijing Wandong Medical Polytron Technologies Inc Address before: 100016 Jiuxianqiao East Road, Beijing, No. 9 A3 Patentee before: Huarun Wandong Medical Equipment Co., Ltd. |