CN103645881B - Execution controller for floating-point number addition/subtractionoperation operation - Google Patents
Execution controller for floating-point number addition/subtractionoperation operation Download PDFInfo
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- CN103645881B CN103645881B CN201310681509.2A CN201310681509A CN103645881B CN 103645881 B CN103645881 B CN 103645881B CN 201310681509 A CN201310681509 A CN 201310681509A CN 103645881 B CN103645881 B CN 103645881B
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Abstract
A kind of execution controller for floating-point number addition/subtractionoperation operation, including floating-point operation number configuration control module, floating number plus/minus arithmetical unit, pulsqe distributor, result output control module；This execution controller application FPGA design Hard link control circuit, perform controller to be chosen by system, starting impulse allotter, under the time sequential pulse of internal pulses allotter controls, independently complete to participate in the option and installment of 2 operands of computing, the latch of operation result, it is not necessary to system applies sequencing contro pulse to the calculation process process performing controller.This execution controller is able to carry out 2 operands and both is from the computing of system data bus, it also is able to perform the result that 1 operand is computing last time, every ordering calculation is avoided to terminate the process being required for being write back by operation result, and during floating number plus/minus method computing, system can read the result of computing last time parallel from execution controller, and the system that improves performs the speed of floating number plus/minus operational order sequence.
Description
Technical field
The present invention relates to a kind of execution controller for floating-point number addition/subtractionoperation operation, particularly relate to a kind of based on using FPGA parallel work-flow circuit hardwired floating number plus/minus arithmetic control circuit and sequential control method thereof.
Background technology
Along with data operational precision requirement is improved constantly and the continuous expansion of numerical value operating range by modern science and technology so that the application of floating-point operation gets more and more, more and more important.Floating number plus/minus computing is a most frequent and very important operation during modern science calculating processes, and in modern science calculating processes application, floating number plus/minus operand accounts for more than the 55% of whole floating-point operation.In the instruction system of microprocessor, the instruction of floating number plus/minus method realizes 2 32 the floating number plus/minus computings meeting IEEE754 standard, the design of its floating number plus/minus arithmetical unit generally uses the mode that streamline performs, calculating process is divided into some modules, under the control of the time sequential pulse sent at microprocessor controls, a plurality of floating number plus/minus operational order performs according to sequence of modules, and every ordering calculation in streamline terminates to be required for writing back operation result.But need the operation result applying a upper operational order as the instruction of operand for performed floating number plus/minus method instruction, then the pile line operation of floating number plus/minus computing is ineffective, have impact on the speed that floating number plus/minus operational order performs.And the most much computing is required for the operation result the applying last time operand as this computing, such as plus/minus hybrid operation, if there being multiple continuous print plus/minus computing, such as 7 operands, 6 floating number plus/minus operational orders are needed to be achieved, perform these 6 instructions to need to write back operation result 6 times, operand is transmitted 12 times arithmetical unit to floating number plus/minus, need the address of the timing requirements conversion transmission operand according to data transmission and write back the address of operation result, the process that operation result sends an input of floating number plus/minus computing to as operand and operation result writes back is time-division processing, it is unfavorable for improving the speed that the instruction of arithmetical operation class performs further.
Summary of the invention
It is an object of the invention to provide a kind of execution controller for floating-point number addition/subtractionoperation operation that can independently complete floating number plus/minus calculation function；This execution controller for floating-point number addition/subtractionoperation operation application FPGA design Hard link control circuit, operand is 32 floating numbers meeting IEEE754 standard, it is able to carry out 2 operands and both is from the computing of system data bus, it also is able to perform the computing that 1 operand is operation result last time, every ordering calculation is avoided to terminate the process being required for being write back by operation result, the option and installment of its operand independently completes under the control performing the internal sequential of controller, and during floating number plus/minus method computing, system can perform controller from floating-point plus/minus computing and read the result of computing last time, to overcome the weak point of prior art.
The technical scheme solving above-mentioned technical problem is: a kind of execution controller for floating-point number addition/subtractionoperation operation, relate to a kind of based on using the floating number plus/minus arithmetic control circuit of FPGA circuitry Hard link parallel processing and sequential control method thereof, including floating-point operation number configuration control module, floating number plus/minus arithmetical unit, pulsqe distributor and result output control module；
Described floating-point operation number configuration control module is connected with floating number plus/minus arithmetical unit, pulsqe distributor, result output control module；
Described floating number plus/minus is also connected with result output control module arithmetical unit；
Described pulsqe distributor is also connected with result output control module；
Described floating-point operation number configuration control module comes from the operation result of last time according to the operand 1 of operand type configuration floating number plus/minus arithmetical unit, also come from the floating-point operation number of system data bus DB, under the time sequential pulse of pulsqe distributor output controls, complete the selection of the operand 1 of floating number plus/minus input arithmetical unit, and operand 1 and the configuration of operand 2 and latch；
Operand 1 and operand 2 that floating-point operation number configuration control module is exported arithmetical unit by described floating number plus/minus carry out computing, and according to state given for system's operating mode signal OP, determine and be by addition or subtraction；
Described pulsqe distributor is under conditions of satisfied startup work, according to the type of operand, sends and meets operand 1 and the time sequential pulse of operand 2 configuration, and the latch signal of floating number plus/minus internalarithmetic result；Described pulsqe distributor under conditions of meeting loop start, the work of automatic starting impulse allotter；
Under the effect of the result latch signal that described result output control module exports at pulsqe distributor, operation result is latched, and judged that result of calculation is the most abnormal, if there is exception, sent irq signal；When enabling signal CS and being " 0 ", under the effect of system RD signal, system reads operation result.
Its further technical scheme is: described floating-point operation number configuration control module include gate, operation result depositor, operand register, not gate I or door I or door II and with door I；
One input of described gate is connected with system data bus DB, another input is connected with the operation result outfan of floating number plus/minus arithmetical unit, data output end is connected with the input of operation result depositor, and gating controls input and is connected with the operand type input line of system；When gating control input is " 0 ", what gate gating exported is the operation result of result output control module output；When gating control input is " 1 ", what gate gating exported is the data of system data bus DB input；
The latch pulse input of described operation result depositor is connected with pulsqe distributor, and operand 1 outfan is connected with operand 1 input of floating number plus/minus arithmetical unit；
The input of described operand register and system data bus DB connect, and latch pulse input and the outfan with door I are connected, operand 2 outfan and the operand 2 input connection of floating number plus/minus arithmetical unit；
The input of described not gate I is connected with the operand type input line of system, outfan and an or input connection of door I；
Described or another input of door I and pulsqe distributor connect, outfan and being connected with an input of door I；
Described or door II a input is connected with pulsqe distributor, and another input is connected with the operand type input line of system, outfan and being connected with an input of door I.
Its further technical scheme is: described pulsqe distributor include pulse generator, type register or door III or door IV, not gate II or door V and with door II；
The RESET input of described pulse generator is connected with the reset Rst line of system, start input and or door III outfan connect, loop start input and the outfan with door II are connected, impulsive synchronization input and system clock Clock line connect, type input is connected with the outfan of type register, and pulse 1. outfan is connected with the latch pulse input of operation result depositor or another input of door II；Pulse 2. outfan and or another input connection of door I, the latch pulse input connection of type register；Pulse 3. outfan and an or input connection of door IV；Pulse 4. outfan and or input of door V connect, computing terminates outfan and exports computing end signal to system；
The input of described type register and system operand type input line connect, type register outfan also and or the input of another input of door IV, not gate II connect；Described type register under the effect of pulse 2. trailing edge, the state of latch operation number type；
Two inputs of described or door III enable signal CS line, write signal WR line with system respectively connects；
Described or the outfan of door IV and being connected with an input of door II；
The outfan of described not gate II and or another input connection of door V；
Described or the outfan of door V and being connected with another input of door II；
The described outfan with door II is also connected with result output control module；
Described pulse generator output pulse 1., pulse 2., pulse is 3. 4. Tong Bu with system clock Clock with pulse, i.e. system clock Clock is the lock-out pulse of pulse generation dispensing controller；
When operand type is " 0 ", described pulsqe distributor is under the effect of pulse 2. trailing edge, type register output state is " 0 ", or door V is output as one state, under the effect of pulse 3. trailing edge, or the output of door IV is by " 1 " → " 0 ", then with the output of door II also by " 1 " → " 0 ", as the result latch signal of pulse generator cycle start signal and result output control module；
When operand type is " 1 ", described pulsqe distributor is under the effect of pulse 2. trailing edge, type register output state is " 1 ", or door IV is output as one state, under the effect of pulse 4. trailing edge, or the output of door V is by " 1 " → " 0 ", then with the output of door II also by " 1 " → " 0 ", as the result latch signal of pulse generator cycle start signal and result output control module；
It is " 0 " when the computing of described pulse generator terminates outfan, when CS is " 0 ", under the trailing edge effect of WR signal, start input end signal by " 1 " → " 0 ", starting impulse generator works, and after pulse generator is activated work, puts computing end signal outfan for " 1 "；If starting input is " 0 ", loop start input is worked by " 1 " → " 0 ", starting impulse generator；If starting input end signal is " 1 ", loop start input end signal is by " 1 " → " 0 ", computing end signal is sent to system, pulse generator quits work, pulse 1., pulse 2., pulse 3. with pulse outfan 4. all in for one state, computing terminates outfan for " 0 " state；When the RESET input is " 0 ", reseting pulse generator, pulse 1., pulse 2., pulse 3. with pulse outfan 4. all in for one state, computing terminates outfan for " 0 " state.
Its further technical scheme is: described result output control module includes the control of result output register, computing abnormality mark, 32 triple gate groups and or door VI；
The operation result input of described result output register is connected with the outfan of floating number plus/minus arithmetical unit, operation result input, an input of gate that operation result outfan and the input of 32 triple gate groups, computing abnormality mark control connect, and result latch input terminal and the outfan with door II are connected；
Described computing abnormality mark control result latch input terminal and be connected with the outfan of door II；Outfan output interrupt request singal IRQ, when operation result occurs abnormal, outfan sends interrupt request singal IRQ to system；
The outfan of described 32 triple gate groups is connected with system data bus DB, controls input and or the outfan connection of door VI；
Described or door VI two inputs are connected with enable signal CS, read signal RD respectively；
Described result output control module carries out reading in calculating process enough to go out operation result last time in floating number plus/minus arithmetical unit.
Owing to using above structure, the execution controller for floating-point number addition/subtractionoperation operation of the present invention has the advantages that
One, plus/minus computing has Autonomous Control function
The execution controller for floating-point number addition/subtractionoperation operation of the present invention makes full use of FPGA parallel processing function, perform controller to be chosen by system, starting impulse allotter, execution controller for floating-point number addition/subtractionoperation operation independently completes the option and installment of operand under the time sequential pulse effect of internal pulses allotter, the latch of operation result, it is not necessary to system applies sequencing contro pulse to the calculation process process of execution controller for floating-point number addition/subtractionoperation operation.
Two, the plus/minus computing of 2 type operands, parallel read-out operation result last time are performed
The operand of the execution controller for floating-point number addition/subtractionoperation operation of the present invention is 32 floating numbers meeting IEEE754 standard, can be according to operand type mark, perform 2 operands and both be from the computing of system data bus, it also is able to perform the computing that 1 operand is operation result last time, every ordering calculation is avoided to terminate the process being required for being write back by operation result, and during floating number plus/minus computing, system can perform parallel read-out operation result last time controller from floating-point plus/minus computing.
Three. perform controller cost performance high
The execution controller for floating-point number addition/subtractionoperation operation of the present invention is with the Hard link control circuit of FPGA as core, type according to computing, the option and installment of operand is independently completed under the time sequential pulse effect of internal pulses allotter, the latch of operation result, the system that need not applies sequencing contro pulse to the calculation process process of execution controller for floating-point number addition/subtractionoperation operation, system can perform parallel read-out operation result last time controller from floating addition/subtraction, the system that improves performs the speed of command sequence, when floating number plus/minus computing occurs abnormal, interruption application can be sent to system, there is higher cost performance.
With embodiment, the technical characteristic of the execution controller for floating-point number addition/subtractionoperation operation of the present invention is further described below in conjunction with the accompanying drawings.
Accompanying drawing explanation
The system architecture diagram of the execution controller for floating-point number addition/subtractionoperation operation of Fig. 1: the present invention；
The circuit connection diagram of the floating-point operation number configuration control module of the execution controller for floating-point number addition/subtractionoperation operation of Fig. 2: the present invention；
The circuit connection diagram of the pulsqe distributor of the execution controller for floating-point number addition/subtractionoperation operation of Fig. 3: the present invention；
The circuit connection diagram of the result output control module of the execution controller for floating-point number addition/subtractionoperation operation of Fig. 4: the present invention；
The sequential chart of the operand type 0 of the execution controller for floating-point number addition/subtractionoperation operation of Fig. 5: the present invention；
The sequential chart of the operand type 1 of the execution controller for floating-point number addition/subtractionoperation operation of Fig. 6: the present invention；
The sequential chart of two kinds of operand types of the execution controller for floating-point number addition/subtractionoperation operation of Fig. 7: the present invention；
The floating number multiplication of Fig. 8: the embodiment of the present invention two performs the system architecture diagram of controller.
In figure:
I floating-point operation number configuration control module, II a floating number plus/minus arithmetical unit, II b floating number multiplication device, III pulsqe distributor, IV result output control module；
1 gate, 2 operation result depositors, 3 operand registers, 4 not gates I, 5 or door I, 6 or door II, 7 with door I, 8 pulse generators, 9 type register, 10 or door III, 11 or door IV, 12 not gates II, 13 or door V, 14 with door II, 15 result output registers, 16 computing abnormality marks control, 17 32 triple gate groups, 18 or door VI.
Abbreviation explanation in literary composition:
FPGA-Field Programmable Gate Array, field programmable gate array；
DB-Data Bus, data/address bus；
OP-Operation mode, mode of operation；
CS-Chip Select, sheet choosing or enable, in figure, CS represents " enable signal "；
Clock-clock；
RD-Read, reads, and represents " read signal " in figure；
WR-Write, writes, and represents " write signal " in figure；
IRQ-Interrupt Request, interrupts application, represents " interrupt request singal " in figure；
Rst-Reset, resets.
Detailed description of the invention
Embodiment one:
A kind of execution controller for floating-point number addition/subtractionoperation operation, as shown in Figure 1, adding deduct computing for realizing 2 32 floating numbers meeting IEEE754 standard, this execution controller includes floating-point operation number configuration control module I, floating number plus/minus a arithmetical unit II, pulsqe distributor III and result output control module IV；
Described floating-point operation number configuration control module I is connected with floating number plus/minus a arithmetical unit II, pulsqe distributor III, result output control module IV；
Described floating number plus/minus a arithmetical unit II is also connected with result output control module IV；
Described pulsqe distributor III is also connected with result output control module IV；
Described floating-point operation number configuration control module I comes from the operation result of last time according to the operand 1 of operand type configuration floating number plus/minus a arithmetical unit II, also come from the floating-point operation number of system data bus DB, under the time sequential pulse of pulsqe distributor III output controls, complete the selection of operand 1 of floating number plus/minus a arithmetical unit II input, and operand 1 and the configuration of operand 2 and latch；
Operand 1 and operand 2 that floating-point operation number configuration control module I is exported by described floating number plus/minus a arithmetical unit II carry out computing, and according to state given for system's operating mode signal OP, determine and be by addition or subtraction；
Described pulsqe distributor III is under conditions of satisfied startup work, according to the type of operand, sends and meets operand 1 and the time sequential pulse of operand 2 configuration, and the latch signal of floating number plus/minus a operation result arithmetical unit II；Described pulsqe distributor III under conditions of meeting loop start, the work of automatic starting impulse allotter III；
Under the effect of the result latch signal that described result output control module IV exports at pulsqe distributor III, operation result is latched, and judged that result of calculation is the most abnormal, if there is exception, sent irq signal；When enabling signal CS and being " 0 ", under the effect of system RD signal, system reads operation result.
As in figure 2 it is shown, described floating-point operation number configuration control module I include gate 1, operation result depositor 2, operand register 3, not gate I 4 or door I 5 or door II 6 and with door I 7；
One input of described gate 1 is connected with system data bus DB, another input is connected with the operation result outfan of floating number plus/minus a arithmetical unit II, data output end is connected with the input of operation result depositor 2, and gating controls input and is connected with the operand type input line of system；When gating control input is " 0 ", what gate 1 gating exported is the operation result of result output control module IV output；When gating control input is " 1 ", what gate 1 gating exported is the data of system data bus DB input；
The latch pulse input of described operation result depositor 2 is connected with pulsqe distributor III, and operand 1 outfan is connected with operand 1 input of floating number plus/minus a arithmetical unit II；
The input of described operand register 3 and system data bus DB connect, and latch pulse input and the outfan with door I 7 are connected, and operand 2 input of operand 2 outfan and floating number plus/minus a arithmetical unit II connects；
The input of described not gate I 4 is connected with the operand type input line of system, outfan and an or input connection of door I 5；
Described or another input of door I 5 and pulsqe distributor III connect, outfan and being connected with an input of door I 7；
Described or door II 6 a input is connected with pulsqe distributor III, and another input is connected with the operand type input line of system, outfan and being connected with an input of door I 7.
As it is shown on figure 3, described pulsqe distributor III include pulse generator 8, type register 9 or door III 10 or door IV 11, not gate II 12 or door V 13 and with door II 14；
The RESET input of described pulse generator 8 is connected with the reset Rst line of system, start input and or door III 10 outfan connect, loop start input and the outfan with door II 14 are connected, impulsive synchronization input and system clock Clock line connect, type input is connected with the outfan of type register 9, and pulse 1. outfan is connected with the latch pulse input of operation result depositor 2 or another input of door II 6；Pulse 2. outfan and or door I 5 another input connect, be also connected with the latch pulse input of type register 9；Pulse 3. outfan and an or input connection of door IV 11；Pulse 4. outfan and or input of door V 13 connect, computing terminates outfan and exports computing end signal to system；
The input of described type register 9 and system operand type input line connect, type register outfan also and or the input of another input of door IV 11, not gate II 12 connect；Described type register 9 under the effect of pulse 2. trailing edge, the state of latch operation number type；
Two inputs of described or door III 10 enable signal CS line, write signal WR line with system respectively connects；
Described or the outfan of door IV 11 and being connected with an input of door II 14；
The outfan of described not gate II 12 and or another input connection of door V 13；
Described or the outfan of door V 13 and being connected with another input of door II 14；
The described outfan with door II 14 is also connected with result output control module IV；
Described pulse generator 8 output pulse 1., pulse 2., pulse is 3. 4. Tong Bu with system clock Clock with pulse, i.e. system clock Clock is the lock-out pulse of pulse generation dispensing controller III；
When operand type is " 0 ", described pulsqe distributor III is under the effect of pulse 2. trailing edge, type register 9 output state is " 0 ", or door V 13 is output as one state, under the effect of pulse 3. trailing edge, or the output of door IV 11 is by " 1 " → " 0 ", then with the output of door II 14 also by " 1 " → " 0 ", as the result latch signal of pulse generator 8 cycle start signal and result output control module IV；
When operand type is " 1 ", described pulsqe distributor III is under the effect of pulse 2. trailing edge, type register 9 output state is " 1 ", or door IV 12 is output as one state, under the effect of pulse 4. trailing edge, or the output of door V 13 is by " 1 " → " 0 ", then with the output of door II 14 also by " 1 " → " 0 ", as the result latch signal of pulse generator 8 cycle start signal and result output control module IV；
It is " 0 " when the computing of described pulse generator 8 terminates outfan, when CS is " 0 ", under the trailing edge effect of WR signal, start input end signal by " 1 " → " 0 ", starting impulse generator 8 works, and after pulse generator 8 is activated work, puts computing end signal outfan for " 1 "；If starting input is " 0 ", loop start input is worked by " 1 " → " 0 ", starting impulse generator 8；If starting input end signal is " 1 ", loop start input end signal is by " 1 " → " 0 ", computing end signal is sent to system, if now starting input end signal is " 1 ", pulse generator 8 quits work, pulse 1., pulse 2., pulse 3. with pulse outfan 4. all in for one state, computing terminates outfan for " 0 " state；When the RESET input is " 0 ", reseting pulse generator 8, pulse 1., pulse 2., pulse 3. with pulse outfan 4. all in for one state, computing terminates outfan for " 0 " state.
As shown in Figure 4, described result output control module IV includes that result output register 15, computing abnormality mark control 16,32 triple gate groups 17 and or door VI 18；
The operation result input of described result output register 15 is connected with the outfan of floating number plus/minus a arithmetical unit II, operation result outfan and the input of 32 triple gate groups 17, computing abnormality mark control the operation result input of 16, an input of gate 1 connects, and result latch input terminal and the outfan with door II 14 are connected；
Described computing abnormality mark controls the result latch input terminal of 16 and is connected with the outfan of door II 14；Outfan output interrupt request singal IRQ, when operation result occurs abnormal, outfan sends interrupt request singal IRQ to system；
The outfan of described 32 triple gate groups 17 is connected with system data bus DB, controls input and or the outfan connection of door VI 18；
Described or door VI 18 two inputs are connected with enable signal CS, read signal RD respectively；
Described result output control module IV carries out can reading in calculating process operation result last time at floating number plus/minus a arithmetical unit II.
Embodiment two:
A kind of floating number multiplication performs controller (seeing Fig. 8).
Embodiment two is a kind of mapped structure of the embodiment of the present invention one, and this floating number multiplication performs the basic structure of controller with embodiment one；Institute's difference is: this floating number multiplication performs floating number plus/minus a arithmetical unit II of the floating number multiplication device II b alternative embodiment one of controller, floating number plus/minus a arithmetical unit II of Fig. 1 and Fig. 4 will be changed to floating number multiplication device II b, cancel the OP signal input part of floating number plus/minus a arithmetical unit II of Fig. 1；In the sequential chart of the execution controller for floating-point number addition/subtractionoperation operation of Fig. 5, Fig. 6, Fig. 7, be converted to the clock cycle required for the floating number multiplication time by completing a floating number plus/minus computing clock cycle.
Claims (1)
1. an execution controller for floating-point number addition/subtractionoperation operation, add deduct computing for realizing 2 32 floating numbers meeting IEEE754 standard, it is characterised in that: this execution controller includes floating-point operation number configuration control module (I), floating number plus/minus arithmetical unit (II a), pulsqe distributor (III) and result output control module (IV)；
Described floating-point operation number configuration control module (I) is connected with floating number plus/minus arithmetical unit (II a), pulsqe distributor (III), result output control module (IV)；
Described floating number plus/minus arithmetical unit (II a) is also connected with result output control module (IV)；
Described pulsqe distributor (III) is also connected with result output control module (IV)；
Described floating-point operation number configuration control module (I) comes from the operation result of last time according to the operand 1 of operand type configuration floating number plus/minus arithmetical unit (II a), also come from the floating-point operation number of system data bus DB, under the time sequential pulse control that pulsqe distributor (III) exports, complete the selection of the floating number plus/minus operand 1 that (II a) inputs arithmetical unit, and operand 1 and the configuration of operand 2 and latch；
The described floating number plus/minus operand 1 that floating-point operation number configuration control module (I) is exported by (II a) arithmetical unit and operand 2 carry out computing, and according to state given for system's operating mode signal OP, determine and be by addition or subtraction；
Described pulsqe distributor (III) is under conditions of satisfied startup work, according to the type of operand, sends and meets operand 1 and the time sequential pulse of operand 2 configuration, and the latch signal of floating number plus/minus arithmetical unit (II a) operation result；Described pulsqe distributor (III) under conditions of meeting loop start, the work of automatic starting impulse allotter (III)；
Under the effect of the result latch signal that described result output control module (IV) exports at pulsqe distributor (III), operation result is latched, and judged that result of calculation is the most abnormal, if there is exception, sent irq signal；When enabling signal CS and being " 0 ", under the effect of system RD signal, system reads operation result；
Described floating-point operation number configuration control module (I) include gate (1), operation result depositor (2), operand register (3), not gate I (4) or door I (5) or door II (6) and with door I (7)；
One input of described gate (1) is connected with system data bus DB, another input is connected with the operation result outfan of floating number plus/minus arithmetical unit (II a), data output end is connected with the input of operation result depositor (2), and gating controls input and is connected with the operand type input line of system；When gating control input be " 0 " time, what gate (1) gating exported is the operation result that exports of result output control module (IV)；When gating control input is " 1 ", what gate (1) gating exported is the data of system data bus DB input；
The latch pulse input of described operation result depositor (2) is connected with pulsqe distributor (III), and operand 1 outfan is connected with operand 1 input of floating number plus/minus arithmetical unit (II a)；
The input of described operand register (3) and system data bus DB connect, and latch pulse input and the outfan with door I (7) are connected, and operand 2 input of operand 2 outfan and floating number plus/minus arithmetical unit (II a) connects；
The described input of not gate I (4) is connected with the operand type input line of system, outfan and an or input connection of door I (5)；
Described or another input of door I (5) and pulsqe distributor (III) connect, outfan and being connected with an input of door I (7)；
Described or door II (6) a input is connected with pulsqe distributor (III), and another input is connected with the operand type input line of system, and outfan and another input with door I (7) are connected；
Described pulsqe distributor (III) include pulse generator (8), type register (9) or door III (10) or door IV (11), not gate II (12) or door V (13) and with door II (14)；
The RESET input of described pulse generator (8) is connected with the reset Rst line of system, start input and or door III (10) outfan connect, loop start input and the outfan with door II (14) are connected, impulsive synchronization input and system clock Clock line connect, type input is connected with the outfan of type register (9), and pulse 1. outfan is connected with the latch pulse input of operation result depositor (2) or another input of door II (6)；Pulse 2. outfan and or another input of door I (5), the latch pulse input connection of type register (9)；Pulse 3. outfan and an or input connection of door IV (11)；Pulse 4. outfan and or input of door V (13) connect, computing terminates outfan and exports computing end signal to system；
The input of described type register (9) and system operand type input line connect, type register (9) outfan also and or the input of another input of door IV (11), not gate II (12) connect；Described type register (9) under the effect of pulse 2. trailing edge, the state of latch operation number type；
Two inputs of described or door III (10) enable signal CS line, write signal WR line with system respectively connects；
Described or the outfan of door IV (11) and being connected with an input of door II (14)；
The outfan of described not gate II (12) and or another input connection of door V (13)；
Described or the outfan of door V (13) and another input with door II (14) are connected；
The described outfan with door II (14) is also connected with result output control module (IV)；
The pulse that described pulse generator (8) exports 1., pulse 2., pulse is 3. 4. Tong Bu with system clock Clock with pulse, i.e. system clock Clock is the lock-out pulse of pulsqe distributor (III)；
When operand type is " 0 ", described pulsqe distributor (III) is under the effect of pulse 2. trailing edge, type register (9) output state is " 0 ", or door V (13) is output as one state, under the effect of pulse 3. trailing edge, or the output of door IV (11) is by " 1 " → " 0 ", then with the output of door II (14) also by " 1 " → " 0 ", as pulse generator (8) cycle start signal and the result latch signal of result output control module (IV)；
When operand type is " 1 ", described pulsqe distributor (III) is under the effect of pulse 2. trailing edge, type register (9) output state is " 1 ", or door IV (12) is output as one state, under the effect of pulse 4. trailing edge, or the output of door V (13) is by " 1 " → " 0 ", then with the output of door II (14) also by " 1 " → " 0 ", as pulse generator (8) cycle start signal and the result latch signal of result output control module (IV)；
When the computing of described pulse generator (8) terminates outfan for " 0 ", when CS is " 0 ", under the trailing edge effect of WR signal, start input end signal by " 1 " → " 0 ", starting impulse generator (8) works, after pulse generator (8) is activated work, put computing end signal outfan for " 1 "；If starting input is " 0 ", loop start input is worked by " 1 " → " 0 ", starting impulse generator (8)；If starting input end signal is " 1 ", loop start input end signal is by " 1 " → " 0 ", computing end signal is sent to system, pulse generator (8) quits work, pulse 1., pulse 2., pulse 3. with pulse outfan 4. all in for one state, computing terminates outfan for " 0 " state；When the RESET input is " 0 ", reseting pulse generator (8), pulse 1., pulse 2., pulse 3. with pulse outfan 4. all in for one state, computing terminates outfan for " 0 " state；
Described result output control module (IV) includes that result output register (15), computing abnormality mark control (16), 32 triple gate groups (17) and or door VI (18)；
The operation result input of described result output register (15) is connected with the outfan of floating number plus/minus arithmetical unit (II a), operation result outfan and the input of 32 triple gate groups (17), computing abnormality mark control the operation result input of (16), an input of gate (1) connects, and result latch input terminal and the outfan with door II (14) are connected；
Described computing abnormality mark controls the result latch input terminal of (16) and is connected with the outfan of door II (14)；Outfan output interrupt request singal IRQ, when operation result occurs abnormal, outfan sends interrupt request singal IRQ to system；
The outfan of described 32 triple gate groups (17) is connected with system data bus DB, controls input and or the outfan connection of door VI (18)；
Described or door VI (18) two inputs are connected with enable signal CS, read signal RD respectively；
Described result output control module (IV) carries out can reading in calculating process operation result last time in floating number plus/minus arithmetical unit (II a).
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