CN103645881A - Execution controller for floating-point number addition/subtraction operation - Google Patents
Execution controller for floating-point number addition/subtraction operation Download PDFInfo
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- CN103645881A CN103645881A CN201310681509.2A CN201310681509A CN103645881A CN 103645881 A CN103645881 A CN 103645881A CN 201310681509 A CN201310681509 A CN 201310681509A CN 103645881 A CN103645881 A CN 103645881A
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Abstract
An execution controller for floating-point number addition/subtraction operation comprises a floating-point operand configuration control module, a floating-point number addition/subtraction arithmetic unit, a pulse allocator and a result output control module; the execution controller adopts an FPGA (field programmable gate array) to design a hard-link control circuit, the execution controller is selected by a system, the pulse allocator is started, under the control of timing sequence pulses of the inside pulse allocator, optional configuration of two operands participating in operation is independently finished, latch of an operation result is finished, and the system is not required to apply a sequential control pulse to the operation processing procedure of the execution controller. The execution controller can execute operation in which the two operands are from a system data bus, and further can execute operation in which one operand is the result of last-time operation, so that the process that an operation result is required to be written back when each instruction operation is ended is avoided; and moreover, in a process of floating-point number addition/subtraction operation, the system can read out the result of the last-time operation from the execution controller in parallel, and accordingly, the speed of the system for executing a floating-point number addition/subtraction operation instruction sequence is increased.
Description
Technical field
The present invention relates to a kind of floating number and add/subtract computing implementation controller, relate in particular to a kind of based on adopting the hardwired floating number of FPGA parallel work-flow circuit to add/subtract arithmetic control circuit and sequential control method thereof.
Background technology
Continuous expansion along with modern science and technology improving constantly that data operational precision is required and numerical operation scope, makes the application of floating-point operation more and more, more and more important.It is a very frequent and very important operation in modern science computing that floating number adds/subtract computing, and in modern science computing application, floating number adds/subtracts operand and accounts for the more than 55% of whole floating-point operations.In the order set of microprocessor, add/subtraction instruction of floating number is realized 2 32 floating numbers that meet IEEE754 standard and is added/subtract computing, the mode that the design that its floating number adds/subtract arithmetical unit adopts streamline to carry out conventionally, calculating process is divided into some modules, under the control of the time sequential pulse sending at microprocessor control assembly, many floating numbers add/subtract operational order to be carried out according to sequence of modules, and every ordering calculation in streamline finishes all to need operation result to write back.But need to apply the operation result of a upper operational order as the instruction of operand for add/subtraction instruction of performed floating number, it is ineffective that floating number adds/subtract the stream line operation of computing, affected floating number and added/subtracted the speed that operational order is carried out.And conventionally a lot of computings all need to apply the operation result of last time as the operand of this computing, for example add/subtract hybrid operation, if there are a plurality of continuous computings that add/subtract, such as 7 operands, needing 6 floating numbers to add/subtract operational order is achieved, carrying out these 6 instructions need to write back operation result 6 times, to floating number, add/subtract arithmetical unit transmission operand 12 times, need to require according to the sequential of data transmission the address and the address that writes back operation result of conversion transmission operand, operation result sends as operand that floating number adds/subtract input end of computing and process that operation result writes back is time-division processing to, be unfavorable for further improving the speed that the instruction of arithmetical operation class is carried out.
Summary of the invention
The object of the present invention is to provide and a kind ofly can independently complete the floating number that floating number adds/subtract calculation function and add/subtract computing implementation controller, this floating number adds/subtracts the hard control circuit that connects of computing implementation controller application FPGA design, operand is 32 floating numbers that meet IEEE754 standard, can carry out 2 operands all from the computing of system data bus, also can carry out the computing that 1 operand is operation result last time, avoid every ordering calculation to finish all to need the process that operation result is write back, the option and installment of its operand independently completes under the control of the inner sequential of implementation controller, and in the process of add in floating number/subtraction, system can be from floating add/the subtract result that computing implementation controller is read computing last time, to overcome the weak point of prior art.
The technical scheme solving the problems of the technologies described above is: a kind of floating number adds/subtract computing implementation controller, relate to a kind of floating number based on adopting FPGA circuit firmly to connect parallel processing and add/subtract arithmetic control circuit and sequential control method thereof, comprise that configuration control module is counted in floating-point operation, floating number adds/subtract arithmetical unit, pulsqe distributor and result output control module;
Described floating-point operation is counted configuration control module and floating number and is added/subtract arithmetical unit, pulsqe distributor, result output control module and be connected;
Described floating number adds/subtracts arithmetical unit and is also connected with result output control module;
Described pulsqe distributor is also connected with result output control module;
It is the operation result that comes from last time that the operand 1 that configuration control module adds/subtract arithmetical unit according to operand type configuration floating number is counted in described floating-point operation, still the floating-point operation number that comes from system data bus DB, under the time sequential pulse of pulsqe distributor output is controlled, complete the selection that floating number adds/subtract the operand 1 of arithmetical unit input, and the configuration of operand 1 and operand 2 and latching;
Described floating number adds/subtracts operand 1 and the operand 2 that arithmetical unit counts configuration control module output to floating-point operation and carries out computing, and according to the given state of system's operating mode signal OP, determines and carry out addition or subtraction;
Described pulsqe distributor, meeting under the condition of startup work, according to the type of operand, send the time sequential pulse that meets operand 1 and operand 2 configurations, and floating number adds/subtracts the latch signal of internalarithmetic result; Described pulsqe distributor is meeting under the condition of loop start, automatically the work of starting impulse divider;
Described result output control module, under the effect of the result latch signal of pulsqe distributor output, is latched operation result, and is judged that whether result of calculation is abnormal, if there is extremely, sends irq signal; When enable signal CS is " 0 ", under the effect of system RD signal, system is read operation result.
Its further technical scheme is: described floating-point operation count configuration control module comprise gate, operation result register, operand register, not gate I or door I or door II and with door I;
An input end of described gate is connected with system data bus DB, another input end is connected with the operation result output terminal that floating number adds/subtract arithmetical unit, data output end is connected with the input end of operation result register, and gating control input end is connected with the operand type input line of system; When gating control input end is " 0 ", what gate gating was exported is the operation result of result output control module output; When gating control input end is " 1 ", what gate gating was exported is the data of system data bus DB input;
The latch pulse input end of described operation result register is connected with pulsqe distributor, and operand 1 output terminal is connected with operand 1 input end that floating number adds/subtract arithmetical unit;
The input end of described operand register is connected with system data bus DB, latch pulse input end be connected with the output terminal of door I, operand 2 output terminals are connected with operand 2 input ends that floating number adds/subtract arithmetical unit;
The input end of described not gate I is connected with the operand type input line of system, output terminal with or door I an input end be connected;
Described or door I another input end be connected with pulsqe distributor, output terminal be connected with an input end of door I;
Described or door II an input end be connected with pulsqe distributor, another input end is connected with the operand type input line of system, output terminal be connected with an input end of door I.
Its further technical scheme is: described pulsqe distributor comprise pulse producer, type register or door III or door IV, not gate II or door V and with door II;
The RESET input of described pulse producer is connected with the reset Rst line of system, start input end and or the output terminal of an III be connected, loop start input end be connected with the output terminal of door II, impulsive synchronization input end is connected with system clock Clock line, type input end is connected with the output terminal of type register, and pulse 1. output terminal is connected with the latch pulse input end of operation result register or another input end of door II; Pulse 2. output terminal with or another input end of door I is connected, the connection of the latch pulse input end of type register; Pulse 3. output terminal with or door IV an input end be connected; Pulse 4. output terminal with or an input end of door V is connected, computing finishes output terminal and exports computing end signal to system;
The input end of described type register is connected with system operand type input line, type register output terminal also with or door another input end of IV, the input end of not gate II be connected; Described type register is in pulse 2. under the effect of negative edge, and latch operation is counted the state of type;
Two input ends described or door III are connected with enable signal CS line, the write signal WR line of system respectively;
Described or door IV output terminal be connected with an input end of door II;
The output terminal of described not gate II with or door V another input end be connected;
Described or door V output terminal be connected with another input end of door II;
Described with door II output terminal be also connected with result output control module;
The pulse of described pulse producer output 1., pulse 2., 4. 3. pulse synchronize with system clock Clock with pulse, system clock Clock is the synchronizing pulse of pulse generation dispensing controller;
When operand type is " 0 ", described pulsqe distributor is in pulse 2. under the effect of negative edge, type register output state is " 0 ", or door V is output as one state, in pulse 3. under the effect of negative edge, or door IV output by " 1 " → " 0 ", with the output of door II also by " 1 " → " 0 ", as the result latch signal of pulse producer cycle start signal and result output control module;
When operand type is " 1 ", described pulsqe distributor is in pulse 2. under the effect of negative edge, type register output state is " 1 ", or door IV is output as one state, in pulse 4. under the effect of negative edge, or door V output by " 1 " → " 0 ", with the output of door II also by " 1 " → " 0 ", as the result latch signal of pulse producer cycle start signal and result output control module;
When the computing of described pulse producer finishes output terminal for " 0 ", when CS is " 0 ", under the negative edge effect of WR signal, start input end signal by " 1 " → " 0 ", the work of starting impulse generator, after pulse producer is activated work, puts computing end signal output terminal for " 1 "; If starting input end is " 0 ", loop start input end is by " 1 " → " 0 ", and starting impulse generator is worked; If starting input end signal is " 1 ", loop start input end signal is by " 1 " → " 0 ", to system, send computing end signal, pulse producer quits work, pulse 1., pulse 2., pulse 3. with pulse output terminal 4. all in being one state, it is " 0 " state that computing finishes output terminal; When the RESET input is " 0 ", reseting pulse generator, pulse 1., pulse 2., pulse 3. with pulse output terminal 4. all in being one state, it is " 0 " state that computing finishes output terminal.
Its further technical scheme is: described result output control module comprises that result output register, computing abnormality mark are controlled, 32 triple gate groups and or door VI;
The output terminal that operation result input end and the floating number of described result output register adds/subtract arithmetical unit is connected, the operation result input end that the input end of operation result output terminal and 32 triple gate groups, computing abnormality mark are controlled, an input end of gate are connected, result latch input terminal be connected with the output terminal of door II;
The result latch input terminal that described computing abnormality mark is controlled be connected with the output terminal of door II; Output terminal output interrupt request singal IRQ, when operation result occurs that when abnormal, output terminal sends interrupt request singal IRQ to system;
The output terminal of described 32 triple gate groups is connected with system data bus DB, control input end with or door VI output terminal be connected;
Two input ends described or door VI are connected with enable signal CS, read signal RD respectively;
Described result output control module adds/subtract arithmetical unit in floating number can read enough to go out operation result last time in carrying out calculating process.
Owing to adopting above structure, the present invention's floating number adds/subtracts computing implementation controller and has following beneficial effect:
One, adding/subtract computing has from main control function
The present invention's floating number adds/subtracts computing implementation controller and makes full use of FPGA parallel processing function, implementation controller is chosen by system, starting impulse divider, floating number adds/subtracts the option and installment of computing implementation controller autonomous complete operation number under the time sequential pulse effect of internal pulses divider, latching of operation result, the calculation process process that does not need system to add/subtract computing implementation controller to floating number applies sequential control pulse.
That two, carries out 2 types of operands adds/subtracts computing, parallel read-out operation result last time
The operand that the present invention's floating number adds/subtract computing implementation controller is 32 floating numbers that meet IEEE754 standard, can be according to operand type sign, carry out 2 operands all from the computing of system data bus, also can carry out the computing that 1 operand is operation result last time, avoid every ordering calculation to finish all to need the process that operation result is write back, and in floating number, add/subtract in the process of computing, system can be from floating add/subtract parallel read-out operation result last time computing implementation controller.
Three. implementation controller cost performance is high
The present invention's floating number adds/subtract computing implementation controller, and to take the hard connection control circuit of FPGA be core, according to the type of computing, the option and installment of autonomous complete operation number under the time sequential pulse effect of internal pulses divider, latching of operation result, the calculation process process that does not need system to add/subtract computing implementation controller to floating number applies sequential control pulse, system can be from floating add/subtraction implementation controller parallel read-out operation result last time, improved the speed of system fill order sequence, when adding/subtract computing, floating number occurs when abnormal, can send and interrupt application to system, there is higher cost performance.
The technical characterictic that the present invention's floating number is added/subtract computing implementation controller below in conjunction with drawings and Examples is further described.
Accompanying drawing explanation
Fig. 1: the present invention's floating number adds/subtract the system architecture diagram of computing implementation controller;
Fig. 2: the circuit connection diagram of configuration control module is counted in the floating-point operation that the present invention's floating number adds/subtract computing implementation controller;
Fig. 3: the present invention's floating number adds/subtract the circuit connection diagram of the pulsqe distributor of computing implementation controller;
Fig. 4: the present invention's floating number adds/subtract the circuit connection diagram of the result output control module of computing implementation controller;
Fig. 5: the present invention's floating number adds/subtract the sequential chart of the operand type 0 of computing implementation controller;
Fig. 6: the present invention's floating number adds/subtract the sequential chart of the operand type 1 of computing implementation controller;
Fig. 7: the present invention's floating number adds/subtract the sequential chart of two kinds of operand types of computing implementation controller;
Fig. 8: the system architecture diagram of the floating number multiplication implementation controller of the embodiment of the present invention two.
In figure:
Configuration control module is counted in I-floating-point operation, and II a-floating number adds/subtract arithmetical unit, II b-floating number multiplication device, III-pulsqe distributor, IV-result output control module;
1-gate, 2-operation result register, 3-operand register, 4-not gate I, 5-or door I, 6-or door II, 7-with door an I, 8-pulse producer, 9-type register, 10-or door III, 11-or door IV, 12-not gate II, 13-or door V, 14-with II, 15-result output register, 16-computing abnormality mark is controlled, 17-32 triple gate groups, 18-or door VI.
Abbreviation explanation in literary composition:
FPGA-Field Programmable Gate Array, field programmable gate array;
DB-Data Bus, data bus;
OP-Operation mode, mode of operation;
CS-Chip Select, sheet selects or enables, CS representative " enable signal " in figure;
Clock-clock;
RD-Read, reads, representative " read signal " in figure;
WR-Write, writes, representative " write signal " in figure;
IRQ-Interrupt Request, interrupts application, representative " interrupt request singal " in figure;
Rst-Reset, resets.
Embodiment
Embodiment mono-:
A kind of floating number adds/subtracts computing implementation controller, as shown in Figure 1, for realizing the computing that adds deduct of 2 32 floating numbers that meet IEEE754 standard, this implementation controller comprises that configuration control module I is counted in floating-point operation, floating number adds/subtract arithmetical unit II a, pulsqe distributor III and result output control module IV;
Described floating-point operation is counted configuration control module I and floating number and is added/subtract arithmetical unit II a, pulsqe distributor III, result output control module IV and be connected;
Described floating number adds/subtracts arithmetical unit II a and is also connected with result output control module IV;
Described pulsqe distributor III is also connected with result output control module IV;
It is the operation result that comes from last time that the operand 1 that configuration control module I adds/subtract arithmetical unit II a according to operand type configuration floating number is counted in described floating-point operation, still the floating-point operation number that comes from system data bus DB, under the time sequential pulse of pulsqe distributor III output is controlled, complete the selection that floating number adds/subtract the operand 1 of arithmetical unit II a input, and the configuration of operand 1 and operand 2 and latching;
Described floating number adds/subtracts operand 1 and the operand 2 that arithmetical unit II a counts configuration control module I output to floating-point operation and carries out computing, and according to the given state of system's operating mode signal OP, determines and carry out addition or subtraction;
Described pulsqe distributor III, meeting under the condition of startup work, according to the type of operand, send the time sequential pulse that meets operand 1 and operand 2 configurations, and floating number adds/subtracts the latch signal of arithmetical unit II a operation result; Described pulsqe distributor III is meeting under the condition of loop start, automatically the work of starting impulse divider III;
Described result output control module IV, under the effect of the result latch signal of pulsqe distributor III output, is latched operation result, and is judged that whether result of calculation is abnormal, if there is extremely, sends irq signal; When enable signal CS is " 0 ", under the effect of system RD signal, system is read operation result.
As shown in Figure 2, described floating-point operation count configuration control module I comprise gate 1, operation result register 2, operand register 3, not gate I 4 or door I 5 or door II 6 and with door I 7;
An input end of described gate 1 is connected with system data bus DB, another input end is connected with the operation result output terminal that floating number adds/subtract arithmetical unit II a, data output end is connected with the input end of operation result register 2, and gating control input end is connected with the operand type input line of system; When gating control input end is " 0 ", what gate 1 gating was exported is the operation result of result output control module IV output; When gating control input end is " 1 ", what gate 1 gating was exported is the data of system data bus DB input;
The latch pulse input end of described operation result register 2 is connected with pulsqe distributor III, and operand 1 output terminal is connected with operand 1 input end that floating number adds/subtract arithmetical unit II a;
The input end of described operand register 3 is connected with system data bus DB, latch pulse input end be connected with the output terminal of door I 7, operand 2 output terminals are connected with operand 2 input ends that floating number adds/subtract arithmetical unit II a;
The input end of described not gate I 4 is connected with the operand type input line of system, output terminal with or door I 5 an input end be connected;
Described or door I 5 another input end be connected with pulsqe distributor III, output terminal be connected with an input end of door I 7;
Described or door II 6 an input end be connected with pulsqe distributor III, another input end is connected with the operand type input line of system, output terminal be connected with an input end of door I 7.
As shown in Figure 3, described pulsqe distributor III comprise pulse producer 8, type register 9 or door III 10 or door IV 11, not gate II 12 or door V 13 and with door II 14;
The RESET input of described pulse producer 8 is connected with the reset Rst line of system, start input end and or the output terminal of an III 10 be connected, loop start input end be connected with the output terminal of door II 14, impulsive synchronization input end is connected with system clock Clock line, type input end is connected with the output terminal of type register 9, and pulse 1. output terminal is connected with the latch pulse input end of operation result register 2 or another input end of door II 6; Pulse 2. output terminal with or door I 5 another input end be connected, be also connected with the latch pulse input end of type register 9; Pulse 3. output terminal with or door IV 11 an input end be connected; Pulse 4. output terminal with or an input end of door V 13 is connected, computing finishes output terminal and exports computing end signal to system;
The input end of described type register 9 is connected with system operand type input line, type register output terminal also with or door another input end of IV 11, the input end of not gate II 12 be connected; Described type register 9 is in pulse 2. under the effect of negative edge, and latch operation is counted the state of type;
Two input ends described or door III 10 are connected with enable signal CS line, the write signal WR line of system respectively;
Described or door IV 11 output terminal be connected with an input end of door II 14;
The output terminal of described not gate II 12 with or door V 13 another input end be connected;
Described or door V 13 output terminal be connected with another input end of door II 14;
Described with door II 14 output terminal be also connected with result output control module IV;
The pulse of described pulse producer 8 outputs 1., pulse 2., 4. 3. pulse synchronize with system clock Clock with pulse, system clock Clock is the synchronizing pulse of pulse generation dispensing controller III;
When operand type is " 0 ", described pulsqe distributor III is in pulse 2. under the effect of negative edge, type register 9 output states are " 0 ", or door V 13 is output as one state, in pulse 3. under the effect of negative edge, or door IV 11 output by " 1 " → " 0 ", with the output of door II 14 also by " 1 " → " 0 ", as the result latch signal of pulse producer 8 cycle start signals and result output control module IV;
When operand type is " 1 ", described pulsqe distributor III is in pulse 2. under the effect of negative edge, type register 9 output states are " 1 ", or door IV 12 is output as one state, in pulse 4. under the effect of negative edge, or door V 13 output by " 1 " → " 0 ", with the output of door II 14 also by " 1 " → " 0 ", as the result latch signal of pulse producer 8 cycle start signals and result output control module IV;
When the computing of described pulse producer 8 finishes output terminal for " 0 ", when CS is " 0 ", under the negative edge effect of WR signal, start input end signal by " 1 " → " 0 ", 8 work of starting impulse generator, after pulse producer 8 is activated work, put computing end signal output terminal for " 1 "; If starting input end is " 0 ", loop start input end is by " 1 " → " 0 ", and starting impulse generator 8 is worked; If starting input end signal is " 1 ", loop start input end signal is by " 1 " → " 0 ", to system, send computing end signal, if now start input end signal for " 1 ", pulse producer 8 quits work, pulse 1., pulse 2., pulse 3. with pulse output terminal 4. all in being one state, it is " 0 " state that computing finishes output terminal; When the RESET input is " 0 ", reseting pulse generator 8, pulse 1., pulse 2., pulse 3. with pulse output terminal 4. all in being one state, it is " 0 " state that computing finishes output terminal.
As shown in Figure 4, described result output control module IV comprise result output register 15, computing abnormality mark control 16,32 triple gate groups 17 and or door VI 18;
The output terminal that operation result input end and the floating number of described result output register 15 adds/subtract arithmetical unit II a is connected, the input end of operation result output terminal and 32 triple gate groups 17, computing abnormality mark are controlled 16 operation result input end, an input end of gate 1 is connected, result latch input terminal be connected with the output terminal of door II 14;
Described computing abnormality mark is controlled 16 result latch input terminal and is connected with the output terminal of door II 14; Output terminal output interrupt request singal IRQ, when operation result occurs that when abnormal, output terminal sends interrupt request singal IRQ to system;
The output terminal of described 32 triple gate groups 17 is connected with system data bus DB, control input end with or door VI 18 output terminal be connected;
Two input ends described or door VI 18 are connected with enable signal CS, read signal RD respectively;
Described result output control module IV adds/subtract arithmetical unit II a in floating number can read operation result last time in carrying out calculating process.
Embodiment bis-:
A kind of floating number multiplication implementation controller (referring to Fig. 8).
Embodiment bis-is a kind of mapped structures of the embodiment of the present invention one, and the basic structure of this floating number multiplication implementation controller is with embodiment mono-; Institute's difference is: the floating number of the floating number multiplication device II b alternative embodiment one of this floating number multiplication implementation controller adds/subtract arithmetical unit II a, the floating number that is about to Fig. 1 and Fig. 4 adds/subtracts arithmetical unit II a and is changed to floating number multiplication device II b, and the floating number of cancelling Fig. 1 adds/subtract the OP signal input part of arithmetical unit II a; The floating number of Fig. 5, Fig. 6, Fig. 7 adds/subtracts in the sequential chart of computing implementation controller, will complete floating number and add/subtract the computing clock period and be converted to the needed clock period of floating number multiplication time one time.
Claims (4)
1. a floating number adds/subtracts computing implementation controller, for realizing the computing that adds deduct of 2 32 floating numbers that meet IEEE754 standard, it is characterized in that: this implementation controller comprise floating-point operation count configuration control module (I), floating number add/subtract arithmetical unit (II a), pulsqe distributor (III) and result output control module (IV);
Described floating-point operation is counted configuration control module (I) and floating number and is added/subtract arithmetical unit (II a), pulsqe distributor (III), result output control module (IV) be connected;
Described floating number adds/subtract arithmetical unit, and (II a) is also connected with result output control module (IV);
Described pulsqe distributor (III) is also connected with result output control module (IV);
Described floating-point operation is counted configuration control module (I) and according to operand type configuration floating number, is added/subtract arithmetical unit (II operand 1 a) is the operation result that comes from last time, still the floating-point operation number that comes from system data bus DB, under the time sequential pulse of pulsqe distributor (III) output is controlled, complete floating number and add/subtract arithmetical unit (selection of the operand 1 that II a) is inputted, and the configuration of operand 1 and operand 2 and latching;
Described floating number adds/subtract arithmetical unit, and (II operand 1 and the operand 2 of a) floating-point operation being counted to configuration control module (I) output carries out computing, and according to the given state of system's operating mode signal OP, determines and carry out addition or subtraction;
Described pulsqe distributor (III), meeting under the condition of startup work, according to the type of operand, send the time sequential pulse that meets operand 1 and operand 2 configurations, and floating number adds/subtract arithmetical unit, and (II is the latch signal of operation result a); Described pulsqe distributor (III) is meeting under the condition of loop start, automatically the work of starting impulse divider (III);
Described result output control module (IV), under the effect of the result latch signal of pulsqe distributor (III) output, is latched operation result, and is judged that whether result of calculation is abnormal, if there is extremely, sends irq signal; When enable signal CS is " 0 ", under the effect of system RD signal, system is read operation result.
2. floating number as claimed in claim 1 adds/subtracts computing implementation controller, it is characterized in that: described floating-point operation count configuration control module (I) comprise gate (1), operation result register (2), operand register (3), not gate I (4) or door I (5) or door II (6) and with door I (7);
An input end of described gate (1) is connected with system data bus DB, another input end adds/subtract arithmetical unit with floating number, and (II operation result output terminal a) is connected, data output end is connected with the input end of operation result register (2), and gating control input end is connected with the operand type input line of system; When gating control input end is " 0 ", what gate (1) gating was exported is the operation result of result output control module (IV) output; When gating control input end is " 1 ", what gate (1) gating was exported is the data of system data bus DB input;
The latch pulse input end of described operation result register (2) is connected with pulsqe distributor (III), and operand 1 output terminal adds/subtract arithmetical unit with floating number, and (II operand 1 input end a) is connected;
The input end of described operand register (3) is connected with system data bus DB, latch pulse input end be connected with the output terminal of door I (7), operand 2 output terminals add/subtract arithmetical unit with floating number, and (II operand 2 input ends a) are connected;
The input end of described not gate I (4) is connected with the operand type input line of system, output terminal with or door I (5) an input end be connected;
Described or door I (5) another input end be connected with pulsqe distributor (III), output terminal be connected with an input end of door I (7);
Described or door II (6) an input end be connected with pulsqe distributor (III), another input end is connected with the operand type input line of system, output terminal be connected with an input end of door I (7).
3. floating number as claimed in claim 1 adds/subtracts computing implementation controller, it is characterized in that: described pulsqe distributor (III) comprise pulse producer (8), type register (9) or door III (10) or door IV (11), not gate II (12) or door V (13) and with door II (14);
The RESET input of described pulse producer (8) is connected with the reset Rst line of system, start input end and or the output terminal of an III (10) be connected, loop start input end be connected with the output terminal of door II (14), impulsive synchronization input end is connected with system clock Clock line, type input end is connected with the output terminal of type register (9), and pulse 1. output terminal is connected with the latch pulse input end of operation result register (2) or another input end of door II (6); Pulse 2. output terminal with or another input end, the latch pulse input end of type register (9) of door I (5) be connected; Pulse 3. output terminal with or door IV (11) an input end be connected; Pulse 4. output terminal with or an input end of door V (13) is connected, computing finishes output terminal and exports computing end signal to system;
The input end of described type register (9) is connected with system operand type input line, type register (9) output terminal also with or another input end, the input end of not gate II (12) of door IV (11) be connected; Described type register (9) is in pulse 2. under the effect of negative edge, and latch operation is counted the state of type;
Two input ends described or door III (10) are connected with enable signal CS line, the write signal WR line of system respectively;
Described or door IV (11) output terminal be connected with an input end of door II (14);
The output terminal of described not gate II (12) with or door V (13) another input end be connected;
Described or door V (13) output terminal be connected with another input end of door II (14);
Described with door II (14) an output terminal be also connected with result output control module (IV);
The pulse of described pulse producer (8) output 1., pulse 2., 4. 3. pulse synchronize with system clock Clock with pulse, system clock Clock is the synchronizing pulse of pulse generation dispensing controller (III);
When operand type is " 0 ", described pulsqe distributor (III) is in pulse 2. under the effect of negative edge, type register (9) output state is " 0 ", or door V (13) is output as one state, in pulse 3. under the effect of negative edge, or door IV (11) output by " 1 " → " 0 ", with the output of door II (14) also by " 1 " → " 0 ", as the result latch signal of pulse producer (8) cycle start signal and result output control module (IV);
When operand type is " 1 ", described pulsqe distributor (III) is in pulse 2. under the effect of negative edge, type register (9) output state is " 1 ", or door IV (12) is output as one state, in pulse 4. under the effect of negative edge, or door V (13) output by " 1 " → " 0 ", with the output of door II (14) also by " 1 " → " 0 ", as the result latch signal of pulse producer (8) cycle start signal and result output control module (IV);
When the computing of described pulse producer (8) finishes output terminal for " 0 ", when CS is " 0 ", under the negative edge effect of WR signal, start input end signal by " 1 " → " 0 ", starting impulse generator (8) work, after pulse producer (8) is activated work, put computing end signal output terminal for " 1 "; If starting input end is " 0 ", loop start input end is by " 1 " → " 0 ", and starting impulse generator (8) is worked; If starting input end signal is " 1 ", loop start input end signal is by " 1 " → " 0 ", to system, send computing end signal, pulse producer (8) quits work, pulse 1., pulse 2., pulse 3. with pulse output terminal 4. all in being one state, it is " 0 " state that computing finishes output terminal; When the RESET input is " 0 ", reseting pulse generator (8), pulse 1., pulse 2., pulse 3. with pulse output terminal 4. all in being one state, it is " 0 " state that computing finishes output terminal.
4. floating number as claimed in claim 1 adds/subtracts computing implementation controller, it is characterized in that: described result output control module (IV) comprise result output register (15), computing abnormality mark control (16), 32 triple gate groups (17) and or a VI (18);
The operation result input end of described result output register (15) adds/subtract arithmetical unit with floating number, and (II output terminal a) is connected, the input end of operation result output terminal and 32 triple gate groups (17), computing abnormality mark are controlled the operation result input end of (16), an input end of gate (1) is connected, result latch input terminal be connected with the output terminal of door II (14);
The result latch input terminal that described computing abnormality mark is controlled (16) be connected with the output terminal of door II (14); Output terminal output interrupt request singal IRQ, when operation result occurs that when abnormal, output terminal sends interrupt request singal IRQ to system;
The output terminal of described 32 triple gate groups (17) is connected with system data bus DB, control input end with or door VI (18) output terminal be connected;
Two input ends described or door VI (18) are connected with enable signal CS, read signal RD respectively;
Described result output control module (IV) adds/subtract arithmetical unit in floating number, and (II a) can be read operation result last time in carrying out calculating process.
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