CN103618525B - A kind of current-mode comparator - Google Patents
A kind of current-mode comparator Download PDFInfo
- Publication number
- CN103618525B CN103618525B CN201310656921.9A CN201310656921A CN103618525B CN 103618525 B CN103618525 B CN 103618525B CN 201310656921 A CN201310656921 A CN 201310656921A CN 103618525 B CN103618525 B CN 103618525B
- Authority
- CN
- China
- Prior art keywords
- nmos tube
- pmos
- grid
- drain electrode
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Amplifiers (AREA)
Abstract
The present invention provides a kind of current-mode comparator, and described current-mode comparator is used for receiving first via electric current and the second road electric current, exports comparative result voltage signal.Described current-mode comparator at least includes: the first differential-mode current produces circuit, is used for receiving first via electric current and the second road electric current, output first via electric current and the difference of the second road electric current；Second differential-mode current produces circuit, is used for receiving first via electric current and the second road electric current, exports the second road electric current and the difference of first via electric current；AB class output-stage circuit, produce circuit with described first differential-mode current and described second differential-mode current produces circuit and is connected, in running order for making described first differential-mode current generation circuit and described second differential-mode current produce circuit Zhong mono-tunnel differential-mode current generation circuit, another road differential-mode current simultaneously produces circuit and is off state, thus realizes comparative result output.Present configuration is simple, and power consumption is extremely low, and system bandwidth is big, compares speed fast.
Description
Technical field
The present invention relates to a kind of microelectronics and solid-state electronic techniques field, particularly relate to signal and realize under current-mode
Comparator relatively.
Background technology
Along with the development of integrated circuit technology, integrated circuit operation voltage is more and more lower, enabling the signal of process
The amplitude of oscillation is more and more less, and the design of voltage-mode signal processing system becomes more complicated and difficult, and voltage-mode signal is converted into electricity
Stream mould processes, and is the effective ways solving this difficult problem.
At present, people have researched and developed a series of current-mode comparator.Such as, BULT.K, and GEELEN.G carries
Go out a kind of current-mode comparator using B class voltage output buffer to constitute, B.M.Min and S.ff.Kim and L.Chen,
B.Shiand C.Lu proposes a kind of current-mode comparator respectively, Traff it is also proposed that cross a kind of current-mode comparator, but all without
Method obtains good compromise between power consumption, speed and precision, there is the problem that power consumption is big.
Summary of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of current-mode comparator, is used for
Solve the compromise problem of existing current-mode comparator sensitivity, speed and power consumption in prior art.
For achieving the above object and other relevant purposes, the present invention provides a kind of current-mode comparator, described current-mode ratio
Relatively device is used for receiving first via electric current and the second road electric current, exports comparative result voltage signal；Described current-mode comparator includes:
First differential-mode current produces circuit, is used for receiving first via electric current and the second road electric current, output first via electric current and the second road electricity
The difference of stream；Second differential-mode current produce circuit, be used for receiving first via electric current and the second road electric current, export the second road electric current and
The difference of first via electric current；AB class output-stage circuit, produces circuit and described second differential mode electricity with described first differential-mode current
The raw circuit of miscarriage is connected, for making described first differential-mode current generation circuit and described second differential-mode current produce in circuit
It is in running order that road differential-mode current produces circuit, and another road differential-mode current simultaneously produces circuit and is off state, thus real
Existing comparative result output.
Preferably, described first differential-mode current generation circuit includes NMOS tube M1, NMOS tube M2, NMOS tube M4, NMOS tube
M5, NMOS tube M11, NMOS tube M12, and PMOS P1, PMOS P2, PMOS P6, PMOS P8；Wherein, described first
Electric current is input to the drain electrode of described NMOS tube M1, and the drain electrode of described NMOS tube M1 is connected with the grid of described NMOS tube M1, described
The grid of NMOS tube M1 is connected with the grid of described NMOS tube M2, the source electrode of described NMOS tube M1 and the source electrode of described NMOS tube M2
Being connected, the drain electrode of described NMOS tube M2 is connected with the drain electrode of described PMOS P1, the drain electrode of described PMOS P1 and described PMOS
The grid of pipe P1 is connected, and the grid of described PMOS P1 is connected with the grid of described PMOS P2, the source electrode of described PMOS P1
It is connected with the source electrode of described PMOS P2；Described second electric current is input to the drain electrode of described NMOS tube M12, described NMOS tube M12
Drain electrode be connected with the grid of described NMOS tube M12, the grid of described NMOS tube M12 is connected with the grid of described NMOS tube M11,
The source electrode of described NMOS tube M12 is connected with the source electrode of described NMOS tube M11, the drain electrode of described NMOS tube M11 and described PMOS
The drain electrode of P8 be connected, the drain electrode of described PMOS P8 is connected with the grid of described PMOS P8, the grid of described PMOS P8 and
The grid of described PMOS P6 is connected, and the source electrode of described PMOS P8 is connected with the source electrode of described PMOS P6；Described PMOS
The drain electrode of P6 is connected with the drain electrode of described NMOS tube M5, and the drain electrode of described NMOS tube M5 is connected with the grid of described NMOS tube M5,
The grid of described NMOS tube M5 is connected with the grid of described NMOS tube M4, the source electrode of described NMOS tube M5 and described NMOS tube M4
Source electrode is connected, and the drain electrode of described NMOS tube M4 is outfan with the junction point of the drain electrode of described PMOS P2.
Preferably, described NMOS tube M1, described NMOS tube M2, described NMOS tube M11, the breadth length ratio of described NMOS tube M12
Ratio be 1:1:1:1；Described NMOS tube M4, the ratio of breadth length ratio of described NMOS tube M5 are 1:1；Described PMOS P1, described
PMOS P2, described PMOS P6, the ratio of breadth length ratio of described PMOS P8 are 1:1:1:1.
Preferably, described second differential-mode current generation circuit includes NMOS tube M1, NMOS tube M2, NMOS tube M8, NMOS tube
M9, NMOS tube M11, NMOS tube M12, and PMOS P1, PMOS P3, PMOS P7, PMOS P8；Wherein, described first
Electric current is input to the drain electrode of described NMOS tube M1, and the drain electrode of described NMOS tube M1 is connected with the grid of described NMOS tube M1, described
The grid of NMOS tube M1 is connected with the grid of described NMOS tube M2, the source electrode of described NMOS tube M1 and the source electrode of described NMOS tube M2
Being connected, the drain electrode of described NMOS tube M2 is connected with the drain electrode of described PMOS P1, the drain electrode of described PMOS P1 and described PMOS
The grid of pipe P1 is connected, and the grid of described PMOS P1 is connected with the grid of described PMOS P3, the source electrode of described PMOS P1
It is connected with the source electrode of described PMOS P3；Described second electric current is input to the drain electrode of described NMOS tube M12, described NMOS tube M12
Drain electrode be connected with the grid of described NMOS tube M12, the grid of described NMOS tube M12 is connected with the grid of described NMOS tube M11,
The source electrode of described NMOS tube M12 is connected with the source electrode of described NMOS tube M11, the drain electrode of described NMOS tube M11 and described PMOS
The drain electrode of P8 be connected, the drain electrode of described PMOS P8 is connected with the grid of described PMOS P8, the grid of described PMOS P8 and
The grid of described PMOS P7 is connected, and the source electrode of described PMOS P8 is connected with the source electrode of described PMOS P7；Described PMOS
The drain electrode of P3 is connected with the drain electrode of described NMOS tube M8, and the drain electrode of described NMOS tube M8 is connected with the grid of described NMOS tube M8,
The grid of described NMOS tube M8 is connected with the grid of described NMOS tube M9, the source electrode of described NMOS tube M8 and described NMOS tube M9
Source electrode is connected, and the drain electrode of described NMOS tube M9 is outfan with the junction point of the drain electrode of described PMOS P7.
Preferably, described NMOS tube M1, described NMOS tube M2, described NMOS tube M11, the breadth length ratio of described NMOS tube M12
Ratio be 1:1:1:1；Described NMOS tube M8, the ratio of breadth length ratio of described NMOS tube M9 are 1:1；Described PMOS P1, described
PMOS P3, described PMOS P7, the ratio of breadth length ratio of described PMOS P8 are 1:1:1:1.
Preferably, described AB class output-stage circuit includes NMOS tube M3, NMOS tube M6, NMOS tube M7, NMOS tube M10, with
And PMOS P4, PMOS P5；The outfan that described first differential-mode current produces circuit is connected with the drain electrode of described NMOS tube M3,
The drain electrode of described NMOS tube M3 is connected with the grid of described NMOS tube M3, described first differential-mode current produce circuit outfan with
The grid of described NMOS tube M6 is connected, and the drain electrode of described NMOS tube M6 is connected with the drain electrode of described PMOS P4, described PMOS
The drain electrode of P4 is connected with the grid of described PMOS P4, and the grid of described PMOS P4 is connected with the grid of described PMOS P5,
The source electrode of described PMOS P4 is connected with the source electrode of described PMOS P5；Described second differential-mode current produce circuit outfan with
The drain electrode of described NMOS tube M10 is connected, and the drain electrode of described NMOS tube M10 is connected with the grid of described NMOS tube M10, and described first
Differential-mode current produces the outfan of circuit and is connected with the grid of described NMOS tube M7, the drain electrode of described NMOS tube M7 and described PMOS
The junction point of the drain electrode of pipe P5 is outfan.
Preferably, the ratio of the breadth length ratio of described PMOS P4, described PMOS P5 is 1:1；Described NMOS tube M3, described
NMOS tube M10, described NMOS tube M6, the ratio of breadth length ratio of described NMOS tube M7 are 1:1:n:n, and wherein, n is any more than 1
Value.
As it has been described above, the current-mode comparator of the present invention, have the advantages that owing to present invention employs AB class defeated
Go out, and without bias current, simple in construction, power consumption be extremely low, comparator in addition to output node without high resistant node, system bandwidth
Greatly, speed is compared fast.Simultaneously as the circuit that the present invention uses has the strongest symmetry, technique change is had the highest Shandong
Rod.
Accompanying drawing explanation
Fig. 1 is shown as the system structure schematic diagram of the present invention a kind of current-mode comparator.
Fig. 2 is shown as the circuit theory schematic diagram A of the present invention a kind of current-mode comparator.
Fig. 3 is shown as the circuit theory schematic diagram B of the present invention a kind of current-mode comparator.
Input/output signal when Fig. 4 is shown as the work of the present invention a kind of current-mode comparator compares schematic diagram.
Element numbers explanation
1 current-mode comparator
11 first differential-mode currents produce circuit
12 second differential-mode currents produce circuit
13 AB class output-stage circuits
Detailed description of the invention
By particular specific embodiment, embodiments of the present invention being described below, those skilled in the art can be by this explanation
Content disclosed by book understands other advantages and effect of the present invention easily.
It should be clear that structure depicted in this specification institute accompanying drawings, ratio, size etc., the most only in order to coordinate description to be taken off
The content shown, understands for those skilled in the art and reads, being not limited to the enforceable qualifications of the present invention, therefore
Do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size, do not affecting the present invention
Under the effect that can be generated by and the purpose that can reach, all should still fall and obtain, at disclosed technology contents, the model that can contain
In enclosing.Meanwhile, in this specification cited as " on ", D score, "left", "right", the term of " middle " and " " etc., be also only
Being easy to understanding of narration, and be not used to limit the enforceable scope of the present invention, being altered or modified of its relativeness, without essence
Under change technology contents, when being also considered as the enforceable category of the present invention.
As it is shown in figure 1, the present invention provides a kind of current-mode comparator 1, described current-mode comparator 1 is used for receiving the first via
Electric current and the second road electric current, export comparative result voltage signal.Described current-mode comparator 1 includes: the first differential-mode current produces
Circuit 11, the second differential-mode current produces circuit 12, AB class output-stage circuit 13.Wherein:
Described first differential-mode current produces circuit 11 and is used for receiving first via electric current and the second road electric current, output first via electricity
Stream and the difference of the second road electric current.First differential-mode current produces a kind of embodiment of circuit 11 as in figure 2 it is shown, described first differential mode
Current generating circuit 11 includes NMOS tube M1, NMOS tube M2, NMOS tube M4, NMOS tube M5, NMOS tube M11, NMOS tube M12, with
And PMOS P1, PMOS P2, PMOS P6, PMOS P8；Wherein, described first electric current is input to the leakage of described NMOS tube M1
Pole, the drain electrode of described NMOS tube M1 is connected with the grid of described NMOS tube M1, the grid of described NMOS tube M1 and described NMOS tube
The grid of M2 be connected, the source electrode of described NMOS tube M1 is connected with the source electrode of described NMOS tube M2, the drain electrode of described NMOS tube M2 and
The drain electrode of described PMOS P1 is connected, and the drain electrode of described PMOS P1 is connected with the grid of described PMOS P1, described PMOS
The grid of P1 is connected with the grid of described PMOS P2, and the source electrode of described PMOS P1 is connected with the source electrode of described PMOS P2；
Described second electric current is input to the drain electrode of described NMOS tube M12, the drain electrode of described NMOS tube M12 and the grid of described NMOS tube M12
The most connected, the grid of described NMOS tube M12 is connected with the grid of described NMOS tube M11, and the source electrode of described NMOS tube M12 is with described
The source electrode of NMOS tube M11 is connected, and the drain electrode of described NMOS tube M11 is connected with the drain electrode of described PMOS P8, described PMOS P8
Drain electrode be connected with the grid of described PMOS P8, the grid of described PMOS P8 is connected with the grid of described PMOS P6, institute
The source electrode of the source electrode and described PMOS P6 of stating PMOS P8 is connected；The drain electrode of described PMOS P6 and the leakage of described NMOS tube M5
The most connected, the drain electrode of described NMOS tube M5 is connected with the grid of described NMOS tube M5, and the grid of described NMOS tube M5 is with described
The grid of NMOS tube M4 is connected, and the source electrode of described NMOS tube M5 is connected with the source electrode of described NMOS tube M4, described NMOS tube M4
Drain electrode is outfan with the junction point of the drain electrode of described PMOS P2.
Specifically, as it is shown on figure 3, described first differential-mode current produces described NMOS tube M1 of circuit 11, described NMOS tube
M2, described NMOS tube M11, the ratio of breadth length ratio of described NMOS tube M12 are 1:1:1:1；Described breadth length ratio refers to a transistor
The ratio of dimensional parameters W (wide) and L (length).Described NMOS tube M4, the ratio of breadth length ratio of described NMOS tube M5 are 1:1；Described
PMOS P1, described PMOS P2, described PMOS P6, the ratio of breadth length ratio of described PMOS P8 are 1:1:1:1
Described second differential-mode current produces circuit 12, is used for receiving first via electric current and the second road electric current, exports the second tunnel
Electric current and the difference of first via electric current.Second differential-mode current produces a kind of embodiment of circuit 12 as in figure 2 it is shown, described second poor
Mould current generating circuit 12 includes NMOS tube M1, NMOS tube M2, NMOS tube M8, NMOS tube M9, NMOS tube M11, NMOS tube M12,
And PMOS P1, PMOS P3, PMOS P7, PMOS P8；Wherein, described first electric current is input to described NMOS tube M1
Drain electrode, the drain electrode of described NMOS tube M1 is connected with the grid of described NMOS tube M1, the grid of described NMOS tube M1 and described NMOS
The grid of pipe M2 is connected, and the source electrode of described NMOS tube M1 is connected with the source electrode of described NMOS tube M2, the drain electrode of described NMOS tube M2
Drain electrode with described PMOS P1 is connected, and the drain electrode of described PMOS P1 is connected with the grid of described PMOS P1, described PMOS
The grid of pipe P1 is connected with the grid of described PMOS P3, the source electrode phase of the source electrode of described PMOS P1 and described PMOS P3
Even；Described second electric current is input to the drain electrode of described NMOS tube M12, the drain electrode of described NMOS tube M12 and described NMOS tube M12
Grid is connected, and the grid of described NMOS tube M12 is connected with the grid of described NMOS tube M11, the source electrode of described NMOS tube M12 and institute
The source electrode stating NMOS tube M11 is connected, and the drain electrode of described NMOS tube M11 is connected with the drain electrode of described PMOS P8, described PMOS
The drain electrode of P8 is connected with the grid of described PMOS P8, and the grid of described PMOS P8 is connected with the grid of described PMOS P7,
The source electrode of described PMOS P8 is connected with the source electrode of described PMOS P7；The drain electrode of described PMOS P3 and described NMOS tube M8
Drain electrode is connected, and the drain electrode of described NMOS tube M8 is connected with the grid of described NMOS tube M8, and the grid of described NMOS tube M8 is with described
The grid of NMOS tube M9 is connected, and the source electrode of described NMOS tube M8 is connected with the source electrode of described NMOS tube M9, described NMOS tube M9
Drain electrode is outfan with the junction point of the drain electrode of described PMOS P7.
Specifically, as it is shown on figure 3, described second differential-mode current produces described NMOS tube M1 of circuit 12, described NMOS tube
M2, described NMOS tube M11, the ratio of breadth length ratio of described NMOS tube M12 are 1:1:1:1；Described NMOS tube M8, described NMOS tube M9
The ratio of breadth length ratio be 1:1；Described PMOS P1, described PMOS P3, described PMOS P7, the breadth length ratio of described PMOS P8
Ratio be 1:1:1:1.
Described AB class output-stage circuit 13, produces circuit 11 and described second differential-mode current with described first differential-mode current
Produce circuit 12 to be connected, be used for making described first differential-mode current produce circuit 11 and described second differential-mode current produces in circuit 12
A road differential-mode current to produce circuit in running order, another road differential-mode current simultaneously produces circuit and is off state, from
And realize comparative result output.A kind of embodiment of described AB class output-stage circuit 13 is as in figure 2 it is shown, described AB class output stage is electric
Road 13 includes NMOS tube M3, NMOS tube M6, NMOS tube M7, NMOS tube M10, and PMOS P4, PMOS P5；Described first poor
The outfan of mould current generating circuit is connected with the drain electrode of described NMOS tube M3, the drain electrode of described NMOS tube M3 and described NMOS tube
The grid of M3 is connected, and the outfan that described first differential-mode current produces circuit is connected with the grid of described NMOS tube M6, described
The drain electrode of NMOS tube M6 is connected with the drain electrode of described PMOS P4, the drain electrode of described PMOS P4 and the grid of described PMOS P4
Being connected, the grid of described PMOS P4 is connected with the grid of described PMOS P5, the source electrode of described PMOS P4 and described PMOS
The source electrode of pipe P5 is connected；The outfan that described second differential-mode current produces circuit is connected with the drain electrode of described NMOS tube M10, described
The drain electrode of NMOS tube M10 is connected with the grid of described NMOS tube M10, and described first differential-mode current produces outfan and the institute of circuit
The grid stating NMOS tube M7 is connected, and the drain electrode of described NMOS tube M7 is outfan with the junction point of the drain electrode of described PMOS P5.
Specifically, as it is shown on figure 3, described PMOS P4 of described AB class output-stage circuit 13, the width of described PMOS P5
The ratio of long ratio is 1:1；Described NMOS tube M3, described NMOS tube M10, described NMOS tube M6, described NMOS tube M7 breadth length ratio it
Ratio is m:m:(m*n): (m*n), i.e. 1:1:n:n, wherein, n is the arbitrary value more than 1；Can change by changing described n value
The speed of described current-mode comparator 1, n can be the arbitrary value more than 1, and n value is the biggest, and described current-mode comparator 1 speed is more
Hurry up, transmission delay is the shortest, but the actual value of n also needs to consider parasitic gate electric current and the current mirror of the metal-oxide-semiconductor of correspondence
Matching.
The implementation of described current-mode comparator 1 is: as Iref > Iin time, described first differential-mode current produce circuit 11
Normal work, the second differential-mode current produces circuit 12 off state；As Iref, < during Iin, described second differential-mode current produces circuit
12 normally work, and the first differential-mode current produces circuit 11 off state；Using AB class output-stage circuit, differential-mode current 1 produces electricity
Road and differential-mode current 2 produce circuit and alternately control, it is achieved comparative result exports.
Specifically, during as in figure 2 it is shown, described current-mode comparator 1 works, according to the mirror image relationship of current mirror, M1 is passed through
Electric current Iref be mirrored to M2, by the current mirror of P1 to P2, P3, in like manner, Iin through M12 mirror image to M11, P8 mirror image to P7,
P6, through the current mirror of M5 to M4, through the current mirror of M8 to M3, is then Iref-Iin by the electric current of M3, passes through M10
Electric current be Iin-Iref.As Iref > Iin time, by the electric current of M3 more than zero, and be zero by the electric current of M10, M9 is in line
Sex work district, thus M6 conducting, M7 turns off, and P4, P5 turn on.So time, the first differential-mode current produces circuit 11 and works, and second is poor
Mould current generating circuit 12 is output as low, the P5 pipe conducting of AB class output-stage circuit 13, and M7 pipe turns off, and comparator is output as high electricity
Flat；In like manner, as Iref, < during Iin, M7 turns on, and M6, P4, P5 turn off, and the second differential-mode current produces circuit 12 and works, the first differential mode
Current generating circuit 11 is output as low, and the P5 pipe of AB class output-stage circuit 13 turns off, and M7 pipe turns on, and comparator is output as low electricity
Flat.
In actual work example, when working as the signal that Iref=5uA, Iin are 0-10uA linear change, described current-mode ratio
The input current Iref of relatively device 1, input current Iin are with current-mode comparator 1 output voltage relation as shown in Figure 4.
In sum, one current-mode comparator of the present invention, have employed AB class output-stage circuit, and without biased electrical
Stream, simple in construction, power consumption is extremely low, and comparator is without high resistant node in addition to output node, and system bandwidth is big, compares speed fast.Meanwhile,
The circuit used due to the present invention has the strongest symmetry, has the highest robustness to technique change.So, the present invention is effective
Overcome various shortcoming of the prior art and have high industrial utilization.
The principle of above-described embodiment only illustrative present invention and effect thereof, not for limiting the present invention.Any ripe
Above-described embodiment all can be modified under the spirit and the scope of the present invention or change by the personage knowing this technology.Cause
This, have usually intellectual such as complete with institute under technological thought without departing from disclosed spirit in art
All equivalences become are modified or change, and must be contained by the claim of the present invention.
Claims (7)
1. a current-mode comparator, it is characterised in that described current-mode comparator is used for receiving first via electric current and the second tunnel
Electric current, exports comparative result voltage signal；Described current-mode comparator at least includes:
First differential-mode current produces circuit, is used for receiving first via electric current and the second road electric current, exports first via electric current and second
The difference of road electric current；
Second differential-mode current produces circuit, is used for receiving first via electric current and the second road electric current, exports the second road electric current and first
The difference of road electric current；
AB class output-stage circuit, produces circuit with described first differential-mode current and described second differential-mode current produces circuit phase
Even, it is used for making described first differential-mode current produce circuit and described second differential-mode current produces the differential-mode current of circuit Zhong mono-tunnel and produces
Raw circuit is in running order, and another road differential-mode current simultaneously produces circuit and is off state, thus it is defeated to realize comparative result
Go out.
Current-mode comparator the most according to claim 1, it is characterised in that: described first differential-mode current produces circuit and includes
NMOS tube M1, NMOS tube M2, NMOS tube M4, NMOS tube M5, NMOS tube M11, NMOS tube M12, and PMOS P1, PMOS
P2, PMOS P6, PMOS P8；Wherein, described first via electric current is input to the drain electrode of described NMOS tube M1, described NMOS tube M1
Drain electrode be connected with the grid of described NMOS tube M1, the grid of described NMOS tube M1 is connected with the grid of described NMOS tube M2, institute
The source electrode of the source electrode and described NMOS tube M2 of stating NMOS tube M1 is connected, the drain electrode of described NMOS tube M2 and the leakage of described PMOS P1
The most connected, the drain electrode of described PMOS P1 is connected with the grid of described PMOS P1, and the grid of described PMOS P1 is with described
The grid of PMOS P2 is connected, and the source electrode of described PMOS P1 is connected with the source electrode of described PMOS P2；Described second road electric current
Being input to the drain electrode of described NMOS tube M12, the drain electrode of described NMOS tube M12 is connected with the grid of described NMOS tube M12, described
The grid of NMOS tube M12 is connected with the grid of described NMOS tube M11, the source electrode of described NMOS tube M12 and described NMOS tube M11
Source electrode is connected, and the drain electrode of described NMOS tube M11 is connected with the drain electrode of described PMOS P8, the drain electrode of described PMOS P8 and described
The grid of PMOS P8 is connected, and the grid of described PMOS P8 is connected with the grid of described PMOS P6, described PMOS P8
Source electrode is connected with the source electrode of described PMOS P6；The drain electrode of described PMOS P6 is connected with the drain electrode of described NMOS tube M5, described
The drain electrode of NMOS tube M5 is connected with the grid of described NMOS tube M5, the grid of described NMOS tube M5 and the grid of described NMOS tube M4
Being connected, the source electrode of described NMOS tube M5 is connected with the source electrode of described NMOS tube M4, the drain electrode of described NMOS tube M4 and described PMOS
The junction point of the drain electrode of pipe P2 is outfan.
Current-mode comparator the most according to claim 2, it is characterised in that: described NMOS tube M1, described NMOS tube M2, institute
The ratio of the breadth length ratio stating NMOS tube M11, described NMOS tube M12 is 1:1:1:1；Described NMOS tube M4, the width of described NMOS tube M5
The ratio of long ratio is 1:1；Described PMOS P1, described PMOS P2, described PMOS P6, the ratio of breadth length ratio of described PMOS P8
For 1:1:1:1.
Current-mode comparator the most according to claim 1, it is characterised in that: described second differential-mode current produces circuit and includes
NMOS tube M1, NMOS tube M2, NMOS tube M8, NMOS tube M9, NMOS tube M11, NMOS tube M12, and PMOS P1, PMOS
P3, PMOS P7, PMOS P8；Wherein, described first via electric current is input to the drain electrode of described NMOS tube M1, described NMOS tube M1
Drain electrode be connected with the grid of described NMOS tube M1, the grid of described NMOS tube M1 is connected with the grid of described NMOS tube M2, institute
The source electrode of the source electrode and described NMOS tube M2 of stating NMOS tube M1 is connected, the drain electrode of described NMOS tube M2 and the leakage of described PMOS P1
The most connected, the drain electrode of described PMOS P1 is connected with the grid of described PMOS P1, and the grid of described PMOS P1 is with described
The grid of PMOS P3 is connected, and the source electrode of described PMOS P1 is connected with the source electrode of described PMOS P3；Described second road electric current
Being input to the drain electrode of described NMOS tube M12, the drain electrode of described NMOS tube M12 is connected with the grid of described NMOS tube M12, described
The grid of NMOS tube M12 is connected with the grid of described NMOS tube M11, the source electrode of described NMOS tube M12 and described NMOS tube M11
Source electrode is connected, and the drain electrode of described NMOS tube M11 is connected with the drain electrode of described PMOS P8, the drain electrode of described PMOS P8 and described
The grid of PMOS P8 is connected, and the grid of described PMOS P8 is connected with the grid of described PMOS P7, described PMOS P8
Source electrode is connected with the source electrode of described PMOS P7；The drain electrode of described PMOS P3 is connected with the drain electrode of described NMOS tube M8, described
The drain electrode of NMOS tube M8 is connected with the grid of described NMOS tube M8, the grid of described NMOS tube M8 and the grid of described NMOS tube M9
Being connected, the source electrode of described NMOS tube M8 is connected with the source electrode of described NMOS tube M9, the drain electrode of described NMOS tube M9 and described PMOS
The junction point of the drain electrode of pipe P7 is outfan.
Current-mode comparator the most according to claim 4, it is characterised in that: described NMOS tube M1, described NMOS tube M2, institute
The ratio of the breadth length ratio stating NMOS tube M11, described NMOS tube M12 is 1:1:1:1；Described NMOS tube M8, the width of described NMOS tube M9
The ratio of long ratio is 1:1；Described PMOS P1, described PMOS P3, described PMOS P7, the ratio of breadth length ratio of described PMOS P8
For 1:1:1:1.
Current-mode comparator the most according to claim 1, it is characterised in that: described AB class output-stage circuit includes NMOS tube
M3, NMOS tube M6, NMOS tube M7, NMOS tube M10, and PMOS P4, PMOS P5；Described first differential-mode current produces circuit
Outfan be connected with the drain electrode of described NMOS tube M3, the drain electrode of described NMOS tube M3 is connected with the grid of described NMOS tube M3,
Described first differential-mode current produce circuit outfan be connected with the grid of described NMOS tube M6, the drain electrode of described NMOS tube M6 and
The drain electrode of described PMOS P4 is connected, and the drain electrode of described PMOS P4 is connected with the grid of described PMOS P4, described PMOS
The grid of P4 is connected with the grid of described PMOS P5, and the source electrode of described PMOS P4 is connected with the source electrode of described PMOS P5；
The outfan that described second differential-mode current produces circuit is connected with the drain electrode of described NMOS tube M10, the drain electrode of described NMOS tube M10
Being connected with the grid of described NMOS tube M10, described first differential-mode current produces the outfan of circuit and the grid of described NMOS tube M7
The most connected, the drain electrode of described NMOS tube M7 is outfan with the junction point of the drain electrode of described PMOS P5.
Current-mode comparator the most according to claim 6, it is characterised in that: described PMOS P4, described PMOS P5
The ratio of breadth length ratio is 1:1；Described NMOS tube M3, described NMOS tube M10, described NMOS tube M6, the breadth length ratio of described NMOS tube M7
Ratio be 1:1:n:n, wherein, n is the arbitrary value more than 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310656921.9A CN103618525B (en) | 2013-12-06 | 2013-12-06 | A kind of current-mode comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310656921.9A CN103618525B (en) | 2013-12-06 | 2013-12-06 | A kind of current-mode comparator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103618525A CN103618525A (en) | 2014-03-05 |
| CN103618525B true CN103618525B (en) | 2016-08-17 |
Family
ID=50169229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310656921.9A Expired - Fee Related CN103618525B (en) | 2013-12-06 | 2013-12-06 | A kind of current-mode comparator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103618525B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106160703B (en) * | 2016-07-20 | 2019-05-24 | 珠海全志科技股份有限公司 | Comparator and relaxor |
| CN106200755A (en) * | 2016-07-27 | 2016-12-07 | 上海华虹宏力半导体制造有限公司 | A kind of current-Mode Circuits of current maxima |
| CN106774584B (en) * | 2017-02-14 | 2018-07-20 | 上海华虹宏力半导体制造有限公司 | A kind of current-mode current minimum circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5471172A (en) * | 1994-08-24 | 1995-11-28 | National Semiconductor Corporation | "AB Cascode" amplifier in an input stage of an amplifier or comparator |
| US6275075B1 (en) * | 1998-12-15 | 2001-08-14 | Hyundai Electronics Industries Co., Ltd. | Current comparator |
| CN1457146A (en) * | 2002-05-07 | 2003-11-19 | 三星电子株式会社 | AB amplifier for controlling static current |
| US7474153B1 (en) * | 2006-05-23 | 2009-01-06 | Marvell International Ltd. | Dual stage source/sink amplifier circuit with quiescent current determination |
| CN102749502A (en) * | 2011-04-22 | 2012-10-24 | 上海贝岭股份有限公司 | Double-current comparison circuit for electric energy metering chip |
-
2013
- 2013-12-06 CN CN201310656921.9A patent/CN103618525B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5471172A (en) * | 1994-08-24 | 1995-11-28 | National Semiconductor Corporation | "AB Cascode" amplifier in an input stage of an amplifier or comparator |
| US6275075B1 (en) * | 1998-12-15 | 2001-08-14 | Hyundai Electronics Industries Co., Ltd. | Current comparator |
| CN1457146A (en) * | 2002-05-07 | 2003-11-19 | 三星电子株式会社 | AB amplifier for controlling static current |
| US7474153B1 (en) * | 2006-05-23 | 2009-01-06 | Marvell International Ltd. | Dual stage source/sink amplifier circuit with quiescent current determination |
| CN102749502A (en) * | 2011-04-22 | 2012-10-24 | 上海贝岭股份有限公司 | Double-current comparison circuit for electric energy metering chip |
Non-Patent Citations (1)
| Title |
|---|
| "On Improving the performance of Traff’s Comparator";Ranjana Sridhar et al.;《Power Electronics (IICPE), 2012 IEEE 5th India International Conference on》;20121208;第1页左栏第一段至第4页左栏第二段 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103618525A (en) | 2014-03-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103346773B (en) | Level shifting circuit | |
| CN105245220A (en) | Physical unclonable chip circuit | |
| CN104156025B (en) | A kind of high-order temperature compensated reference source | |
| CN103618525B (en) | A kind of current-mode comparator | |
| CN105867518B (en) | A kind of effective current mirror for suppressing supply voltage influence | |
| CN103092253A (en) | Reference voltage generation circuit | |
| CN105094207A (en) | Band gap reference source eliminating bulk effect | |
| CN102480276B (en) | Foldable cascade operational amplifier | |
| CN106774593A (en) | A kind of current source | |
| CN109947172A (en) | A kind of high output resistance image current source circuit of low pressure drop | |
| CN107317567A (en) | The RC oscillating circuits of low-temperature coefficient output frequency | |
| CN104300949A (en) | Low-voltage resetting circuit for radio frequency chip of internet of things | |
| CN104202022A (en) | Novel low-power-consumption comparator | |
| CN209297190U (en) | A kind of low pressure drop image current source circuit | |
| CN203950228U (en) | Current source circuit | |
| CN102981550A (en) | Low-voltage low-power consumption CMOS (Complementary Metal Oxide Semiconductor) voltage source | |
| CN105425008A (en) | Internet of things high sensitivity magnetic-sensor sampling circuit | |
| CN106681418B (en) | Input circuit with wide input voltage range and adjustable threshold voltage | |
| CN206741349U (en) | A kind of current source | |
| CN209572001U (en) | A kind of driving circuit and level shifting circuit of signal transfer tube | |
| CN103389768B (en) | Differential signal driver | |
| CN202331252U (en) | Threshold voltage generating circuit | |
| CN103023318B (en) | Low-voltage power supply generating circuit for inside of high-voltage chip | |
| CN102447845A (en) | Infrared focal plane array readout circuit and adaptive power consumption regulation method thereof | |
| CN108227814A (en) | One introduces a collection follows circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160817 Termination date: 20201206 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |