CN103607014B - Charge control system in charging chip - Google Patents

Charge control system in charging chip Download PDF

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CN103607014B
CN103607014B CN201310618043.1A CN201310618043A CN103607014B CN 103607014 B CN103607014 B CN 103607014B CN 201310618043 A CN201310618043 A CN 201310618043A CN 103607014 B CN103607014 B CN 103607014B
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voltage
pmos
nmos tube
current
control loop
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CN103607014A (en
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陈康
李俊杰
杨敏
余维学
郭辉
刘晓宇
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Shanghai Awinic Technology Co Ltd
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Shanghai Awinic Technology Co Ltd
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Abstract

A charge control system in charging chip, comprises Isobarically Control loop, current constant control loop, output circuit and biasing circuit.Described Isobarically Control loop is suitable for carrying out error to the first sampled voltage and the first reference voltage and amplifies process to produce the first pull-down current, and described first pull-down current is zero when described cell voltage is less than first threshold voltage; Described current constant control loop is suitable for carrying out error to the second sampled voltage and the second reference voltage and amplifies process to produce the second pull-down current, described second pull-down current is zero when described cell voltage is greater than Second Threshold voltage, and described Second Threshold voltage is greater than described first threshold voltage; Described output circuit is suitable for exporting control voltage according to described first pull-down current and the second pull-down current.The automatic smoothing that charge control system in charging chip provided by the invention achieves between constant current charging mode and constant voltage charge pattern switches, and improves the stability of charging current and cell voltage.

Description

Charge control system in charging chip
Technical field
The present invention relates to battery charging control technology field, the charge control system particularly in a kind of charging chip.
Background technology
Rechargeable battery is the limited chargeable battery of charging times, has the advantage such as economy and environmental protection.The principal element affecting rechargeable battery cycle life is charging modes and the charge efficiency of rechargeable battery.Therefore, while portable type electronic product develops to higher level integrated level, how for rechargeable battery provides the charging scheme of highly effective and safe more and more to receive the concern of designer.For the charge characteristic of rechargeable battery, usually adopt constant current-constant voltage mode charging.
Fig. 1 is the waveform schematic diagram of cell voltage and the charging current adopting constant current-constant voltage mode to charge to rechargeable battery.With reference to figure 1, horizontal axis representing time, the longitudinal axis represents voltage/current, and imaginary curve L11 represents cell voltage, and solid-line curve L12 represents charging current.During 0 ~ t1 moment, charging current remains unchanged, and cell voltage constantly raises, and adopts constant current mode to charge the battery; After the t1 moment, charging current reduces gradually, and cell voltage remains unchanged, and adopts constant voltage mode to charge the battery.
Fig. 2 is common a kind of part-structure schematic diagram realizing the charging chip of constant current-constant voltage mode charging.With reference to figure 2, described charging chip comprises charge control system 21 and control signal produces circuit 22, and described charge control system 21 comprises Isobarically Control loop 211 and current constant control loop 212.
Usually, described Isobarically Control loop 211 and current constant control loop 212 are error amplifier.Described Isobarically Control loop 211 is suitable for the first sampled voltage V fBwith the first reference voltage V rEF1carry out error and amplify process to produce the first control voltage EA1, described first sampled voltage V fBobtain for carrying out sampling to cell voltage.Described current constant control loop 212 is suitable for the second sampled voltage V cSwith the second reference voltage V rEF2carry out error and amplify process to produce the second control voltage EA2, described second sampled voltage V cSobtain for carrying out sampling to charging current.
Described control signal produces circuit 22 and is suitable for receiving described first control voltage EA1 or described second control voltage EA2, and produces the adjustable grid control signal Vg of duty ratio based on described first control voltage EA1 or described second control voltage EA2.Described grid control signal Vg is suitable for the grid inputting charge power pipe, controls conducting and the cut-off of charge power pipe.
When constant current charging mode, described Isobarically Control loop 211 exports high-impedance state, and described control signal produces circuit 23 and controlled by described second control signal EA2.Particularly, when charging current is greater than the constant current pre-set, described control signal produces circuit 22 under the control of described second control voltage EA2, and the duty ratio of the grid control signal Vg of generation reduces, the ON time of charge power pipe is shortened, reduces charging current; When charging current is less than the constant current pre-set, described control signal produces circuit 22 under the control of described second control voltage EA2, and the duty ratio of the grid control signal Vg of generation increases, and the ON time of charge power pipe is increased, increase charging current, to realize current constant control.
When constant voltage charge pattern, described current constant control loop 212 exports high-impedance state, and described control signal produces circuit 23 and controlled by described first control signal EA1.Particularly, when cell voltage is greater than the constant voltage pre-set, described control signal produces circuit 22 under the control of described first control voltage EA1, the duty ratio of the grid control signal Vg produced reduces, the ON time of charge power pipe is shortened, reduces the output voltage of described charging chip; When cell voltage is less than the constant voltage pre-set, described control signal produces circuit 22 under the control of described first control voltage EA1, the duty ratio of the grid control signal Vg produced increases, the ON time of charge power pipe is increased, increase the output voltage of described charging chip, to realize Isobarically Control.
But when being switched to constant voltage charge pattern by constant current charging mode, described current constant control loop 212 can not automatically switch to described Isobarically Control loop 211.When cell voltage is increased to the constant voltage preset, needs first to make described current constant control loop 212 quit work, then open described Isobarically Control loop 211.In switching overshoot, cause charging current and cell voltage instability.
Summary of the invention
What the present invention solved is that constant current charging mode and constant voltage charge pattern can not take over seamlessly and cause the problem of charging current and cell voltage instability.
For solving the problem, the invention provides the charge control system in a kind of charging chip, comprising Isobarically Control loop, current constant control loop, output circuit and biasing circuit;
Described Isobarically Control loop is suitable for carrying out error to the first sampled voltage and the first reference voltage and amplifies process to produce the first pull-down current, described first sampled voltage is relevant to cell voltage, and described first pull-down current is zero when described cell voltage is less than first threshold voltage;
Described current constant control loop is suitable for carrying out error to the second sampled voltage and the second reference voltage and amplifies process to produce the second pull-down current, described second sampled voltage is relevant to charging current, described second pull-down current is zero when described cell voltage is greater than Second Threshold voltage, and described Second Threshold voltage is greater than described first threshold voltage;
Described output circuit is suitable for exporting control voltage according to input current, and the magnitude of voltage of described control voltage reduces with the increase of described input current, and described input current comprises described first pull-down current and described second pull-down current;
Described biasing circuit is suitable for providing bias voltage to described Isobarically Control loop, described current constant control loop and described output circuit.
Optionally, the open-loop gain of described Isobarically Control loop is greater than the open-loop gain of described current constant control loop.
Optionally, described first sampled voltage is carry out to described cell voltage the voltage obtained of sampling, and described second sampled voltage is carry out to described charging current the voltage obtained of sampling.
Optionally, described current constant control loop comprises differential amplifier circuit, the first current mirror and the second current mirror;
Described differential amplifier circuit is suitable for carrying out error to described second sampled voltage and described second reference voltage and amplifies process to produce error amplification voltage;
It is error amplified current that described first current mirror is suitable for described error to amplify voltage transitions;
Described second current mirror is suitable for carrying out mirror image to export described second pull-down current to described error amplified current, and the image current output of described second current mirror is the output that described current constant control loop exports described second pull-down current.
Optionally, charge control system in described charging chip also comprises power management control loop, described power management control loop is suitable for carrying out error to the 3rd sampled voltage and the 3rd reference voltage and amplifies process to produce the 3rd pull-down current, described 3rd sampled voltage is relevant to the voltage that adapter inputs described charging chip, and described input current also comprises described 3rd pull-down current;
Described biasing circuit is also suitable for providing bias voltage to described power management control loop.
Optionally, described 3rd sampled voltage is that the voltage inputting described charging chip to adapter carries out the voltage obtained of sampling.
Optionally, charge control system in described charging chip also comprises input Current limited Control loop, described input Current limited Control loop is suitable for carrying out error to the 4th sampled voltage and the 4th reference voltage and amplifies process to produce the 4th pull-down current, described 4th sampled voltage is relevant to the electric current that adapter inputs described charging chip, and described input current also comprises described 4th pull-down current;
Described biasing circuit is also suitable for providing bias voltage to described input Current limited Control loop.
Optionally, described 4th sampled voltage is that the electric current inputting described charging chip to adapter carries out the voltage obtained of sampling.
Compared with prior art, technical scheme of the present invention has the following advantages:
Isobarically Control loop in charge control system in charging chip provided by the invention and current constant control loop share same output circuit, and the first pull-down current that described output circuit produces according to described Isobarically Control loop and the second pull-down current that described current constant control loop produces export control voltage.
When cell voltage is less than first threshold voltage, described Isobarically Control loop exports high-impedance state, and namely described first pull-down current is zero, and described control voltage is determined according to described second pull-down current, adopts constant current mode charging; When cell voltage is more than or equal to described first threshold voltage and is less than or equal to Second Threshold voltage, described Isobarically Control loop is started working, namely described first pull-down current is non-vanishing, described control voltage is determined jointly according to described first pull-down current and described second pull-down current, and constant current charging mode is from trend constant voltage charge mode transition; When cell voltage is greater than Second Threshold voltage, described current constant control loop exports high-impedance state, and namely described second pull-down current is zero, and described control voltage is determined according to described first pull-down current, adopts constant voltage mode charging.Therefore, the automatic smoothing that the charge control system in charging chip provided by the invention achieves between constant current charging mode and constant voltage charge pattern switches, and improves the stability of charging current and cell voltage.
In possibility of the present invention, the open-loop gain of described Isobarically Control loop is greater than the open-loop gain of described current constant control loop, when cell voltage is increased to equal with described Second Threshold voltage, described current constant control loop can quit work rapidly, ensure that the constant voltage precision that cell voltage charges, prevent cell voltage from exceeding the deboost of charging, improve the reliability of charging system.
In possibility of the present invention, described Isobarically Control loop comprises the first resistance, the second resistance, the 3rd resistance and the 3rd NMOS tube, and described first resistance, the second resistance, the 3rd resistance and the 3rd NMOS tube form the inside negative feedback of described Isobarically Control loop.Described inner negative feedback can reduce the impedance of the grid of described 3rd NMOS tube, limit corresponding for the grid of described 3rd NMOS tube is pushed away far, makes zero compensation more easy, namely can be integrated in sheet by zero compensation, improve the integrated level of circuit.
In possibility of the present invention, the charge control system in described charging chip also comprises power management control loop.When the driving force of adapter is not enough, described power management control loop substitutes described current constant control loop work, the 3rd pull-down current that described control voltage produces according to described power management control loop is determined, thus self adaptation can reduce charging current to mate the adapter of driving force deficiency.
In possibility of the present invention, the charge control system in described charging chip also comprises input Current limited Control loop.To be applied in the charging chip of switched charge mode when the charge control system in described charging chip and the electric current inputted by USB interface is excessive time, the 4th pull-down current that described control voltage produces according to described input Current limited Control loop is determined, charging current is regulated to obtain stable input current by described control voltage, thus compatible different USB interface agreements.
Accompanying drawing explanation
Fig. 1 is the waveform schematic diagram of cell voltage and the charging current adopting constant current-constant voltage mode to charge to rechargeable battery;
Fig. 2 is the existing part-structure schematic diagram realizing the charging chip of constant current-constant voltage mode charging;
Fig. 3 is the structural representation of the charge control system in the charging chip of embodiment of the present invention;
Fig. 4 is the circuit diagram of the charge control system in the charging chip of the embodiment of the present invention;
Fig. 5 is the circuit diagram of the power management control loop of the embodiment of the present invention;
Fig. 6 is the circuit diagram of the input Current limited Control loop of the embodiment of the present invention.
Embodiment
Technical solution of the present invention provides the charge control system in a kind of charging chip, and Fig. 3 is the structural representation of the charge control system in the charging chip of embodiment of the present invention.With reference to figure 3, described charge control system comprises Isobarically Control loop 31, current constant control loop 32, output circuit 33 and biasing circuit 34.
Described Isobarically Control loop 31 is suitable for the first sampled voltage V fBwith the first reference voltage V rEF1carry out error and amplify process to produce the first pull-down current, described first sampled voltage V fBrelevant to cell voltage, described first pull-down current is zero when described cell voltage is less than first threshold voltage.
Particularly, described first sampled voltage V fBthat the voltage obtained of sampling is carried out, i.e. described first sampled voltage V to described cell voltage fBfollow the change of described cell voltage.Described first reference voltage V rEF1the reference voltage arranged according to constant voltage, voltage when described constant voltage refers to constant voltage charge, battery kept.Described constant voltage can be arranged according to the battery capacity of rechargeable battery, and such as, the constant voltage of rechargeable cellphone battery is set to 4.2V usually.
As described first sampled voltage V fBbe less than described first reference voltage V rEF1time, represent that cell voltage is less than described constant voltage; As described first sampled voltage V fBequal described first reference voltage V rEF1time, represent that cell voltage is equal with described constant voltage; As described first sampled voltage V fBbe greater than described first reference voltage V rEF1time, represent that cell voltage is greater than described constant voltage.
Described first threshold voltage is less than described constant voltage.Described in when cell voltage is less than described first threshold voltage, the first pull-down current is zero, described in when cell voltage is more than or equal to described first threshold voltage, the first pull-down current is non-vanishing, namely, before entering constant voltage charge pattern, described Isobarically Control loop 31 just participates in charging and controls.Described first threshold voltage can be arranged according to the actual requirements, and such as, when described constant voltage is 4.2V, described first threshold voltage can be set to 4.15V, can change described first threshold voltage by the gain adjusting described Isobarically Control loop.
Described current constant control loop 32 is suitable for the second sampled voltage V cSwith the second reference voltage V rEF2carry out error and amplify process to produce the second pull-down current, described second sampled voltage V cSrelevant to charging current, described second pull-down current is zero when described cell voltage is greater than Second Threshold voltage, and described Second Threshold voltage is greater than described first threshold voltage.
Particularly, described second sampled voltage V cSthat the voltage obtained of sampling is carried out, i.e. described second sampled voltage V to described charging current cSfollow the change of described charging current.Described second reference voltage V rEF2the reference voltage arranged according to constant current, the charging current kept when described constant current refers to constant current charge.
As described second sampled voltage V cSbe less than described second reference voltage V rEF2time, represent that charging current is less than described constant current; As described second sampled voltage V cSequal described second reference voltage V rEF2time, represent that charging current is equal with described constant current; As described second sampled voltage V cSbe greater than described second reference voltage V rEF2time, represent that charging current is greater than described constant current.
Described Second Threshold voltage is described constant voltage, voltage when namely described Second Threshold voltage refers to constant voltage charge, battery kept.Described in when cell voltage is greater than described Second Threshold voltage, the second pull-down current is zero, described in when cell voltage is less than or equal to described Second Threshold voltage, the second pull-down current is non-vanishing, namely, after entering constant voltage charge pattern, described current constant control loop 32 does not participate in charging and controls.
Described output circuit 33 is suitable for exporting control voltage according to input current, and the magnitude of voltage of described control voltage reduces with the increase of described input current, and described input current comprises described first pull-down current and described second pull-down current.
Particularly, when cell voltage is less than described first threshold voltage, described first pull-down current is zero, described second pull-down current is non-vanishing, described Isobarically Control loop 31 does not participate in charging and controls, employing constant current charging mode charges, and described control voltage reduces with the increase of described second pull-down current;
When cell voltage is more than or equal to described first threshold voltage and is less than or equal to described Second Threshold voltage, described first pull-down current and described second pull-down current all non-vanishing, described Isobarically Control loop 31 and described current constant control loop 32 all participate in charging and control, constant current charging mode to constant voltage charge mode transition, described control voltage with described first pull-down current and described second pull-down current sum increase and reduce;
When cell voltage is greater than described Second Threshold voltage, non-vanishing, described second pull-down current of described first pull-down current is zero, described current constant control loop 32 does not participate in charging and controls, and adopt the charging of constant voltage charge pattern, described control voltage reduces with the increase of described first pull-down current.
Described control voltage produces the input of circuit as the control signal in charging chip, controls described control signal and produces the adjustable grid control signal of circuit generation duty ratio.Described grid control signal is suitable for the grid inputting charge power pipe, controls conducting and the cut-off of charge power pipe.Those skilled in the art know function and the structure that described control signal produces circuit, do not repeat them here.
Described biasing circuit 34 is suitable for providing bias voltage to described Isobarically Control loop 31, described current constant control loop 32 and described output circuit 33.Described bias voltage is the voltage that normally can work in order to ensure described Isobarically Control loop 31, current constant control loop 32 and output circuit 33 and provide, and described bias voltage can be preset according to conditions such as actual circuit structure.
Charge control system in charging chip provided by the invention, described Isobarically Control loop 31 and described current constant control loop 32 share described output circuit 33, and the first pull-down current that described output circuit 33 produces according to described Isobarically Control loop 31 and the second pull-down current that described current constant control loop 32 produces export control voltage.
When constant current charging mode, only participate in charging by described current constant control loop 32 and control; When constant voltage charge pattern, only participate in charging by described Isobarically Control loop 31 and control.In the process switched to constant voltage charge pattern by constant current charging mode, when cell voltage boosts to equal with described first threshold voltage, described Isobarically Control loop 31 automatically participates in charging and controls, by constant current charging mode to constant voltage charge mode transition; When cell voltage is increased to equal with described Second Threshold voltage (i.e. described constant voltage), described current constant control loop 32 automatically exits charging and controls.Therefore, the automatic smoothing that the charge control system in charging chip provided by the invention achieves between constant current charging mode and constant voltage charge pattern switches, and improves the stability of charging current and cell voltage.
Usually, reduce battery life to prevent from not being full of completely by battery during charging or affect battery performance, very high to the required precision of described constant voltage, the precision controlling of constant voltage described in General Requirements is within ± 1%.That is, when adopting constant voltage mode charging, the absolute value of the ratio that the voltage that charging chip exports obtains than upper described constant voltage with the difference of described constant voltage is less than 1%.
In embodiments of the present invention, the open-loop gain of described Isobarically Control loop 31 is greater than the open-loop gain of described current constant control loop 32.Therefore, in the charging process of constant current charging mode to constant voltage charge mode transition, once cell voltage is increased to equal with described Second Threshold voltage (i.e. described constant voltage), described Isobarically Control loop 31 can take over the control action of described current constant control loop 32 completely, described current constant control loop 32 is quit work rapidly, ensure that the constant voltage precision that cell voltage charges.Further, can prevent cell voltage from exceeding the deboost of charging, improve the reliability of charging system.
It should be noted that, the open-loop gain of described Isobarically Control loop 31 and described current constant control loop 32 can be arranged according to the actual requirements, such as, the open-loop gain that can arrange described Isobarically Control loop 31 is 70dB, and the open-loop gain arranging described current constant control loop 32 is 30dB.Particularly, those skilled in the art know, by the open-loop gain regulating the component parameter forming described Isobarically Control loop 31 and form described current constant control loop 32 can change described Isobarically Control loop 31 and described current constant control loop 32, do not repeat them here.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 4 is the circuit diagram of the charge control system in the charging chip of the embodiment of the present invention.With reference to figure 4, described charge control system comprises Isobarically Control loop 41, current constant control loop 42, output circuit 43 and biasing circuit 44.
Described Isobarically Control loop 41 comprises the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the first resistance R1, the second resistance R2 and the 3rd resistance R3.
The grid of described first PMOS MP1 connects the grid of described second PMOS MP2 and is suitable for input offset voltage Vb, the source electrode of described first PMOS MP1 is suitable for input supply voltage Vdd, the drain electrode of described first PMOS MP1 connects the source electrode of described second PMOS MP2, and the substrate of described first PMOS MP1 connects the substrate of described second PMOS MP2 and is suitable for inputting described supply voltage Vdd.
Described bias voltage Vb is the bias voltage applied at the grid of PMOS in order to ensure described Isobarically Control loop 41 can normally work, and concrete magnitude of voltage can be preset according to conditions such as the manufacturing process of PMOS.Described supply voltage Vdd is the voltage of powering to described charge control system.
The drain electrode of described second PMOS MP2 connects the substrate of the source electrode of described 3rd PMOS MP3, the substrate of described 3rd PMOS MP3, the source electrode of the 4th PMOS MP4 and described 4th PMOS MP4.
The grid of described 3rd PMOS MP3 is suitable for inputting described first sampled voltage V fB, the drain electrode of described 3rd PMOS MP3 connects the grid of the drain electrode of described first NMOS tube MN1, the grid of described first NMOS tube MN1 and described second NMOS tube MN2.
The grid of described 4th PMOS MP4 is suitable for inputting described first reference voltage V rEF1, the drain electrode of described 4th PMOS MP4 connects the drain electrode of described second NMOS tube MN2 and the grid of described 3rd NMOS tube MN3.
The source electrode of described first NMOS tube MN1 connects one end of one end of described first resistance R1, the source electrode of described 3rd NMOS tube MN3 and described 3rd resistance R3, and the substrate of described first NMOS tube MN1 connects the other end of described first resistance R1 and ground connection.
The source electrode of described second NMOS tube MN2 connects one end of described second resistance R2, and the substrate of described second NMOS tube MN2 connects the other end of described second resistance R2 and ground connection.
Described 3rd NMOS tube MN3 drain electrode exports the output of described first pull-down current Id1 for described Isobarically Control loop 41, and the substrate of described 3rd NMOS tube MN3 connects the other end of described 3rd resistance R3 and ground connection.
In the described Isobarically Control loop 41 of the embodiment of the present invention, described first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the first NMOS tube MN1 and the second NMOS tube MN2 form differential amplifier circuit, to described first sampled voltage V fBwith described first reference voltage V rEF1carry out error and amplify process, and node A described in node A(be the drain electrode of described 4th PMOS MP4, the interconnective link of grid of the drain electrode of described second NMOS tube MN2 and described 3rd NMOS tube MN3) produce error amplify after voltage.
Described 3rd NMOS tube MN3 has the effect that source electrode is followed, and be described first pull-down current Id1 by the voltage transitions of described node A, described first pull-down current Id1 flows to the source electrode of described 3rd NMOS tube MN3 by the drain electrode of described 3rd NMOS tube MN3.Because described first pull-down current Id1 is exported by described Isobarically Control loop 41, therefore, what can think that described Isobarically Control loop 41 exports is negative current.
Described Isobarically Control loop 41 introduces the inside negative feedback be made up of described first resistance R1, the second resistance R2, the 3rd resistance R3 and the 3rd NMOS tube MN3, in embodiments of the present invention, the resistance value of described first resistance R1, the second resistance R2 and the 3rd resistance R3 is equal.
Described first pull-down current Id1 is fed back to differential amplifier circuit by described inner negative feedback, makes voltage amplifier become trsanscondutance amplifier, and the mutual conductance of described trsanscondutance amplifier can be done less.When cell voltage is less than described constant voltage, described first pull-down current Id1 is just non-vanishing, namely realizes when cell voltage is more than or equal to described first threshold voltage, and described Isobarically Control loop 41 is got involved charging and controlled; When cell voltage equals described constant voltage (i.e. described Second Threshold voltage), described in the DC operation promise of described trsanscondutance amplifier, the first pull-down current Id1 equals the bias voltage that described output circuit 43 provides, and described Isobarically Control loop 41 is taken over charging completely and controlled.
Further, the inside negative feedback be made up of described first resistance R1, the second resistance R2, the 3rd resistance R3 and the 3rd NMOS tube MN3 can reduce the impedance of described node A, reaches and limit corresponding for node A is pushed away object far away.Because the limit that described node A is corresponding is pushed away far, when the voltage of described node A has Δ V to change, through the transmission of the diode connected mode of described 3rd NMOS tube MN3 and described first NMOS tube MN1, the voltage of Node B also has the change of approximate Δ V, and described Node B is the tie point that the drain electrode of described 3rd PMOS MP3 is connected with the drain electrode of described first NMOS tube MN1.
Common source again through described second NMOS tube MN2 amplifies, and feeding back a size to described node A is g 2× Δ V/(1+g 2× R) small-signal current, thus the small signal impedance of described node A is (1/g 2+ R), much smaller than adding the impedance before feedback, wherein, g 2for the transconductance value of described second NMOS tube MN2, R is the resistance value of described first resistance R1.
In charge control system, in order to prevent loop oscillation, usually all need to carry out resistance-capacitance zero compensation.In prior art, because the value being used as resistance and the electric capacity compensated is comparatively large, need to compensate in chip exterior.And the described Isobarically Control loop 41 that the embodiment of the present invention provides introduces inner negative feedback, limit corresponding for described node A is pushed away far, reduce the small signal impedance of described node A, the value being used as resistance and the electric capacity compensated can obtain less, therefore, can compensate at chip internal, improve circuit level.
Described current constant control loop 42 comprises differential amplifier circuit, the first current mirror and the second current mirror, and wherein, described differential amplifier circuit is suitable for described second sampled voltage V cSwith described second reference voltage V rEF2carry out error and amplify process to produce error amplification voltage; It is error amplified current that described first current mirror is suitable for described error to amplify voltage transitions; Described second current mirror is suitable for carrying out mirror image to export described second pull-down current Id2 to described error amplified current, and the image current output of described second current mirror is the output that described current constant control loop exports described second pull-down current Id2.
In the present embodiment, described differential amplifier circuit is the differential amplifier circuit of folded common source and common grid, comprises the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the tenth PMOS MP10, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6 and the 7th NMOS tube MN7; Described first current mirror comprises the 11 PMOS MP11 and described tenth PMOS MP10; Described second current mirror comprises the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10 and the 11 NMOS tube MN11.
Particularly, the grid of described 5th PMOS MP5 connects the grid of described 6th PMOS MP6 and is suitable for inputting described bias voltage Vb, the source electrode of described 5th PMOS MP5 is suitable for inputting described supply voltage Vdd, the drain electrode of described 5th PMOS MP5 connects the source electrode of described 6th PMOS MP6, and the substrate of described 5th PMOS MP5 connects the substrate of described 6th PMOS MP6 and is suitable for inputting described supply voltage Vdd.
The drain electrode of described 6th PMOS MP6 connects the substrate of the source electrode of described 7th PMOS MP7, the substrate of described 7th PMOS MP7, the source electrode of the 8th PMOS MP8 and described 8th PMOS MP8.
The grid of described 7th PMOS MP7 is suitable for inputting described second reference voltage V rEF2, the drain electrode of described 7th PMOS MP7 connects the source electrode of described 4th NMOS tube MN4 and the drain electrode of described 5th NMOS tube MN5.
The grid of described 8th PMOS MP8 is suitable for inputting described second sampled voltage V cS, the drain electrode of described 8th PMOS MP8 connects the source electrode of described 6th NMOS tube MN6 and the drain electrode of described 7th NMOS tube MN7.
The grid of described 9th PMOS MP9 connects the drain electrode of described 9th PMOS MP9 and the drain electrode of described 4th NMOS tube MN4, and the source electrode of described 9th PMOS MP9 connects the substrate of described 9th PMOS MP9 and is suitable for inputting described supply voltage Vdd.
The grid of described 4th NMOS tube MN4 connects the grid of the grid of described 5th NMOS tube MN5, the grid of the 6th NMOS tube MN6 and described 7th NMOS tube MN7 and is suitable for inputting primary grid voltage, and the substrate of described 4th NMOS tube MN4 connects the substrate of described 5th NMOS tube MN5 and the source electrode of described 5th NMOS tube MN5 and ground connection.
Described primary grid voltage is the bias voltage applied at the grid of NMOS tube in order to ensure described current constant control loop 42 can normally work, and concrete magnitude of voltage can be preset according to conditions such as the manufacturing process of NMOS tube.In the present embodiment, described primary grid voltage is also provided by described biasing circuit 44.
The grid of described tenth PMOS MP10 connects the drain electrode of the drain electrode of described tenth PMOS MP10, the grid of described 11 PMOS MP11 and described 6th NMOS tube MN6, and the source electrode of described tenth PMOS MP10 connects the substrate of described tenth PMOS MP10 and is suitable for inputting described supply voltage Vdd.
The substrate of described 6th NMOS tube MN6 connects the substrate of described 7th NMOS tube MN7 and the source electrode of described 7th NMOS tube MN7 and ground connection.
The source electrode of described 11 PMOS MP11 connects the substrate of described 11 PMOS MP11 and is suitable for inputting described supply voltage Vdd, and the drain electrode of described 11 PMOS MP11 connects the drain electrode of described 8th NMOS tube MN8, the grid of described 8th NMOS tube MN8, the grid of described 9th NMOS tube MN9, the grid of described tenth NMOS tube MN10 and the grid of described 11 NMOS tube MN11.
The source electrode of described 8th NMOS tube MN8 connects the drain electrode of described 9th NMOS tube MN9, and the substrate of described 8th NMOS tube MN8 connects the substrate of described 9th NMOS tube MN9 and the source electrode of described 9th NMOS tube MN9 and ground connection.
The drain electrode of described tenth NMOS tube MN10 is the output that described current constant control loop 42 exports described second pull-down current Id2, the source electrode of described tenth NMOS tube MN10 connects the drain electrode of described 11 NMOS tube MN11, and the substrate of described tenth NMOS tube MN10 connects the substrate of described 11 NMOS tube MN11 and the source electrode of described 11 NMOS tube MN11 and ground connection.
In the described current constant control loop 42 that the embodiment of the present invention provides, the differential amplifier circuit that described 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the tenth PMOS MP10, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6 and the 7th NMOS tube MN7 are formed, to described second sampled voltage V cSwith described second reference voltage V rEF2carry out error and amplify process, produce error in the drain electrode of described 6th NMOS tube MN6 and amplify voltage;
It is error amplified current that described error is amplified voltage transitions by the first current mirror that described tenth PMOS MP10 and described 11 PMOS MP11 is formed, the electric current that the image current output (i.e. the drain electrode of described 11 PMOS MP11) that described error amplified current is described first current mirror exports;
The second current mirror be made up of described 8th NMOS tube MN8, the 9th NMOS tube MN9, the 9th NMOS tube MN9 and the tenth NMOS tube MN10 carries out mirror image to described error amplified current, the image current that described second current mirror exports is described second pull-down current Id2, and namely the image current output (i.e. the drain electrode of described tenth NMOS tube MN10) of described second current mirror exports the output of described second pull-down current Id2 for described current constant control loop 42.
Described second pull-down current Id2 flows to the source electrode of described tenth NMOS tube MN10 by the drain electrode of described tenth NMOS tube MN10.Because described second pull-down current Id2 is exported by described current constant control loop 42, therefore, what can think that described current constant control loop 42 exports is negative current.
It should be noted that, described differential amplifier circuit, the first current mirror and the second current mirror are not limited to the circuit provided of the present embodiment, in other embodiments, also can adopt differential amplifier circuit and the current mirror of other circuit forms, the present invention is not construed as limiting this.
Described output circuit 43 comprises the 12 PMOS MP12 and the 13 PMOS MP13.
The grid of described 12 PMOS MP12 connects the grid of described 13 PMOS MP13 and is suitable for inputting described bias voltage Vb, the source electrode of described 12 PMOS MP12 is suitable for inputting described supply voltage Vdd, the drain electrode of described 12 PMOS MP12 connects the source electrode of described 13 PMOS MP13, and the substrate of described 12 PMOS MP12 connects the substrate of described 13 PMOS MP13 and is suitable for inputting described supply voltage Vdd.
The drain electrode of described 13 PMOS MP13 is the output out that described output circuit 43 exports described control voltage, the output being suitable for exporting with described Isobarically Control loop 41 described first pull-down current Id1 is connected with the output that described current constant control loop 42 exports described second pull-down current Id2, namely in the present embodiment, the drain electrode of described 13 PMOS MP13 connects the drain electrode of described 3rd NMOS tube MN3 and the drain electrode of described tenth NMOS tube MN10.
Described output circuit 43 produces bias current by described 12 PMOS MP12 and described 13 PMOS MP13.According to Kirchhoff's current law (KCL), the electric current that described output out exports equals described bias current and adds the input current inputting described output circuit 43, in embodiments of the present invention, described input current comprises described first pull-down current Id1 and described second pull-down current Id2.Because described first pull-down current Id1 and described second pull-down current Id2 is the electric current flowing out described output circuit 43, therefore, the electric current that described output out exports equals described bias current and deducts described first pull-down current Id1 and described second pull-down current Id2, and the magnitude of voltage of described control voltage reduces with the increase of described first pull-down current Id1 and described second pull-down current Id2 sum.
Described biasing circuit 44 comprises the 12 NMOS tube MN12, the 13 NMOS tube MN13, the 14 NMOS tube MN14, the 15 NMOS tube MN15, the 14 PMOS MP14 and the 15 PMOS MP15.
The grid of the described 12 NMOS tube MN12 of drain electrode connection of described 12 NMOS tube MN12, the grid of described 13 NMOS tube MN13, the grid of described 14 NMOS tube MN14 and the grid of described 15 NMOS tube MN15 are also suitable for input reference current Ir, the source electrode of described 12 NMOS tube MN12 connects the drain electrode of described 13 NMOS tube MN13, and the substrate of described 12 NMOS tube MN12 connects the substrate of described 13 NMOS tube MN13 and the source electrode of described 13 NMOS tube MN13 and ground connection.
Described reference current Ir is the electric current inputted in order to described biasing circuit 44 can normally work, and concrete current value can be arranged according to actual circuit structure and device parameters etc.
The drain electrode of described 14 NMOS tube MN14 connects the drain electrode of described 15 PMOS MP15, the grid of described 15 PMOS MP15 and the grid of described 14 PMOS MP14 and is suitable for exporting described bias voltage Vb, the source electrode of described 14 NMOS tube MN14 connects the drain electrode of described 15 NMOS tube MN15, and the substrate of described 14 NMOS tube MN14 connects the substrate of described 15 NMOS tube MN15 and the source electrode of described 15 NMOS tube MN15 and ground connection.
The source electrode of described 14 PMOS MP14 is suitable for inputting described supply voltage Vdd, the drain electrode of described 14 PMOS MP14 connects the source electrode of described 15 PMOS MP15, and the substrate of described 14 PMOS MP14 connects the substrate of described 15 PMOS MP15 and is suitable for inputting described supply voltage Vdd.
As previously mentioned, the primary grid voltage inputting described 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6 and the 7th NMOS tube MN7 is also provided by described biasing circuit 44, therefore, the grid of described 15 NMOS tube MN15 also connects the grid of the grid of described 4th NMOS tube MN4, the grid of the 5th NMOS tube MN5, the grid of the 6th NMOS tube MN6 and the 7th NMOS tube MN7.
Below the operation principle of the charge control system of the embodiment of the present invention is described.
When constant current charging mode, namely when cell voltage is less than described first threshold voltage, described Isobarically Control loop 41 exports high-impedance state, described first pull-down current Id1 is zero, and the second pull-down current Id2 that the control voltage that described output circuit 43 exports is exported by described current constant control loop 42 controls;
When being switched to constant voltage charge pattern by constant current charging mode, namely when cell voltage is more than or equal to described first threshold voltage and is less than or equal to described Second Threshold voltage (i.e. described constant voltage), described first pull-down current Id1 and described second pull-down current Id2 is all non-vanishing, and the control voltage that described output circuit 43 exports is controlled by described first pull-down current Id1 and described second pull-down current Id2;
When constant voltage charge pattern, namely when cell voltage is greater than described Second Threshold voltage (i.e. described constant voltage), described current constant control loop 42 exports high-impedance state, described second pull-down current Id2 is zero, and the first pull-down current Id1 that the control voltage that described output circuit 43 exports is exported by described Isobarically Control loop 41 controls.
In charging chip, some functional circuit only works when constant voltage charge pattern, needs to provide constant voltage signal to these functional circuits when entering constant voltage charge pattern.Therefore, the charge control system of the embodiment of the present invention can also comprise the constant voltage signal generation circuit 45 producing described constant voltage signal.
Continue with reference to figure 4, described constant voltage signal produces circuit 45 and comprises the 16 PMOS MP16, the 17 PMOS MP17, the 16 NMOS tube MN16 and the 4th resistance R4.
The grid of described 16 PMOS MP16 connects the grid of described 17 PMOS MP17 and is suitable for inputting described bias voltage Vb, the source electrode of described 16 PMOS MP16 is suitable for inputting described supply voltage Vdd, the drain electrode of described 16 PMOS MP16 connects the source electrode of described 17 PMOS MP17, and the substrate of described 16 PMOS MP16 connects the substrate of described 17 PMOS MP17 and is suitable for inputting described supply voltage Vdd.
The drain electrode of described 17 PMOS MP17 connects the drain electrode of described 16 NMOS tube MN16 and is suitable for exporting constant voltage signal CV.
The grid of described 16 NMOS tube MN16 connects the grid of described 3rd NMOS tube MN3, the source electrode of described 16 NMOS tube MN16 connects one end of described 4th resistance R4, and the substrate of described 16 NMOS tube MN16 connects the other end of described 4th resistance R4 and ground connection.
When constant current charging mode, described 16 NMOS tube MN16 cut-off, described constant voltage signal produces circuit 45 and exports high-impedance state; When constant voltage charge pattern, described 16 NMOS tube MN16 conducting, the constant voltage signal CV that described constant voltage signal produces circuit 45 output is low level signal.
Usually, operationally, the driving force of charging current and adapter matches charging chip, and the input current that namely adapter provides needs to be more than or equal to charging current.But the adapter used due to user has plurality of specifications, and the driving force of adapter may not meet the requirement of charging chip.For this reason, the charge control system of the embodiment of the present invention can also comprise power management control loop, and described power management control loop self adaptation can reduce charging current to mate the adapter of driving force deficiency.
Described power management control loop is suitable for carrying out error to the 3rd sampled voltage and the 3rd reference voltage and amplifies process to produce the 3rd pull-down current, described 3rd sampled voltage is relevant to the voltage that adapter inputs described charging chip, and described input current also comprises described 3rd pull-down current.
Particularly, described 3rd sampled voltage for the voltage that adapter is provided carry out sample obtain voltage, when the driving force of adapter is enough, described 3rd sampled voltage is greater than described 3rd reference voltage, described 3rd pull-down current is zero, described power management control loop exports high-impedance state, thus does not participate in charging control; When the driving force of adapter is not enough, the voltage drop that adapter provides, described 3rd sampled voltage is less than described 3rd reference voltage, described 3rd pull-down current is non-vanishing, and, because charging current does not also reach set constant current, described current constant control loop is inoperative, therefore, described power management control loop replaces described current constant control loop 42 to control charging current, to match with the driving force of adapter.
Fig. 5 is the circuit diagram of the power management control loop of the embodiment of the present invention, with reference to figure 5, described power management control loop comprises the 5th resistance R5, 6th resistance R6, first electric capacity C1, 18 PMOS MP18, 19 PMOS MP19, 20 metal-oxide-semiconductor MP20, 21 PMOS MP21, 22 PMOS MP22, 23 PMOS MP23, 24 metal-oxide-semiconductor MP24, 25 PMOS MP25, 17 NMOS tube MN17, 18 NMOS tube MN18, 19 NMOS tube MN19, 20 NMOS tube MN20, 21 NMOS tube MN21, 22 NMOS tube MN22, 23 NMOS tube MN23, 24 NMOS tube MN24.
One end of described 5th resistance R5 is suitable for the voltage Vbus that input adapter provides, and the other end of described 5th resistance R5 connects one end of described 6th resistance R6, one end of described first electric capacity C1 and the grid of described 20 PMOS MP20.
The other end of described 6th resistance R6 connects the other end of described first electric capacity C1 and ground connection.
The grid of described 18 PMOS MP18 connects the grid of described 19 PMOS MP19 and is suitable for inputting described bias voltage Vb, the source electrode of described 18 PMOS MP18 is suitable for inputting described supply voltage Vdd, the drain electrode of described 18 PMOS MP18 connects the source electrode of described 19 PMOS MP19, and the substrate of described 18 PMOS MP18 connects the substrate of described 19 PMOS MP19 and is suitable for inputting described supply voltage Vdd.
The drain electrode of described 19 PMOS MP19 connects the substrate of the source electrode of described 20 PMOS MP20, the described substrate of the 20 PMOS MP20, the source electrode of the 21 PMOS MP21 and described 21 PMOS MP21.
The drain electrode of described 20 PMOS MP20 connects the source electrode of described 17 NMOS tube MN17 and the drain electrode of described 18 NMOS tube MN18.
The grid of described 21 PMOS MP21 is suitable for inputting described 3rd reference voltage V rEF3, the drain electrode of described 21 PMOS MP21 connects the source electrode of described 19 NMOS tube MN19 and the drain electrode of described 20 NMOS tube MN20.
The grid of described 17 NMOS tube MN17 connects the grid of described 18 NMOS tube MN18, the grid of the 19 NMOS tube MN19 and the grid of described 20 NMOS tube MN20 are also suitable for inputting second grid voltage, the drain electrode of described 17 NMOS tube MN17 connects the drain electrode of described 22 PMOS MP22, the grid of described 22 PMOS MP22 and the grid of described 23 PMOS MP23, the substrate of described 17 NMOS tube MN17 connects the substrate of described 18 NMOS tube MN18 and the source electrode of described 18 NMOS tube MN18 and ground connection.
In embodiments of the present invention, described second grid voltage can be identical with described primary grid voltage, and namely the grid of the grid of described 17 NMOS tube MN17, the described grid of the 18 NMOS tube MN18, the grid of the 19 NMOS tube MN19 and described 20 NMOS tube MN20 is all connected to the grid of described 15 NMOS tube MN15.
The drain electrode of described 19 NMOS tube MN19 connects the drain electrode of described 23 PMOS MP23, the drain electrode of described 24 PMOS MP24, the grid of described 24 PMOS MP24 and the grid of described 25 PMOS MP25, and the substrate of described 19 NMOS tube MN19 connects the substrate of described 20 NMOS tube MN20 and the source electrode of described 20 NMOS tube MN20 and ground connection.
The source electrode of described 22 PMOS MP22 connects the substrate of described 22 PMOS MP22 and is suitable for inputting described supply voltage Vdd.
The source electrode of described 23 PMOS MP23 connects the substrate of described 23 PMOS MP23 and is suitable for inputting described supply voltage Vdd.
The source electrode of described 24 PMOS MP24 connects the substrate of described 24 PMOS MP24 and is suitable for inputting described supply voltage Vdd.
The source electrode of described 25 PMOS MP25 connects the substrate of described 25 PMOS MP25 and is suitable for inputting described supply voltage Vdd, and the drain electrode of described 25 PMOS MP25 connects the drain electrode of described 21 NMOS tube MN21, the grid of described 21 NMOS tube MN21, the grid of described 22 NMOS tube MN22, the grid of described 23 NMOS tube MN23 and the grid of described 24 NMOS tube MN24.
The source electrode of described 21 NMOS tube MN21 connects the drain electrode of described 22 NMOS tube MN22, and the substrate of described 21 NMOS tube MN21 connects the substrate of described 22 NMOS tube MN22 and the source electrode of described 22 NMOS tube MN22 and ground connection.
The drain electrode of described 23 NMOS tube MN23 is the output that described power management control loop exports described 3rd pull-down current Id3, the output out being suitable for exporting with described output circuit 43 described control voltage is connected, namely the drain electrode of described 23 NMOS tube MN23 connects the drain electrode of described 13 PMOS MP13, the source electrode of described 23 NMOS tube MN23 connects the drain electrode of described 24 NMOS tube MN24, the substrate of described 23 NMOS tube MN23 connects the substrate of described 24 NMOS tube MN24 and the source electrode of described 24 NMOS tube MN24 and ground connection.
In the power management control loop that the embodiment of the present invention provides, described 5th resistance R5, the 6th resistance R6 and the first electric capacity C1 form sample circuit, and the voltage of the link that described 5th resistance R5 is connected with described 6th resistance R6 is described 3rd sampled voltage.
Described 18 PMOS MP18, the 19 PMOS MP19, the 20 PMOS MP20, the 21 PMOS MP21, the 22 PMOS MP22, the 23 PMOS MP23, the 17 NMOS tube MN17, the 18 NMOS tube MN18, the 19 NMOS tube MN19 and the 20 NMOS tube MN20 form the differential amplifier circuit of folded cascode configuration, to described 3rd sampled voltage and described 3rd reference voltage V rEF3carry out error and amplify process.
Through described 24 PMOS MP24 and described 25 PMOS MP25 form current mirror by error amplify after voltage transitions be current source, described current source is converted to electric current and sinks by the current mirror be made up of described 21 NMOS tube MN21, the 22 NMOS tube MN22, the 23 NMOS tube MN23 and the 24 NMOS tube MN24 again, exports described 3rd pull-down current Id3 by the drain electrode of described 23 NMOS tube MN23.Described 3rd pull-down current Id3 is flowed to the source electrode of described 23 NMOS tube MN23 by the drain electrode of described 23 NMOS tube MN23.Because described 3rd pull-down current Id3 is exported by described power management control loop, therefore, what can think that described power management control loop exports is negative current.
For the charging chip using switched charge mode, when using USB interface to charge to rechargeable battery as adapter, strictly standard usb interface must be met.And for USB1.0 interface protocol, the current limit that USB interface exports is at 100mA; For USB2.0 interface protocol, the current limit that USB interface exports is at 500mA; For USB3.0 interface protocol, the current limit of USB interface is at 900mA.In order to the USB interface agreement that compatibility is different, the charge control system of the embodiment of the present invention can also comprise input Current limited Control loop, and described input Current limited Control loop can by regulating charging current to obtain stable input current.
Described input Current limited Control loop is suitable for carrying out error to the 4th sampled voltage and the 4th reference voltage and amplifies process to produce the 4th pull-down current, described 4th sampled voltage is relevant to the electric current that adapter inputs described charging chip, and described input current also comprises described 4th pull-down current.
Particularly, described 4th sampled voltage is carry out to the electric current of adapter input charging chip the voltage obtained of sampling, in the present embodiment, charged to rechargeable battery by USB interface, the electric current that described 4th sampled voltage is USB interface input charging chip carries out the voltage obtained of sampling.When the electric current of USB interface input charging chip does not exceed the Limited Current of charging chip setting, described 4th sampled voltage is greater than described 4th reference voltage, described 4th pull-down current is zero, and described input Current limited Control loop exports high-impedance state, thus does not participate in charging control; When the electric current of USB interface input charging chip exceedes the Limited Current of charging chip setting, described 4th sampled voltage is greater than described 4th reference voltage, described 4th pull-down current is non-vanishing, the control voltage that described charge control system exports is determined according to described 4th pull-down current, charging current is controlled by described input Current limited Control loop, described charging current is reduced, thus obtains stable input current, compatible different USB interface agreements.
Fig. 6 is the circuit diagram of the input Current limited Control loop of the embodiment of the present invention, with reference to figure 6, described input Current limited Control loop comprises the 26 PMOS MP26, the 27 PMOS MP27, the 28 PMOS MP28, the 29 PMOS MP29 pipe, the 30 PMOS MP30, the 31 PMOS MP31, the 25 NMOS tube MN25, the 26 NMOS tube MN26, the 27 NMOS tube MN27, the 28 NMOS tube MN28 and the 29 NMOS tube MN29.
The grid of described 26 PMOS MP26 connects the grid of described 27 PMOS MP27 and is suitable for inputting described bias voltage Vb, the source electrode of described 26 PMOS MP26 is suitable for inputting described supply voltage Vdd, the drain electrode of described 26 PMOS MP26 connects the source electrode of described 27 PMOS MP27, and the substrate of described 26 PMOS MP26 connects the substrate of described 27 PMOS MP27 and is suitable for inputting described supply voltage Vdd.
The source electrode of the described 28 PMOS MP28 of drain electrode connection of described 27 PMOS MP27, the substrate of described 28 PMOS MP28, the source electrode of described 29 PMOS MP29 and the substrate of described 29 PMOS MP29.
The grid of described 28 PMOS MP28 is suitable for inputting described 4th reference voltage V rEF4, the drain electrode of described 28 PMOS MP28 connects the drain electrode of described 25 NMOS tube MN25, the grid of described 25 NMOS tube MN25 and the grid of described 26 NMOS tube MN26.
The drain electrode that the grid of described 29 PMOS MP29 is suitable for inputting described 4th sampled voltage Vci, described 29 PMOS MP29 connects the drain electrode of described 27 NMOS tube MN27, the grid of described 27 NMOS tube MN27 and the grid of described 28 NMOS tube MN28.
The source electrode of described 25 NMOS tube MN25 connects the substrate of described 25 NMOS tube MN25 and ground connection.
The drain electrode of described 26 NMOS tube MN26 connects the drain electrode of described 30 PMOS MP30, the grid of described 30 PMOS MP30 and the grid of described 31 PMOS MP31, and the source electrode of described 26 NMOS tube MN26 connects the substrate of described 26 NMOS tube MN26 and ground connection.
The source electrode of described 30 PMOS MP30 connects the substrate of described 30 PMOS MP30 and is suitable for inputting described supply voltage Vdd.
The source electrode of described 27 NMOS tube MN27 connects the substrate of described 27 NMOS tube MN27 and ground connection.
The drain electrode of described 28 NMOS tube MN28 connects the drain electrode of described 31 PMOS MP31 and the grid of described 29 NMOS tube MN29, and the source electrode of described 28 NMOS tube MN28 connects the substrate of described 28 NMOS tube MN28 and ground connection.
The source electrode of described 31 PMOS MP31 connects the substrate of described 31 PMOS MP31 and is suitable for inputting described supply voltage Vdd.
The drain electrode of described 29 NMOS tube MN29 is the output that described input Current limited Control loop exports described 4th pull-down current Id4, the output out being suitable for exporting with described output circuit 43 described control voltage is connected, namely the drain electrode of described 29 NMOS tube MN29 connects the drain electrode of described 13 PMOS MP13, and the source electrode of described 29 NMOS tube MN29 connects the substrate of described 29 NMOS tube MN29 and ground connection.
In the input Current limited Control loop that the embodiment of the present invention provides, described 26 PMOS MP26, the 27 PMOS MP27, the 28 PMOS MP28, the 29 PMOS MP29, the 30 PMOS MP30, the 31 PMOS MP31, the 25 NMOS tube MN25, the 26 NMOS tube MN26, the 27 NMOS tube MN27 and the 28 NMOS tube MN28 form differential amplifier circuit, to described 4th sampled voltage Vci and described 4th reference voltage V rEF4carry out error and amplify process.
Described 29 NMOS tube MN29 has the effect that source electrode is followed, be described 4th pull-down current Id4 by the gate voltage switches of described 29 NMOS tube MN29, described 4th pull-down current Id4 is flowed to the source electrode of described 29 NMOS tube MN29 by the drain electrode of described 29 NMOS tube MN29.Because described 4th pull-down current Id4 is exported by described input Current limited Control loop, therefore, what can think described output input Current limited Control loop is negative current.
It should be noted that the charge control system in the charging chip that the embodiment of the present invention provides can be applied in the charging chip of linear-charging mode, also can be applied in the charging chip of switched charge mode.When in the charging chip being applied to linear-charging mode, described charge control system does not comprise described input Current limited Control loop; When in the charging chip being applied to switched charge mode, described charge control system can comprise described input Current limited Control loop.
In sum, the charge control system in the charging chip that technical solution of the present invention provides, can make constant current charging mode automatic smoothing switch to constant voltage charge pattern, improve the stability of charging current and cell voltage.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (12)

1. the charge control system in charging chip, described charging chip is suitable for, to rechargeable battery charging, it is characterized in that, comprising Isobarically Control loop, current constant control loop, output circuit and biasing circuit and power management control loop;
Described Isobarically Control loop is suitable for carrying out error to the first sampled voltage and the first reference voltage and amplifies process to produce the first pull-down current, described first sampled voltage is relevant to cell voltage, and described first pull-down current is zero when described cell voltage is less than first threshold voltage;
Described current constant control loop is suitable for carrying out error to the second sampled voltage and the second reference voltage and amplifies process to produce the second pull-down current, described second sampled voltage is relevant to charging current, described second pull-down current is zero when described cell voltage is greater than Second Threshold voltage, and described Second Threshold voltage is greater than described first threshold voltage;
Described output circuit is suitable for exporting control voltage according to input current, and the magnitude of voltage of described control voltage reduces with the increase of described input current, and described input current comprises described first pull-down current and described second pull-down current;
Described biasing circuit is suitable for providing bias voltage to described Isobarically Control loop, described current constant control loop and described output circuit;
Described power management control loop is suitable for carrying out error to the 3rd sampled voltage and the 3rd reference voltage and amplifies process to produce the 3rd pull-down current, described 3rd sampled voltage is relevant to the voltage that adapter inputs described charging chip, and described input current also comprises described 3rd pull-down current;
Described biasing circuit is also suitable for providing bias voltage to described power management control loop.
2. the charge control system in charging chip as claimed in claim 1, it is characterized in that, the open-loop gain of described Isobarically Control loop is greater than the open-loop gain of described current constant control loop.
3. the charge control system in charging chip as claimed in claim 1, is characterized in that, described first sampled voltage is carry out to described cell voltage the voltage obtained of sampling, and described second sampled voltage is carry out to described charging current the voltage obtained of sampling.
4. the charge control system in charging chip as claimed in claim 1, it is characterized in that, described Isobarically Control loop comprises the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the first resistance, the second resistance and the 3rd resistance;
The grid of described first PMOS connects the grid of described second PMOS and is suitable for inputting described bias voltage, the source electrode of described first PMOS is suitable for input supply voltage, the drain electrode of described first PMOS connects the source electrode of described second PMOS, and the substrate of described first PMOS connects the substrate of described second PMOS and is suitable for inputting described supply voltage;
The drain electrode of described second PMOS connects the substrate of the source electrode of described 3rd PMOS, the substrate of described 3rd PMOS, the source electrode of the 4th PMOS and described 4th PMOS;
The grid of described 3rd PMOS is suitable for inputting described first sampled voltage, and the drain electrode of described 3rd PMOS connects the grid of the drain electrode of described first NMOS tube, the grid of described first NMOS tube and described second NMOS tube;
The grid of described 4th PMOS is suitable for inputting described first reference voltage, and the drain electrode of described 4th PMOS connects the drain electrode of described second NMOS tube and the grid of described 3rd NMOS tube;
The source electrode of described first NMOS tube connects one end of one end of described first resistance, the source electrode of described 3rd NMOS tube and described 3rd resistance, and the substrate of described first NMOS tube connects the other end of described first resistance and ground connection;
The source electrode of described second NMOS tube connects one end of described second resistance, and the substrate of described second NMOS tube connects the other end of described second resistance and ground connection;
The drain electrode of described 3rd NMOS tube is the output that described Isobarically Control loop exports described first pull-down current, and the substrate of described 3rd NMOS tube connects the other end of described 3rd resistance and ground connection.
5. the charge control system in charging chip as claimed in claim 4, it is characterized in that, the resistance value of described first resistance, described second resistance and described 3rd resistance is equal.
6. the charge control system in charging chip as claimed in claim 4, is characterized in that, also comprises constant voltage signal and produces circuit, and described constant voltage signal produces circuit and comprises the 16 PMOS, the 17 PMOS, the 16 NMOS tube and the 4th resistance;
The grid of described 16 PMOS connects the grid of described 17 PMOS and is suitable for inputting described bias voltage, the source electrode of described 16 PMOS is suitable for inputting described supply voltage, the drain electrode of described 16 PMOS connects the source electrode of described 17 PMOS, and the substrate of described 16 PMOS connects the substrate of described 17 PMOS and is suitable for inputting described supply voltage;
The drain electrode of described 17 PMOS connects the drain electrode of described 16 NMOS tube and is suitable for exporting constant voltage signal;
The grid of described 16 NMOS tube connects the grid of described 3rd NMOS tube, and the source electrode of described 16 NMOS tube connects one end of described 4th resistance, and the substrate of described 16 NMOS tube connects the other end of described 4th resistance and ground connection.
7. the charge control system in charging chip as claimed in claim 1, it is characterized in that, described current constant control loop comprises differential amplifier circuit, the first current mirror and the second current mirror;
Described differential amplifier circuit is suitable for carrying out error to described second sampled voltage and described second reference voltage and amplifies process to produce error amplification voltage;
It is error amplified current that described first current mirror is suitable for described error to amplify voltage transitions;
Described second current mirror is suitable for carrying out mirror image to export described second pull-down current to described error amplified current, and the image current output of described second current mirror is the output that described current constant control loop exports described second pull-down current.
8. the charge control system in charging chip as claimed in claim 1, it is characterized in that, described output circuit comprises the 12 PMOS and the 13 PMOS;
The grid of described 12 PMOS connects the grid of described 13 PMOS and is suitable for inputting described bias voltage, the source electrode of described 12 PMOS is suitable for input supply voltage, the drain electrode of described 12 PMOS connects the source electrode of described 13 PMOS, and the substrate of described 12 PMOS connects the substrate of described 13 PMOS and is suitable for inputting described supply voltage;
The drain electrode of described 13 PMOS is the output that described output circuit exports described control voltage, and the output being suitable for exporting with described Isobarically Control loop described first pull-down current is connected with the output that described current constant control loop exports described second pull-down current.
9. the charge control system in charging chip as claimed in claim 1, it is characterized in that, described biasing circuit comprises the 12 NMOS tube, the 13 NMOS tube, the 14 NMOS tube, the 15 NMOS tube, the 14 PMOS and the 15 PMOS;
The grid of described 12 NMOS tube of drain electrode connection of described 12 NMOS tube, the grid of described 13 NMOS tube, the grid of described 14 NMOS tube and the grid of described 15 NMOS tube are also suitable for inputting reference current, the source electrode of described 12 NMOS tube connects the drain electrode of described 13 NMOS tube, and the substrate of described 12 NMOS tube connects the substrate of described 13 NMOS tube and the source electrode of described 13 NMOS tube and ground connection;
The drain electrode of described 14 NMOS tube connects the drain electrode of described 15 PMOS, the grid of described 15 PMOS and the grid of described 14 PMOS and is suitable for exporting described bias voltage, the source electrode of described 14 NMOS tube connects the drain electrode of described 15 NMOS tube, and the substrate of described 14 NMOS tube connects the substrate of described 15 NMOS tube and the source electrode of described 15 NMOS tube and ground connection;
The source electrode of described 14 PMOS is suitable for input supply voltage, the drain electrode of described 14 PMOS connects the source electrode of described 15 PMOS, and the substrate of described 14 PMOS connects the substrate of described 15 PMOS and is suitable for inputting described supply voltage.
10. the charge control system in charging chip as claimed in claim 1, is characterized in that, described 3rd sampled voltage is carry out to the voltage that adapter inputs described charging chip the voltage obtained of sampling.
Charge control system in 11. charging chips as claimed in claim 1, it is characterized in that, also comprise input Current limited Control loop, described input Current limited Control loop is suitable for carrying out error to the 4th sampled voltage and the 4th reference voltage and amplifies process to produce the 4th pull-down current, described 4th sampled voltage is relevant to the electric current that adapter inputs described charging chip, and described input current also comprises described 4th pull-down current;
Described biasing circuit is also suitable for providing bias voltage to described input Current limited Control loop.
Charge control system in 12. charging chips as claimed in claim 11, is characterized in that, described 4th sampled voltage is that the electric current inputting described charging chip to adapter carries out the voltage obtained of sampling.
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CN105305563B (en) * 2015-11-25 2018-07-24 天津航空机电有限公司 A kind of nickel-cadmium storage battery charging control circuit and charger
CN108879881B (en) * 2018-08-14 2023-12-05 上海艾为电子技术股份有限公司 Bidirectional linear charging circuit and quick charging chip
CN109450045B (en) * 2018-12-21 2024-05-17 厦门奇力微电子有限公司 Multi-battery management protection chip and multi-battery management protection system
CN109861329B (en) * 2019-02-18 2024-06-25 上海南麟电子股份有限公司 Linear charging system, constant-current constant-voltage control circuit and voltage following control method thereof

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