CN103399607B - The high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit - Google Patents

Abstract

The present invention relates to power management techniques.The invention solves existing low pressure difference linear voltage regulator mostly to increase circuit complexity, lower the problem that load capacity and increase output voltage noise etc. are cost solution output voltage generation due to voltage spikes, provide a kind of high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit, its technical scheme can be summarized as: compared with existing LDO, add slew rate enhancing circuit and building-out capacitor, and the normal phase input end of error amplifier is connected with reference voltage source, inverting input is connected with resistive feedback circuit, output terminal is connected with the input end of slew rate enhancing circuit, the output terminal of slew rate enhancing circuit is connected with the grid of Correctional tube, one end of building-out capacitor is connected with the inverting input of error amplifier, the other end of building-out capacitor is connected with output terminal.The invention has the beneficial effects as follows, improve transient response, be applicable to low pressure difference linear voltage regulator.

Description

The high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit

Technical field

The present invention relates to power management techniques, particularly the technology of low pressure difference linear voltage regulator.

Background technology

Low pressure difference linear voltage regulator (LDO) is the class Important Circuit in field of power management, has the advantages such as output noise is little, cost is low, structure is simple, low-power consumption.Along with electronic system improving constantly power requirement, traditional LDO can not meet the requirement of people to indexs such as chip noise, power supply suppression, mappings.Thus, the research of high-performance LDO has become the study hotspot of field of power management.

As shown in Figure 1, typical LDO circuit is generally by reference voltage source Vref, error amplifier, power voltage input terminal VDD, Correctional tube Mp and resistive feedback circuit are formed, the normal phase input end of error amplifier is connected with resistive feedback circuit, inverting input is connected with reference voltage source Vref, output terminal is connected with the grid of Correctional tube Mp, the drain electrode of Correctional tube Mp is output terminal, and be connected with resistive feedback circuit, the source electrode of Correctional tube Mp is connected with power voltage input terminal VDD, concrete, resistive feedback circuit comprises the first resistance R1 and the second resistance R2, one end of first resistance R1 is connected with one end of the second resistance R2, and be connected with the normal phase input end of error amplifier, the other end of the first resistance R1 is connected with output terminal, the other end of the second resistance is connected with ground wire, Correctional tube Mp generally adopts metal-oxide-semiconductor, as PMOS, during use, load RL is generally connected across between output terminal and ground wire, outer electric capacity CL is in parallel with load for sheet, its principle is that the burning voltage that produced by band gap reference and negative feedback control loop are obtained substantially not with the output voltage of environmental change.In order to improve carrying load ability, the area of general Correctional tube Mp is very large, thus the stray capacitance of tens of pF is formed at Correctional tube Mp grid, simultaneously for improving the power consumption of LDO, static working current is very little, thus will be relatively slower to the discharge and recharge of Correctional tube Mp grid, when output current saltus step, output voltage will produce large upper punch, undershoot due to voltage spikes, and voltage resume stabilization time is also by long simultaneously.Some documents propose corresponding solution to this problem, such as at document " Mohammad Al-Shyoukh, Hoi Leeand and Raul Perez.A Transient-EnhancedLow-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation.IEEEJOURNAL OF SOLID-STATE CIRCUITS, VOL.42, NO.8, AUGUST2007 " middle proposition, transient state intensifier circuit is added between error amplifier and Correctional tube, but add the complexity of system balance, and the Slew Rate of LDO can only be improved to a certain extent, power supply rejection ability simultaneously under high frequency does not have greatly improved.

In recent years, a lot of high PSRR LDO solution is there is in paper, but mostly increasing circuit complexity, lower load capacity and increase output voltage noise etc. for cost, and a lot of solution high band particularly more than 1MHz do not obtain large improvement.

Summary of the invention

The object of the invention is will overcome current low pressure difference linear voltage regulator mostly to increase circuit complexity, to lower the shortcoming that load capacity and increase output voltage noise etc. are cost solution output voltage generation due to voltage spikes, a kind of high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit is provided.

The present invention solves its technical matters, the technical scheme adopted is, the high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit, comprise reference voltage source, error amplifier, power voltage input terminal, Correctional tube and resistive feedback circuit, it is characterized in that, also comprise slew rate enhancing circuit and building-out capacitor, the normal phase input end of described error amplifier is connected with reference voltage source, inverting input is connected with resistive feedback circuit, output terminal is connected with the input end of slew rate enhancing circuit, the output terminal of slew rate enhancing circuit is connected with the grid of Correctional tube, the drain electrode of Correctional tube is output terminal, and be connected with resistive feedback circuit, the source electrode of Correctional tube is connected with power voltage input terminal, one end of building-out capacitor is connected with the inverting input of error amplifier, the other end of building-out capacitor is connected with output terminal.

Concrete, described error amplifier is-three dB bandwidth is greater than the amplifier of 2MHz.

Further, described error amplifier comprises bias voltage input, first PMOS, second PMOS, 3rd PMOS, 4th PMOS, first NMOS tube, second NMOS tube, 3rd NMOS tube, 4th NMOS tube and the 5th NMOS tube, the grid of described first PMOS is connected with the grid of the second PMOS, the grid of the second PMOS is connected with the drain electrode of himself, the drain electrode of the first PMOS is connected with the grid of the 4th NMOS tube, the grid of the 4th NMOS tube is connected with the drain electrode of himself, the grid of the second PMOS is connected with the drain electrode of the first NMOS tube, the grid of the 3rd PMOS is connected with the drain electrode of himself, and be connected with the drain electrode of the second NMOS tube, the grid of the 4th PMOS is connected with the grid of the 3rd PMOS, drain electrode is connected with the grid of the 5th NMOS tube, the grid of the 5th NMOS tube is connected with the drain electrode of himself, the grid of the first NMOS tube is error amplifier inverting input, source class is connected with the drain electrode of the 3rd NMOS tube, the grid of the second NMOS tube is error amplifier normal phase input end, source class is connected with the drain electrode of the 3rd NMOS tube, first PMOS, second PMOS, the source class of the 3rd PMOS and the 4th PMOS is all connected with power voltage input terminal, 3rd NMOS tube, the source class of the 4th NMOS tube and the 5th NMOS tube is all connected to ground, the grid of the 3rd NMOS tube is connected with bias voltage input, to produce tail current.

Concrete, described slew rate enhancing circuit comprises the 5th PMOS, 6th PMOS, 7th PMOS, 8th PMOS, 6th NMOS tube, 7th NMOS tube, 8th NMOS tube and the 9th NMOS tube, described 5th PMOS and the 6th NMOS tube form the first phase inverter, 7th PMOS and the 7th NMOS tube form the second phase inverter, the input end of the first phase inverter is connected with the output terminal of error amplifier, first inverter output is connected with the 6th PMOS drain electrode and the second inverter input, 6th PMOS grid is connected with its drain electrode, and be connected with the second inverter input, second inverter output is with the 8th NMOS tube grid, drain electrode and the 9th NMOS tube grid are connected, 8th NMOS tube grid is connected with the 9th NMOS tube grid, 8th POMS tube grid is connected with its drain electrode, and be connected with Correctional tube grid.

Concrete, described resistive feedback circuit comprises the first resistance and the second resistance, and one end of the first resistance is connected with one end of the second resistance, and is connected with the inverting input of error amplifier, the other end of the first resistance is connected with output terminal, and the other end of the second resistance is connected with ground wire.

Further, described Correctional tube is PMOS.

Concrete, also comprise the outer electric capacity of sheet, one end of described outer electric capacity is connected with output terminal, and the other end is connected with ground wire, and the dead resistance of the outer electric capacity of this sheet is less than 10m Ω, and the capacitance of the outer electric capacity of sheet is greater than 2.2uF.

The invention has the beneficial effects as follows, the high PSR low pressure difference linear voltage regulator of the integrated slew rate enhancing circuit in the present invention program, makes Slew Rate strengthen by integrated slew rate enhancing circuit, improves transient response, also enhance the ability suppressed power supply, particularly power supply in high frequency to suppress simultaneously.

Accompanying drawing explanation

Fig. 1 is the system chart of existing LDO.

Fig. 2 is the system chart of the high PSR low pressure difference linear voltage regulator of the integrated slew rate enhancing circuit of the present invention.

Fig. 3 is the circuit diagram of the high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit in the embodiment of the present invention.

Fig. 4 is the gain-phase curve map of supply voltage 2V output load 200mA in the embodiment of the present invention.

Fig. 5 is the gain-phase curve map of supply voltage 2V output load 0A in the embodiment of the present invention.

Fig. 6 is that in the embodiment of the present invention, supply voltage 2V output load 1us jumps to 200mA by 0A, then jumps to the transient response figure of 0A by 200mA.

Fig. 7 is that in the embodiment of the present invention, under output load 200mA, supply voltage 1us is jumped to the transient response figure of 3.3V by 2V.

Fig. 8 is the power supply rejection ratio characteristics figure in the embodiment of the present invention under different output load.

Wherein, Vref is reference voltage source, and VDD is supply voltage, and Mp is Correctional tube, and Cm is building-out capacitor, and Va is bias voltage, MA ₁be the first PMOS, MA ₂be the second PMOS, MA ₃be the 3rd PMOS, MA ₄be the 4th PMOS, MA ₅be the first NMOS tube, MA ₆be the second NMOS tube, MA ₇be the 3rd NMOS tube, MA ₈be the 4th NMOS tube, MA ₉be the 5th NMOS tube, MB ₁be the 5th PMOS, MB ₂be the 6th PMOS, MB ₃be the 7th PMOS, MB ₄be the 8th PMOS, MB ₅be the 6th NMOS tube, MB ₆be the 7th NMOS tube, MB ₇be the 8th NMOS tube, MB ₈be the 9th NMOS tube, R1 is the first resistance, and R2 is the second resistance, and CL is the outer electric capacity of sheet, and RL is load.

Embodiment

Below in conjunction with embodiment and accompanying drawing, describe technical scheme of the present invention in detail.

The system chart of the high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit of the present invention is as Fig. 2.The high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit of the present invention, comprise reference voltage source Vref, error amplifier, power voltage input terminal, Correctional tube Mp, resistive feedback circuit, slew rate enhancing circuit and building-out capacitor Cm, the normal phase input end of described error amplifier is connected with reference voltage source Vref, inverting input is connected with resistive feedback circuit, output terminal is connected with the input end of slew rate enhancing circuit, the output terminal of slew rate enhancing circuit is connected with the grid of Correctional tube Mp, the drain electrode of Correctional tube Mp is output terminal, and be connected with resistive feedback circuit, the source electrode of Correctional tube Mp is connected with power voltage input terminal, one end of building-out capacitor Cm is connected with the inverting input of error amplifier, the other end of building-out capacitor Cm is connected with output terminal.

Embodiment

As shown in Figure 2, circuit diagram as shown in Figure 3 for the system chart of the high PSR low pressure difference linear voltage regulator of the integrated slew rate enhancing circuit of the embodiment of the present invention.The high PSR low pressure difference linear voltage regulator of the integrated slew rate enhancing circuit of this example, comprise reference voltage source Vref, error amplifier, power voltage input terminal, Correctional tube Mp, resistive feedback circuit, slew rate enhancing circuit and building-out capacitor Cm, the normal phase input end of described error amplifier is connected with reference voltage source Vref, inverting input is connected with resistive feedback circuit, output terminal is connected with the input end of slew rate enhancing circuit, the output terminal of slew rate enhancing circuit is connected with the grid of Correctional tube Mp, the drain electrode of Correctional tube Mp is output terminal, and be connected with resistive feedback circuit, the source electrode of Correctional tube Mp is connected with power voltage input terminal, one end of building-out capacitor Cm is connected with the inverting input of error amplifier, the other end of building-out capacitor Cm is connected with output terminal, in this example, Correctional tube Mp is PMOS, power voltage input terminal input supply voltage VDD.

This routine medial error amplifier is-and three dB bandwidth is greater than the amplifier of 2MHz, and it comprises bias voltage input, the first PMOS MA ₁, the second PMOS MA ₂, the 3rd PMOS MA ₃, the 4th PMOS MA ₄, the first NMOS tube MA ₅, the second NMOS tube MA ₆, the 3rd NMOS tube MA ₇, the 4th NMOS tube MA ₈and the 5th NMOS tube MA ₉, wherein, the first PMOS MA ₁grid and the second PMOS MA ₂grid connect, the second PMOS MA ₂grid be connected with the drain electrode of himself, the first PMOS MA ₁drain electrode and the 4th NMOS tube MA ₈grid connect, the 4th NMOS tube MA ₈grid be connected with the drain electrode of himself, the second PMOS MA ₂grid and the first NMOS tube MA ₅drain electrode connect, the 3rd PMOS MA ₃grid be connected with the drain electrode of himself, and with the second NMOS tube MA ₆drain electrode connect, the 4th PMOS MA ₄grid and the 3rd PMOS MA ₃grid connect, drain electrode with the 5th NMOS tube MA ₉grid connect, the 5th NMOS tube MA ₉grid be connected with the drain electrode of himself, the first NMOS tube MA ₅grid be error amplifier inverting input, source class and the 3rd NMOS tube MA ₇drain electrode connect, the second NMOS tube MA ₆grid be error amplifier normal phase input end, source class and the 3rd NMOS tube MA ₇drain electrode connect, the first PMOS MA ₁, the second PMOS MA ₂, the 3rd PMOS MA ₃and the 4th PMOS MA ₄source class be all connected with power voltage input terminal, the 3rd NMOS tube MA ₇, the 4th NMOS tube MA ₈and the 5th NMOS tube MA ₉source class be all connected to ground, the 3rd NMOS tube MA ₇grid be connected with bias voltage input, to produce tail current, bias voltage input is in order to input offset voltage Va.In order to make error amplifier not introduce low-frequency pole, its output resistance Ro can not be too large, and consider simultaneously and reduce quiescent dissipation and increase Slew Rate, its tail current should get the value of a rather moderate, its low-frequency gain A _eAfor 50dB, exporting limit is 3M Hz.

Slew rate enhancing circuit in this example comprises the 5th PMOS MB ₁, the 6th PMOS MB ₂, the 7th PMOS MB ₃, the 8th PMOS MB ₄, the 6th NMOS tube MB ₅, the 7th NMOS tube MB ₆, the 8th NMOS tube MB ₇and the 9th NMOS tube MB ₈, wherein, the 5th PMOS MB ₁with the 6th NMOS tube MB ₅form the first phase inverter, the 7th PMOS MB ₃with the 7th NMOS tube MB ₆form the second phase inverter, the input end of the first phase inverter is connected with the output terminal of error amplifier, and the first inverter output is with the 6th PMOS MB ₂drain electrode and the second inverter input are connected, the 6th PMOS MB ₂grid is connected with its drain electrode, and is connected with the second inverter input, and the second inverter output is with the 8th NMOS tube MB ₇grid, drain electrode and the 9th NMOS tube MB ₈grid is connected, the 8th NMOS tube MB ₇grid and the 9th NMOS tube MB ₈grid connects, the 8th POMS pipe MB ₄grid is connected with its drain electrode, and is connected with Correctional tube Mp grid.

Resistive feedback circuit in this example comprises the first resistance R1 and the second resistance R2, one end of first resistance R1 is connected with one end of the second resistance R2, and be connected with the inverting input of error amplifier, the other end of the first resistance R1 is connected with output terminal, and the other end of the second resistance R2 is connected with ground wire.

During use, load RL is connected across between output terminal and ground wire, and outer electric capacity CL is in parallel with load RL for sheet, namely one end of the outer electric capacity CL of sheet is connected with output terminal, the other end is connected with ground wire, and the dead resistance of the outer electric capacity CL of this sheet is less than 10m Ω, and the capacitance of the outer electric capacity CL of sheet is greater than 2.2uF.

Slew rate enhancing circuit is emphasis of the present invention, and the effect that Slew Rate strengthens is the grid input that can change Correctional tube Mp when load changes fast, thus adjusts output voltage stabilization within the extremely short time.

Under stable condition, the 8th PMOS MB ₄image load RL electric current, simultaneously biased 9th NMOS tube MB ₈, the 8th NMOS tube MB ₇mirror image the 9th NMOS tube MB ₈electric current, ratio is 1:k, the 8th NMOS tube MB ₇grid voltage is fixed; Due to the 8th NMOS tube MB ₇grid voltage is fixed, so the input voltage of the second phase inverter is also fixed; 6th PMOS MB ₂mirror image the 7th PMOS MB ₃electric current, and the 6th PMOS MB ₂for diode connects, thus the output terminal limit of the first phase inverter is operated in high frequency place; The output terminal of the first phase inverter is connected with the second inverter input, and the input terminal voltage of the second phase inverter is fixed, and namely the output end voltage of the first phase inverter is fixed, thus the input terminal voltage of the first phase inverter is fixed.

When load jumps to heavy duty by underloading, output voltage will have undershoot voltage, be amplified by error amplifier, first inverter input will be rapidly charged, first inverter input voltage increases, thus the first phase inverter is output capacitor rapid discharge, flows through the 6th PMOS MB ₂electric current will increase, the second inverter input voltage will reduce fast, and the second phase inverter is output capacitor rapid charge, thus the 9th NMOS tube MB ₈grid voltage increases, the 9th NMOS tube MB ₈to flow through more big current is Correctional tube gate discharge, and final system is stablized.When load jumps to underloading by heavy duty, output voltage will have upper punch voltage, be amplified by error amplifier, first inverter input will be discharged rapidly, first inverter input voltage reduces, thus the first phase inverter is output capacitor rapid charge, flows through the 6th PMOS MB ₂electric current will reduce, the second inverter input voltage will increase fast, and the second phase inverter is output capacitor rapid discharge, thus the 9th NMOS tube MB ₈grid voltage reduces, the 8th PMOS MB ₄to flow through more big current is Correctional tube gate charges, and final system is stablized.

Slew rate enhancing circuit in the present invention greatly improves transient response speed, and effectively reduces the spike of output voltage.

For slew rate enhancing circuit: the first inverter output meets the 6th PMOS MB of diode type of attachment ₂, thus under the first inverter output zero pole point will be operated in high frequency; Second inverter output meets the 8th NMOS tube MB of diode type of attachment ₇, thus under the second inverter output zero pole point will be operated in high frequency; 8th PMOS MB ₄for diode type of attachment, Correctional tube Mp grid will introduce high frequency poles.So slew rate enhancing circuit does not introduce unnecessary low-frequency pole, in 10MHz, whole system has three limits and one to compensate zero point.

Three limits are as follows respectively:

$P1=\frac{1}{\mathrm{CL}*\mathrm{Rout}}$

$P2=\frac{1}{R_P*C_P}$

$P3=\frac{1}{C_O*R_O}$

Wherein, P1 is the output limit that output terminal is corresponding, P2 is corresponding Rp and Cp of Correctional tube Mp grid limit, P3 is that error amplifier exports corresponding Ro and Co of limit, Resr is the dead resistance of the outer electric capacity of sheet, Rp is the dead resistance of Correctional tube grid, Cp is the stray capacitance of Correctional tube grid, Co is the load capacitance of error amplifier, Ro is the output resistance of error amplifier, and Rout is the output equivalent resistance of LDO, Rout=1/ (gdsp+GL), wherein gdsp is the output equivalent conductance of Correctional tube Mp, and GL is the inverse of pull-up resistor RL.

In building-out capacitor Cm and resistive feedback circuit, the first resistance R1, the second resistance R2 produce a pair zero pole point, and zero point is:

$\mathrm{Zm}=\frac{1}{\mathrm{Cm}*R_1}$

Limit is:

$\mathrm{Pm}=\frac{1}{\mathrm{Cm}*R_1//R_2}$

Stability analysis:

The output limit P1 of output terminal is as being more than 2.2uF for dominant pole load capacitance, and for not introducing low frequency zero point, influential system stability, the series parasitic resistance Resr of the outer electric capacity CL of sheet is less than 10m Ω.

The grid of Correctional tube Mp introduces time limit P ₂, due to the 8th PMOS MB ₄for diode type of attachment, then:

$\mathrm{Rp}\≈\frac{1}{\mathrm{gmb}4}$

$P_2\≈\frac{\mathrm{gmb}4}{\mathrm{Cp}}$

Wherein, gmb4 is the 8th PMOS MB ₄mutual conductance.Design the 8th PMOS MB ₄breadth length ratio makes gmb4 enough large, thus secondary limit P2 is shifted onto more than 100 times of dominant pole P1, ensures system stability.

Because the output resistance Ro of error amplifier is less, and its bringing onto load electric capacity Co is also very little, its limit P produced ₃high frequency treatment will be operated in.

The first resistance R in building-out capacitor Cm and resistive feedback circuit ₁, the second resistance R ₂produce a pair zero pole point, Zm and Pm, design the first resistance R ₁with the second resistance R ₂ratio, make zero point Zm compensating error amplifier export limit P ₃, make the limit Pm produced work in very high-frequency simultaneously.The introducing of building-out capacitor Cm well improves the stability of system.

The high PSR low pressure difference linear voltage regulator of the integrated slew rate enhancing circuit that the present invention proposes also has high power supply rejection ability, slew rate enhancing circuit will improve whole loop gain, under low frequency, low pressure difference linear voltage regulator is directly proportional to power supply rejection ability and open-loop gain, thus the Power Supply Rejection Ratio under improve low frequency.

Low frequency open-loop gain Aol is as follows:

$\mathrm{Aol}=\frac{\mathrm{\β}*A_{\mathrm{EA}}*\mathrm{Gm}*\mathrm{gmp}}{\mathrm{gmb}4*(\mathrm{gdsp}+\mathrm{GL})}=\frac{\mathrm{\β}*A_{\mathrm{EA}}*\mathrm{Gm}*\mathrm{gmp}*\mathrm{Rout}}{\mathrm{gmb}4}$

Wherein, for feedback factor, gmp is the mutual conductance of Correctional tube Mp, and gmb4 is the 8th PMOS MB ₄mutual conductance, Gm is the equivalent transconductance of slew rate enhancing circuit, A _eAfor error amplifier gain, Rout is output equivalent resistance, and gdsp is the output admittance of power tube Mp, and GL is the inverse of pull-up resistor.。

Fallen by the zero compensation that building-out capacitor Cm produces because error amplifier exports limit P1, can not have an impact to PSR so error amplifier exports limit P1 and building-out capacitor Cm.By calculating, high frequency small-signal output voltage v _outwith high frequency small-signal input supply voltage v _inratio as shown in the formula:

$\frac{v_{\mathrm{out}}}{v_{\mathrm{in}}}\≈\frac{\mathrm{gdsp}(\mathrm{gmb}4+\mathrm{sCp})}{(\mathrm{sCL}+\mathrm{gdsp}+\mathrm{GL})(\mathrm{sCp}+\mathrm{gmb}4)+\mathrm{Aol}*\mathrm{gmb}4*\left(\mathrm{gdspGL}\right)}$

PSR transition function has a zero point in frequency place, will make system PSR reduce this zero point, but has the generations of two limits soon, and second limit will make system PSR rise to the weakening of PSR at first pole cancellation zero point.Whole system PSR will be made to reduce in the equivalent inductance of higher frequency place load capacitance.

As shown in Figure 4, be the gain-phase curve map of supply voltage 2V output load 200mA.A is phase curve, and B is gain trace.When load 200mA, phase margin is 75.26 °, system stability.

As shown in Figure 5, be the gain-phase curve map of supply voltage 2V output load 0A.A is phase curve, and B is gain trace.When load is 0A, phase margin is 77.15 °, system stability.

Adopt the technology library the same with the present invention, power consumption, load RL and the outer electric capacity CL of sheet, to redesign in background technology put forward the structure of document, Fig. 6 and Fig. 7 compares to the load regulation of this structure LDO and LDO of the present invention and line regulation.

As shown in Figure 6, for supply voltage 2V output load 1us jumps to 200mA by 0A, then the transient response figure of 0A is jumped to by 200mA.A is carried document (Mohammad Al-Shyoukh by background technology, Hoi Leeand and Raul Perez.ATransient-Enhanced Low-Quiescent Current Low-Dropout Regulator With BufferImpedance Attenuation.IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.42, NO.8, AUGUST2007) in, the output voltage of LDO is with the change curve of load, B is the change curve pressure of output voltage with load of LDO of the present invention, and C is the transient changing of load.

Background technology carry the output voltage of LDO in document when load 1us jumps to 200mA by 0A, output voltage could be stablized after 50us, and the peak value of undershoot is 96.2mV, when load 1us jumps to 0A by 200mA, output voltage just stabilizes within 5us, the peak value of upper punch is 30.2mV, and its load regulation is 0.33mV/mA.

The output voltage of LDO of the present invention is when load 1us jumps to 200mA by 0A, output voltage just can be stablized in 5us, and the peak value of undershoot is 2.9mV, when load 1us jumps to 0A by 200mA, output voltage just can be stablized within 5us, and the peak value of upper punch is 2.7mV, low pressure difference linear voltage regulator load regulation of the present invention is 0.0135mV/mA, and low pressure difference linear voltage regulator of the present invention is better than the LDO in background technology far away to the regulation of load.

If Fig. 7 is the transient response figure that supply voltage 1us to be jumped to 3.3V by 2V under output load 200mA.A carries by background technology the change curve of output voltage with input voltage of LDO in document, and B is the change curve pressure of output voltage with input voltage of LDO of the present invention, and C is the transient changing of input voltage.

Background technology carry LDO in document input voltage 1us when jumping to 3.3V by 2V, output voltage is just stable after 50us, and peak-peak is 66.6mV; When supply voltage 1us jumps to 2V by 3.3V, output voltage is just stable after 10us, and peak-peak is 26.8mV.Its line regulation is 1.38%.

When the input voltage 1us of LDO of the present invention jumps to 3.3V by 2V, output voltage is stable in 2us, and peak-peak is 0.694mV; When supply voltage 1us jumps to 2V by 3.3V, output voltage is stable in 2us, and maximum differential pressure is 0.9mV.The line regulation of low pressure difference linear voltage regulator of the present invention is 0.053%, is better than the LDO in background technology far away, and linear modulation rate obtains very large improvement.

If Fig. 8 is the Power Supply Rejection Ratio that output load is respectively 1mA, 10mA, 100mA, 200mA.Wherein, A is the Power Supply Rejection Ratio curve of 1mA, and B is the Power Supply Rejection Ratio curve of 10mA, and C is the Power Supply Rejection Ratio curve of 100mA, and D is the Power Supply Rejection Ratio curve of 200mA.

When output load is 1mA, be-89.41dB when being-69.16dB, 10MHz when being-69.65dB, 1MHz when low frequency PSR is-72.82dB, 100kHz; When output load is 10mA, be-69.28dB when being-55.596dB, 10MHz when being-69.09dB, 1MHz when low frequency PSR is-73.73dB, 100kHz; When output load is 100mA, be-57.84dB when being-61.34dB, 10MHz when being-67.64dB, 1MHz when low frequency PSR is-68.08dB, 100kHz; When output load is 200mA, be-56.8dB when being-68.13dB, 10MHz when being-59.39dB, 1MHz when low frequency PSR is-59.29dB, 100kHz.PSR curve coincidence theory under different loads is analyzed.When frequency is 10MHz, minimum Power Supply Rejection Ratio is-56.8dB, and the present invention effectively improves Power Supply Rejection Ratio, the Power Supply Rejection Ratio particularly under high frequency.

Those of ordinary skill in the art will appreciate that, example described here is to help reader understanding's principle of the present invention, should be understood to that protection scope of the present invention is not limited to and so special statement and example.Above embodiment is only in order to illustrate technical scheme of the present invention.Those of ordinary skill in the art should be appreciated that and can modify to the technical scheme in this direction or equivalent replacement, and does not depart from the spirit and scope of our surface technology scheme, all should be encompassed in the middle of the scope of the present invention.

Claims (6)

1. the high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit, comprise reference voltage source, error amplifier, power voltage input terminal, Correctional tube and resistive feedback circuit, it is characterized in that, also comprise slew rate enhancing circuit and building-out capacitor, the normal phase input end of described error amplifier is connected with reference voltage source, inverting input is connected with resistive feedback circuit, output terminal is connected with the input end of slew rate enhancing circuit, the output terminal of slew rate enhancing circuit is connected with the grid of Correctional tube, the drain electrode of Correctional tube is output terminal, and be connected with resistive feedback circuit, the source electrode of Correctional tube is connected with power voltage input terminal, one end of building-out capacitor is connected with the inverting input of error amplifier, the other end of building-out capacitor is connected with the drain electrode of Correctional tube,

Described slew rate enhancing circuit comprises the 5th PMOS, 6th PMOS, 7th PMOS, 8th PMOS, 6th NMOS tube, 7th NMOS tube, 8th NMOS tube and the 9th NMOS tube, described 5th PMOS and the 6th NMOS tube form the first phase inverter, 7th PMOS and the 7th NMOS tube form the second phase inverter, the input end of the first phase inverter is connected with the output terminal of error amplifier, first inverter output is connected with the 6th PMOS drain electrode and the second inverter input, 6th PMOS grid is connected with its drain electrode, and be connected with the second inverter input, the source electrode of the 6th PMOS is connected with power voltage input terminal, second inverter output is with the 8th NMOS tube grid, drain electrode and the 9th NMOS tube grid are connected, 8th NMOS tube grid is connected with the 9th NMOS tube grid, the source ground of the 8th NMOS tube, 8th POMS tube grid is connected with its drain electrode, and be connected with Correctional tube grid, the source electrode of the 8th PMOS is connected with power voltage input terminal, the source ground of the 9th NMOS tube, its drain electrode is connected with the drain electrode of the 8th PMOS.

2. the high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit as claimed in claim 1, is characterized in that, and described error amplifier is-and three dB bandwidth is greater than the amplifier of 2MHz.

3. the high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit as claimed in claim 1, it is characterized in that, described error amplifier comprises bias voltage input, first PMOS, second PMOS, 3rd PMOS, 4th PMOS, first NMOS tube, second NMOS tube, 3rd NMOS tube, 4th NMOS tube and the 5th NMOS tube, the grid of described first PMOS is connected with the grid of the second PMOS, the grid of the second PMOS is connected with the drain electrode of himself, the drain electrode of the first PMOS is connected with the grid of the 4th NMOS tube, the grid of the 4th NMOS tube is connected with the drain electrode of himself, the grid of the second PMOS is connected with the drain electrode of the first NMOS tube, the grid of the 3rd PMOS is connected with the drain electrode of himself, and be connected with the drain electrode of the second NMOS tube, the grid of the 4th PMOS is connected with the grid of the 3rd PMOS, the drain electrode of the 4th PMOS is connected with the grid of the 5th NMOS tube, the grid of the 5th NMOS tube is connected with the drain electrode of himself, the grid of the first NMOS tube is error amplifier inverting input, the source electrode of the first NMOS tube is connected with the drain electrode of the 3rd NMOS tube, the grid of the second NMOS tube is error amplifier normal phase input end, the source electrode of the second NMOS tube is connected with the drain electrode of the 3rd NMOS tube, first PMOS, second PMOS, the source electrode of the 3rd PMOS and the 4th PMOS is all connected with power voltage input terminal, 3rd NMOS tube, the source electrode of the 4th NMOS tube and the 5th NMOS tube is all connected to ground, the grid of the 4th NMOS tube is connected with the grid of the 5th NMOS tube, the grid of the 3rd NMOS tube is connected with bias voltage input, to produce tail current.

4. the high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit as claimed in claim 1, it is characterized in that, described resistive feedback circuit comprises the first resistance and the second resistance, one end of first resistance is connected with one end of the second resistance, and be connected with the inverting input of error amplifier, the other end of the first resistance is connected with the drain electrode of Correctional tube, and the other end of the second resistance is connected with ground wire.

5. the high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit as claimed in claim 1, is characterized in that, described Correctional tube is PMOS.

6. the high PSR low pressure difference linear voltage regulator of the integrated slew rate enhancing circuit as described in claim 1 or 2 or 3 or 4 or 5, it is characterized in that, also comprise the outer electric capacity of sheet, one end of described outer electric capacity is connected with the drain electrode of Correctional tube, the other end is connected with ground wire, the dead resistance of the outer electric capacity of this sheet is less than 10m Ω, and the capacitance of the outer electric capacity of sheet is greater than 2.2uF.