CN103582945B - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN103582945B CN103582945B CN201380000972.4A CN201380000972A CN103582945B CN 103582945 B CN103582945 B CN 103582945B CN 201380000972 A CN201380000972 A CN 201380000972A CN 103582945 B CN103582945 B CN 103582945B
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- built
- binding post
- inserted plate
- semiconductor chip
- post array
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- Semiconductor Integrated Circuits (AREA)
Abstract
一种半导体器件,包括:半导体芯片、内插板、表面电路图案以及接线柱阵列。表面电路图案形成在内插板的一个表面上并包括连接至半导体芯片的外部连接焊盘的芯片侧焊盘、接合焊盘以及具有连接至芯片侧焊盘的一端且连接至连接焊盘的另一端的互连线。互连线从芯片侧焊盘朝向内插板的外边缘延伸。接线柱阵列包括导电路径以及将导电路径彼此隔离的绝缘树脂。接线柱阵列布置为导电路径在与内插板的表面交叉的方向上延伸。导电路径各具有连接至连接焊盘的一端以及要连接至印刷线路板的另一端。
Description
技术领域
本发明涉及一种包括半导体芯片的封装半导体器件。
背景技术
近年来,越来越期待具有更小的尺寸的这种类型的半导体器件。例如,实际中采用安装在诸如母板的有机材料制成的印刷线路板上的半导体芯片以及与其彼此集成的内插板的封装,即CSP结构。
专利文献1中的半导体器件是包括其中半导体芯片连接至有机材料(树脂)制成的内插板的封装的CSP结构的一个实例。内插板具有多个通孔,且焊球通过通孔暴露在内插板的上及下表面。提供在半导体芯片上的外部连接焊盘连接至内插板的接线柱的上端。接线柱的下端例如借助焊球连接至母板的焊盘。在这种构造中,封装半导体器件仅具有略大于半导体芯片尺寸的尺寸。该尺寸几乎被认为是最小的。
现有技术文献
专利文献
专利文献1:日本未审专利申请公布No.2006-245289
发明内容
本发明解决的问题
上述公知结构是一种三维结构,其中半导体芯片通过在垂直方向上穿过内插板的导电柱连接至印刷线路板。这种结构会造成以下问题。
(1)印刷线路板的布线间距年复一年地变得愈加密集。但是,印刷线路板的布线间距不足以比拟其中微加工硅晶片以获得半导体芯片的半导体工艺的布线间距。它们存在很大不同。例如,常用的半导体芯片包括处于35至75μm间距的外部连接焊盘,且印刷布线板包括处于400至800μm间距的焊盘。
在包括通过包括导电柱的内插板连接的半导体芯片和印刷线路板的公知结构中,需要以相同的间距布置半导体芯片的焊盘以及印刷线路板的焊盘。因此,半导体芯片的外部连接焊盘的间距被印刷线路板的焊盘的间距限制。换言之,在公知的半导体封装中,即使尝试采用基于微设计规则制造的常用的半导体芯片,印刷线路板的焊盘也不能以对应于半导体芯片的外部连接焊盘间距的间距进行布置。因此,不能使用最先进的微半导体芯片。印刷线路板的焊盘的间距是一个瓶颈。这就致使采用具有根据印刷线路板的布线间距的大线宽的半导体芯片或其中仅外部连接焊盘具有较大宽度的独特半导体的设计。因此,即使在门的数量相同的情况下,芯片面积也会变得更大,且因此半导体芯片的成本变得更高。
(2)半导体芯片产生大量的热量并在半导体器件运行时增加其自身温度。在包括树脂内插板的公知结构中,半导体芯片的硅衬底具有与树脂内插板的膨胀系数显著不同的线性膨胀系数的某一值。因此,在半导体芯片和内插板之间的焊接点处产生较大的热应力。这会降低连接可靠性。此外,与硅板相比,树脂内插板具有较高的热阻。半导体芯片上产生的热量较小可能向内插板流动,且因此半导体芯片具有较高温度,且焊接点处的热应力会进一步增大。
(3)内插板具有其中接线柱被布置在通孔中的三维结构。因此,需要包括形成通孔、电镀通孔的内表面、在通孔中施加焊膏以及回流焊的多个工艺。这会增加生产成本。
本发明的一个目的是提供一种半导体器件,其能在不受印刷线路板的布线间距的限制的情况下采用常规微半导体芯片并具有导电接头的高可靠性,且能进一步以更低价格生产。
解决问题的手段
本文公开的半导体器件是一种要安装到印刷线路板上的半导体器件。该半导体器件包括具有预定的半导体集成电路以及布置为将半导体集成电路连接至外部电路的外部连接焊盘的半导体芯片、由硅或玻璃制成的内插板、形成在内插板的一个表面上的表面电路图案以及包括了多个导电路径以及将导电路径彼此绝缘的绝缘树脂的接线柱阵列。表面电路图案包括提供在内插板的表面上并连接至半导体芯片的外部连接焊盘的芯片侧焊盘、接合焊盘以及具有一端连接至芯片侧焊盘且另一端连接至连接焊盘的互连线。接线柱阵列布置为导电路径在与内插板的表面相交的方向上延伸。导电路径各具有连接至连接焊盘的一端以及要连接至印刷线路板的另一端。互连线从芯片侧焊盘向内插板的外边缘延伸。
在半导体器件中,半导体芯片的外部连接焊盘通过形成在内插板的表面上的表面电路图案并通过接线柱阵列连接至印刷线路板。在表面电路图案中,互连线之间的间距在外边缘侧,即在接合焊盘侧较宽,因为连接至将要连接至半导体芯片的外部接合焊盘的芯片侧焊盘的互连线向内插板的外边缘延伸并连接至接合焊盘。换言之,内侧处的芯片侧焊盘的形成间距可小于接合焊盘的形成间距。因此,可在不受印刷线路板的布线间距的限制的情况下使用具有微间距的公知半导体芯片。
内插板的表面电路图案是不需要通孔的平面电路。内插板由作为包括SiO2作为主要成分的扁平绝缘体的硅或玻璃制成,且因此微表面电路图案可通过在半导体制造工艺中常用的薄膜形成工艺或金属微加工工艺形成在内插板上。因此生产成本低廉。
此外,作为热源的半导体芯片在其电路表面面向上的情况下安装在内插板的背面上。半导体芯片的背面通常位于邻近印刷线路板。借助这种构造,半导体芯片上产生的热量通过内插板和印刷线路板耗散,且可抑制半导体芯片的温度升高。特别地,如果具有低热阻的诸如硅橡胶的导热材料布置在半导体芯片和印刷线路板之间的空间中,则半导体芯片的热量传导至具有较大面积的印刷线路板,且热量可通过器件外壳耗散。上述散热结构对于例如不具有风扇冷却器的移动信息装置的较小和较薄的外壳是最有效和廉价的。这是采用包括不具有通孔的内插板的平面电路结构的封装结构的一个独特的优势。
内插板和半导体芯片具有基本上相同的线性热膨胀系数。即使在半导体芯片和内插板之间存在较大温差时,与包括由树脂制成的内插板的公知结构相比,作用于半导体芯片和内插板之间的导电接头上的热应力也足够小。这改善了接头的可靠性。
另一方面,由硅或玻璃制成的内插板和通常由树脂制成的印刷线路板之间的线性热膨胀系数的差相对较大。在本发明中,内插板和印刷线路板通过接线柱阵列连接。接线柱阵列包括通过绝缘树脂彼此绝缘的导电路径并布置为使导电路径在垂直于内插板的表面的方向上延伸。借助这种构造,可在导电路径随绝缘树脂弯曲时吸收热应力。因此,处于这部分中的接头的可靠性可保持在较高水平。
而且,本发明的半导体器件优选包括用于半导体芯片的电源***的旁路电容器或用于内插板的表面上的I/O端子的钳位二极管。这些无源器件对于半导体芯片的操作来说是必不可少的。因为公知结构使用树脂板作为内插板,因此较少的离散部件安装在内插板或印刷线路板上。在本发明中,因为内插板由硅或玻璃制成,因此旁路电容器或钳位二极管可通过常用微加工工艺形成在表面上。因此,可将根据本发明的半导体器件视为其中封装半导体芯片所需的无源器件的高功能半导体部件。
如果无源器件与集成电路一起形成在半导体芯片上,则需要增加面积。这会增加半导体芯片的尺寸,这又会增加每个半导体芯片的价格。但是在本发明中,可降低每个芯片的价格,因为具有高密度晶体管的集成电路形成在半导体芯片上。此外,考虑到内插板被制成陶瓷,需要较大面积的上述无源器件形成在具有充足面积的内插板上。这就允许非常实用和有效的设置。如果需要改变旁路电容器或钳位二极管的特性,则仅需改变内插板。这就能对规格改变进行灵活响应。
用于I/O端子的电源端子(VDDQ,VSSQ)提供在与用于内部逻辑电路的电源端子(VDD,VSS)隔离的I/O端子的两侧,这是因为相对较大的电流流至诸如半导体存储器的半导体芯片的I/O端子或从其流出。对于半导体器件的高速操作来说,除所有电源端子都连接至电源线之外,旁路电容器优选相邻连接于半导体芯片中的输出晶体管的电源线,以便以高速提供电荷。有鉴于此,在公知结构中,作为旁路电容器的离散构件安装在印刷线路板的表面上或其内,以便旁路电容器和上述电源端子通过印刷线路板的电路图案连接。
但是,当离散构件安装在印刷线路板上时,离散构件布置为在俯视图中不与半导体芯片重叠。半导体芯片的离散构件和电源端子(用于特别需要连接至旁路电容器的I/O端子的电源端子VDDQ、VSSQ)通过具有某一长度的铜箔图案连接。随后,铜箔图案不可避免地具有半导体芯片的旁路电容器和电源端子之间的电感。这会不利地影响半导体芯片的高速响应性。
在本发明中,包括下表面电极、电介质以及上表面电极的旁路电容器形成在内插板的表面上,且用于半导体芯片的I/O电源的外部接合焊盘连接至表面电极。因此,旁路电路器布置在与半导体芯片重叠的区域中,且电源端子和旁路电容器以它们之间的最短距离连接。这种构造能最小化互连的电感并能充分利用旁路电容器的电容,且因此改善了半导体芯片的响应性。
接线柱阵列被制造为与半导体芯片或内插板分隔开的构件并连接至内插板。因此,内插板的产量完全不受影响,且能保持半导体器件的高生产率。此外,因为接线柱阵列与半导体芯片分离地制造,因此其规格可被标准化为适用于各种半导体芯片的通用构件。因此,无需针对各种类型的半导体芯片的特殊设计,且因此可大幅降低开发成本以及用于可靠性测试的成本。此外,可显著降低半导体芯片的封装成本,因为接线柱阵列具有将通过回流焊连接至半导体芯片的的外部连接焊盘的简化结构。
多个接线柱阵列可用于单一内插板。接线柱阵列彼此空间间隔并连接至半导体芯片。借助这种构造,接线柱阵列可更自由地变形,且因此考虑到热应力松弛,这种构造是优选的。
可通过在与金属线相交的方向上切割包括多个金属线以及绝缘树脂的基础构件来制造接线柱阵列。金属线布置为它们的轴彼此平行并通过绝缘树脂彼此分隔开。
如果导电路径通过电镀形成,则较长的导电路径会造成较长的生产时间。但是,即使接线柱阵列被制造为厚(具有较长的金属线),生产时间也不会延长,这是因为通过切割包括金属线和围绕金属线的绝缘树脂的用于接线柱阵列的基础构件,以使得在基本上垂直于其轴的方向上切断金属线来制造接线柱阵列。此外,这种接线柱阵列具有高生产率,这是因为可容易地处理随树脂一起硬化的接线柱阵列。
此外,可通过调整切割间隔来设定接线柱阵列的厚度(对应于绝缘树脂的厚度以及金属线的长度)。因此,可通过将绝缘树脂的厚度设定为适于可能基于内插板和印刷线路板之间的线性热膨胀系数的差异而发生的热应力松弛的厚度而进一步提高接头的可靠性。
在上述接线柱阵列中,为了降低热应力,绝缘树脂优选具有为内插板的线性热膨胀系数和印刷线路板的线性热膨胀系数之间的中间值的线性热膨胀系数。
本发明的有益效果
在本发明的半导体器件中,电路图案可在内插板上延伸。因此,以小间距布置的半导体芯片的电极在不受印刷线路板的宽布线间距的限制的情况下被连接。而且,导电接头的可靠性较高,这是因为热量可能直接从半导体芯片的背面向印刷线路板耗散,并降低热应力。此外,可以更低成本制造半导体器件。
附图说明
图1是示出安装在电路板上的本实施例的半导体器件的截面图。
图2是本实施例的半导体器件的底视图。
图3是示出半导体芯片的焊盘排列的俯视图。
图4是示出内插板的电路图案以及无源器件的简化等效电路图。
图5是示出旁路电容器的结构的放大截面图。
图6A是示出旁路电容器的制造步骤的俯视图。
图6B是示出旁路电容器的制造步骤的俯视图。
图6C是示出旁路电容器的制造步骤的俯视图。
图7是接线柱阵列的放大截面图。
图8是示出本实施例的半导体器件的制造步骤的俯视图,其中从硅晶片取出半导体器件。
图9是示出接线柱阵列的制造步骤的截面图。
图10是示出接线柱阵列的变型的放大截面图。
图11是示出其中内插板具有多级构造的另一实施例的分解截面图。
图12是示出其中半导体器件具有多级构造的另一实施例的截面图。
图13是示出具有不同结构的旁路电容器的放大截面图。
具体实施方式
参考图1至图9描述本发明的第一实施例。
1.半导体器件的构造
图1是示出第一实施例的半导体器件1的示意截面图。半导体器件1包括内插板10、半导体芯片20以及多个接线柱阵列30。通过借助回流焊料40将半导体芯片20和接线柱阵列30连接至内插板10的一个(下)表面来封装半导体器件。封装半导体器件1通过接线柱阵列30安装在公知的印刷线路板50上。印刷线路板50包括有机材料(树脂),例如,印刷线路板由玻璃环氧树脂制成。
半导体芯片20具有包括硅衬底和预定半导体集成电路(未示出)的公知构造。半导体集成电路提供在硅衬底的一个表面(图1中的上表面)上并包括多个半导体元件。半导体芯片20例如具有在一侧上为5mm的矩形形状。在半导体芯片20的上表面上,提供电源端子和用于输入和输出端子(图3)的外部连接焊盘21。电源端子被配置为将半导体集成电路通过钝化膜中的开口连接至外部电路。如图2中所示,外部连接焊盘21布置在沿半导体芯片20的外边缘延伸的方形框架形区域中。例如,总共512个焊盘以70μm的间距交错方式排列成两行。
图3中示出外部连接焊盘21的特定排列。此处,示出具有64位的I/O端子的LSI。在方形框架形区域的相对两侧(位于图3中的右侧和左侧上,未示出右侧上的一侧)上,用于I/O端子的电源端子VDDQ和VSSQ交替排列,以便两个I/O端子位于其间。在另两侧(图3中的上和下侧)上,例如提供用于控制信号的端子CTRL#((#是任意自然数)、用于数据输入的端子DIN#、用于内部逻辑电路的电源端子VDD#、VSS#以及用于时钟信号的端子CLK。
通过将硅晶片或玻璃衬底切割成片来制造内插板10。内插板10例如具有一侧上为7mm的矩形形状。在内插板10的一个表面上,通过公知布线技术形成表面电路图案和各种无源器件。以下将详细说明表面电路图案。在图4中,在等效电路图中示出内插板10的表面电路图案11以及与表面电路图案11一起形成的各种无源器件。因为焊盘的实际数量非常大,因此在图4中,焊盘的数量降至每侧上四个。实际上,如图2中所示,在一侧上提供128个焊盘。
如图4中所示,在为对应于半导体芯片20的外部连接焊盘21的矩形框架形状区域的内插板10的中间区域中,以与外部连接焊盘21相同的数量和尺寸以及以相同的间距提供芯片侧焊盘12。在沿内插板10的外边缘延伸的矩形框架形区域中,以与外部连接焊盘21相同的数量提供接合焊盘13。接合焊盘13和芯片侧焊盘12的数量相同,且芯片侧焊盘12位于内插板10的内侧且接合焊盘13位于内插板10的外侧的矩形框架形区域中。外侧的面积大于内侧的面积。因此,接合焊盘13之间的间距(例如具有以250μm的间距排列的125μm直径的焊盘)大于芯片侧焊盘12之间的间距。在芯片侧焊盘12和相应的接合焊盘13之间,互连线14被布置为从芯片侧焊盘12向内插板19的外边缘延伸。
在内插板10上,除了上述表面电路图案11之外,如图4的等效电路中示意性示出的,通过薄膜形成工艺或金属微加工工艺形成各种无源器件。用于阻抗匹配的阻尼电阻器16提供在连接至半导体芯片20的I/O端子I/O0至I/O3的芯片侧焊盘12和相应的接合焊盘13之间。钳位二极管15提供在连接至I/O端子I/O0至I/O3的互连线14和连接至用于I/O端子的电源端子VDDQ和VSSQ的互连线14之间。此外,上拉电阻器17(或下拉电阻器)提供在连接至I/O端子I/O0至I/O3的互连线14和连接至用于I/O端子的电源端子VDDQ的互连线14之间。
阻尼电阻器16优选具有通过多晶硅的布线电阻或金属电阻获得的相对低的电阻(10至50Ω)。钳位二极管15是用于过压钳位的ESD保护电路且需要具有相对高的耐压和快速响应。优选地,可使用沿相对长的金属线(100至500μm)延伸的PN结或者可通过两种金属和SiO2层构成肖特基势垒二极管以具有快速钳位。上拉电阻器17(或上拉电阻器)通常具有约4.7KΩ或以上的高阻值。通过使用其中P衬底用作内插板10以具有N阱且扩散P+以获得扩散电阻器以及其中具有高特定电阻(例如Ni,Cr)的金属镀层以使这种类型的电阻器具有高电阻并具有小的资源占用。
在连接至用于I/O端子VDDQ、VSSQ的电源端子的各对芯片侧焊盘12之间,在与半导体芯片20的安装区域重叠的区域中提供旁路电容器,即直接位于半导体芯片20上。在作为示意图的图4中,仅示出四个旁路电容器18。但是,实际上为各对用于I/O端子的电源端子都提供旁路电容器18(对用于64位I/O的32对电源端子提供32个旁路电容器,或者如果对各对电源端子提供多个旁路电容器,则为32n个旁路电容器,其中n表示用于各对电源端子的旁路电容器的数量)。
各个旁路电容器18都具有图5中所示的构造并如下制造。在内插板10的一个表面(下表面)上,通过金属溅射或电镀形成第一表面电极18A。它们中的每一个都连接至一对电源端子中的一个。如图6A中所示,第一表面电极18A的延长线部分18B以及用于I/O端子的信号布线18C优选由相同金属形成且与第一表面电极18A同时形成,从而简化步骤。
随后,如图6B中所示,由诸如ITO或STO的金属氧化物膜制成的介电层18D形成在整个第一表面电极18A上,以便介电层18D用作为所有旁路电容器18所共用的一个介电层。介电层可分离地形成在各个第一表面电极18A上。
介电层18D优选通过与本申请为同一申请人申请的未审专利申请公布No.2008-141121中公开的气溶胶沉积方法形成。具体而言,通过超声波振动并与载气一起加热来雾化其中溶解了作为介电层的材料的金属氧化物的溶液,同时将其提供在硅板或玻璃板上。例如将硅板或玻璃板加热至几百度以形成金属氧化物的薄膜。
随后,通过与第一表面电极18A相同的溅射或电镀将第二表面电极18E形成在介电层18D上。第二表面电极18E各具有与第一表面电极18A的形状和尺寸相同的矩形形状。除延长线部分18F位于关于信号布线18C的相对侧上之外(参见图6C),以与第一表面电极18A相同的方式整体形成延长线部分18F。因此,如图5中所示,形成各包括依次位于内插板10上的第一表面电极18A、介电层18D以及第二介电电极18E的旁路电容器18以用于用作I/O端子VDDQ、VSSQ的各对电源端子。
在如上形成旁路电容器18之后,将半导体芯片20布置为与上述半导体芯片20重叠。旁路电容器18中包括的第一和第二表面电极18A,18E的延长线部分18D,18F用作将半导体芯片20连接至内插板10的连接盘。在半导体芯片20的外部连接焊盘21中,I/O端子I/O#,I/O#+1以及用于I/O端子的一对电源端子VDDQ、VSSQ通过回流焊连接至信号线18C,第一表面电极18A的延长线部分18B以及第二表面电极18E的延长线部分18F。
如图7中所示,接线柱阵列30包括作为绝缘树脂32中的导电路径的金属线34。绝缘树脂32围绕金属线34以使金属线34彼此绝缘且在它们之间保持恒定的间隔(排列间隔)。金属线34的端面与绝缘树脂32的端面齐平。将在下文说明接线柱阵列30的制造方法。绝缘树脂32是具有小于印刷线路板50(约15ppm)并大于包括在半导体芯片20中的硅衬底(约4ppm)的线性热膨胀系数的合成树脂。绝缘树脂32具有柔性以允许金属线34弯曲变形。
在将要连接至内插板10的接线柱阵列30的上表面32A上,通过用金进行薄镀形成第一焊盘36以与金属线34的端面重叠。类似地,在将要连接至印刷线路板50的焊盘51的接线柱阵列30的下表面32B上,通过用金进行薄镀形成第二焊盘38以与金属线34的端面重叠。第一焊盘36和第二焊盘38以预定间距提供在绝缘树脂32的正面和背面上以便对应于金属线34。在各个第一焊盘36和各个第二焊盘38的正面上附接焊球并将其熔化以形成焊料块40。
如上所述,在沿内插板10的外边缘延伸的矩形区域中,接合焊盘13以预定间距并以矩阵形式布置在内插板10的下表面上。具有上述构造的接线柱阵列30包括四个接线柱阵列30A至30D。接线柱阵列30A至30D例如分离地附接至矩形形状的每一侧。接线柱阵列30A至30D共同地制造作为用于将被切割为接线柱阵列30A至30D片段的接线柱阵列的基础构件。将在下文说明其制造方法。
接线柱阵列30A至30D以及半导体芯片20在晶圆级安装在内插板10上。具体而言,如图8中所示,在通过薄膜形成工艺或金属微加工将对应于各个内插板10的布线图案以及无源器件提供在硅晶片60上以形成内插板10之后且在将硅晶片60通过划片切割成片之前,将接线柱阵列30A至30D以及半导体芯片20布置在硅晶片60的预定位置。随后,通过回流焊连接接线柱阵列30A至30D。随后,用胶带粘接硅晶片60的背面且沿划片线切割硅晶片60以将硅晶片60分割成内插板10。因此,内插板10各整体地包括接线柱阵列30A至30D以及半导体芯片20,即一次制成半导体器件1。在图8中,出于简化的目的,仅示出12个半导体芯片20,这是因为半导体芯片20的实际数量非常大。
2.接线柱阵列30的制造方法
以下将参考图9说明接线柱阵列30的制造方法的实例。
在本实例中,以绝缘树脂32和金属线34来制造接线柱阵列30。绝缘树脂32包括层间隙物32A和行间隙物32B。层间隙物32A将沿图9中的上和下方向排列的金属线34彼此隔离。行间隙物32B将沿图9中的右至左方向排列的金属线34彼此隔离。绝缘树脂32可以是通过热或紫外线固化的任何类型的公知绝缘树脂。
由这种类型的树脂制成的层间隙物32A在其表面上具有粘性。层间隙物32A例如是具有约400μm厚度的平片材。行间隙物32B具有四棱柱形状,其例如具有约400μm的厚度和约400μm的宽度。可使用具有平行缝隙的一个树脂代替行间隙物32B。金属线34例如具有400μm直径的圆柱形形状。金属线34由诸如铜、铜合金或铝的低阻金属制成。
在接线柱阵列30的制造中,金属线34和行间隙物32B彼此平行的交替排列在层间隙物32A的表面上以形成单元结构片材35。金属线34的轴线方向对应于垂直图8的平面的方向。因此,单元结构片材35具有包括位于层间隙物32A的一个表面上的金属线34和行间隙物32B的层。该层具有125μm的厚度。
随后,单元结构片材35在层间隙物32A的厚度方向上彼此附接以形成层结构。在层结构的厚度方向和宽度方向上稍微施压以消除间隙。热或紫外线施加至层结构以固化层间隙物41和行间隙物42(这不意味着完全失去柔性)。因此,通过层间隙物32A和行间隙物32B保持金属线34以使其彼此平行且其间具有间隔。金属线34仿佛是嵌入绝缘树脂中。各具有125μm直径的金属线34以250μm的间距排列。
例如,沿与金属线34相交的平面以200μm或500μm的间隔切开固化的层结构,使得将层结构切开成多个片材。因此,切割绝缘树脂和金属线34以提供用于接线主阵列的基础构件(未示出),其包括具有对应于切割间隔的厚度的绝缘树脂32以及具有对应于切割间隔的长度并排列在树脂层中的金属线34。随后,对基础构件的各个表面执行金薄镀以在金属线34的各个端部上形成焊盘。此外,通过印刷或光刻形成在对应于焊盘的位置具有开口的保护膜。将焊球布置在开口上并执行热处理以获得用于其上附接焊料块的接线柱阵列的片状基础构件。
随后,将用于接线柱阵列的基础构件切割成各包括预定数量的金属线34的片,以形成接线柱阵列30A至30D。例如,各个接线柱阵列30A至30D都是包括如图2中所示的排列成四行以及三十二列的总计128个金属线34的片。接线柱阵列的片(图2中的四片)都连接至半导体芯片20。排列接线柱阵列30A至30D以使相邻的接线柱阵列在基本上垂直于彼此的方向上延伸且其间具有空隙。接线柱阵列30A至30D例如都安装为与半导体芯片20的各个电极端子14接触并通过回流焊与其连接。接线柱阵列30A至30D通过回流过程中熔化的焊料的表面张力悬置于半导体芯片20上且自然地移动至最优的连接位置。即这就允许自对准操作。
3.本实施例的效果
本实施例的半导体器件1包括内插板10,其上集成了半导体芯片20和接线柱阵列30。因此,半导体器件1可用作一个独立的封装构件。借助这种构造,半导体芯片20通过形成在内插板10上的表面电路图案11以及接线主阵列30连接至印刷线路板50。
表面电路图案11从位于内插板10的中心的电路芯片20向接合焊盘13放射性地向外延伸。位于内插板10中部的相邻芯片侧焊盘12之间的间距小于位于靠近内插板10的外边缘一侧的相邻接合焊盘13之间的间距。因此,即使靠近外边缘一侧的接合焊盘13之间的间距由于印刷线路板50的布线间距的限制而相对大,位于内侧的芯片侧焊盘12之间的间距也足够小。因此,可使用具有常规微间距的半导体芯片20。
内插板10的表面电路图案11是不包括通孔的平面电路。内插板10由硅或玻璃制成。可通过具有高精度等级的常规半导体工艺形成微表面电路图案11,且因此内插板10可以低成本制造。
内插板10由作为半导体芯片20的材料的硅或玻璃衬底形成。半导体芯片安装在内插板的背面上,以便其电路表面面对上侧且其背面面对下侧。半导体芯片的整个背面相邻印刷线路板布置且半导体芯片例如在半导体芯片的大面积硅平面处通过硅橡胶接触印刷线路板50。因此,半导体芯片20具有高散热特性,使得半导体芯片20的温度不太可能升高。
而且,内插板10和半导体芯片20具有基本上相同的线性热膨胀系数。因此,即使半导体芯片20和内插板10具有温差,与包括由树脂制成的内插板的公知结构相比,作用于半导体芯片20和内插板10之间的焊接点上的热应力也明显小。因此电接头可靠性高。
在由硅或玻璃制成的内插板10和通常由树脂制成的印刷线路板50之间线性热膨胀系数存在相对大的差异。在本实施例中,内插板10和印刷线路板50通过接线柱阵列30连接。接线柱阵列30布置为使其金属线34在垂直于内插板10的表面的方向上延伸。金属线34通过绝缘树脂32彼此隔离。借助这种构造,金属线34在内插板10的平面方向上与绝缘树脂32一起弯曲,从而吸收热应力。因此,可进一步高度保持焊接点部分的可靠性。
而且,在本实施例中,内插板10是通过薄膜形成工艺或金属微加工工艺允许无源器件形成和微布线的硅板或玻璃板。因此,表面电路图案11形成在内插板10上且半导体芯片20的稳定操作所需的诸如钳位二极管15和电阻器17的无源器件形成在内插板10上。因此,本实施例的半导体器件1可加工为包括对半导体芯片20的操作来说必不可少的半导体芯片20和无源器件的一个封装构件。因此,可简化印刷线路板50的电路构造。如果无源器件15至17与集成电路一起形成在半导体芯片20上,则会增加所需面积。这种半导体芯片尺寸的增加会增加每个半导体芯片的价格。但是在本发明中,减小所需面积并可降低每个芯片的价格,这是因为仅在半导体芯片上形成作为有源器件的具有高密度晶体管的集成电路。如果需要改变无源器件的特征,则仅需改变内插板10即可。这就能对规格改变进行灵活响应。
当半导体存储器或图像处理芯片用作半导体芯片时,相对大的电流被输入至半导体芯片的I/O端子或从其输出。因此,在本实施例中(参见图3),用于I/O端子(VDDQ、VSSQ)的电源端子提供在与用于内部逻辑电路的电源端子(VDD、VSS)隔离的I/O端子的两侧。对于半导体芯片20的高速操作来说,除了所有电源端子都连接至电源线之外,旁路电容器优选连接至电源线以便以高速提供电荷。在本实施例中,鉴于内插板10由能通过薄膜形成工艺或金属微加工工艺处理的硅板或玻璃板制成,包括下表面电极18A、介电层18D以及上表面电极18E的旁路电容器18形成在与半导体芯片20重叠的内插板10的表面区域中。用于半导体芯片20的I/O电源(VDDQ、VSSQ)的外部连接焊盘21连接至电极18A和18E。电源端子(VDDQ、VSSQ)和旁路电容器18之间的距离最小。因此,布线的电感可被最小化以充分利用旁路电容器18的电容并提高半导体芯片20的响应性。
通过在与金属线34相交的方向上切割包括金属线34的基础构件获得本实施例的接线柱阵列30,所述金属线34被布置为其轴在相同方向上延伸且与绝缘树脂32彼此间隔开。接线柱阵列30不会影响内插板10的生产量,这是因为接线柱阵列30与半导体芯片20和内插板10分离制造并附接至内插板10。可高度保持半导体器件1的生产率。因为接线柱阵列30与半导体芯片20分离制造,因此其规格可被标准化为可应用至各种半导体芯片20的通用构件。因此,无需用于各种类型的半导体芯片20的特殊设计,且因此可大幅降低开发成本以及用于可靠性测试的成本。此外,可显著降低半导体芯片20的封装成本,这是因为接线柱阵列30具有将要通过回流焊连接至半导体芯片20的外部连接焊盘的简化结构。
而且,如果通过电镀形成导电路径,则更长的导电路径会导致更长的生产时间。但是,即使将接线柱阵列30制造得厚(具有较长的金属线34),生产时间也不会更长,这是因为通过切割用于接线柱阵列的、包括有金属线34和围绕金属线34的绝缘树脂32的基础构件以使得在基本上垂直于其轴的方向上切断金属线34来制造接线柱阵列30。此外,接线柱阵列30具有高生产率,这是因为可容易地处理与树脂一同硬化的接线柱阵列30。
而且,可通过调整切割间距来设定接线柱阵列30的厚度(对应于绝缘树脂32的厚度和金属线34的长度)。因此,可通过将绝缘树脂32的厚度设定为适于可能基于内插板10和印刷线路板50之间的线性热膨胀系数的差异而发生的热应力松弛的厚度而进一步提高焊接点的可靠性。此外,在本实施例中,接线柱阵列30(四个接线柱阵列)连接至单个内插板10。接线柱阵列30彼此间隔。借助这种构造,接线柱阵列30可更自由地改变其形状,这在热应力松弛方面是有利的。
<其它实施例>
本发明不限于上述说明书和附图中描述的上述实施例。例如,以下方面同样被包括在本发明的技术范围内。
(1)在上述实施例中,接线柱阵列30包括绝缘树脂32以及布置在绝缘树脂32中的金属线34,但是本发明不限于此。可使用包括通过绝缘树脂而彼此绝缘的导电路径的任何接线柱阵列。导电路径不限于金属线,而可以是金属箔。此外,金属线不限于由铜或铜合金制成的金属线,且可由诸如铝的低阻金属材料制成或可以是多芯线。
(2)当利用金属线制造接线柱阵列时,金属线34的布置不限于其中金属线34通过单元结构片材35或层间隙物32A分隔开的布置。例如,可集束包括由热粘合树脂涂覆的金属线的电线并可固化热粘合树脂。随后,可切开集束电线以在与金属线的轴交叉的方向上切割金属线。
(3)在上述实施例中,接线柱阵列30的每个金属线34都对应于一个第一焊盘36和一个第二焊盘38,但是本发明不限于此。如图10中所示,一个第一焊盘36和一个第二焊盘38可对应于各具有小于第一和第二焊盘36、38直径的直径的多个金属线34。借助这种构造,在接线柱阵列30的制造中,即使第一焊盘36和第二焊盘38被放置处于远离预定位置,至少一个金属线34也能接触第一和第二焊盘36、38。这种构造不需要焊盘35、36的形成的高精度,这致使生产率提高。
(4)在上述实施例中,接线柱阵列30连接半导体芯片20和由玻璃环氧树脂制成的印刷线路板50。但是,电路板可以不是诸如玻璃环氧树脂的有机材料制成的电路板。电路板可以是硅板、玻璃板或由诸如半导体的其他无机材料制成的电路板。
(5)内插板10的板可以由诸如硼硅酸玻璃、石英玻璃或钠玻璃的玻璃制成,只要能执行薄膜形成和金属微加工即可。
(6)在上述实施例中,单一半导体芯片20安装在单一内插板10上。但是,多个半导体芯片20可安装在单一内插板10上。此外,如图11中所示,内插板可具有多级构造。在多级构造中,其中半导体芯片20和接线柱阵列30安装在内插板10上的半导体器件1通过接线柱阵列30连接至由硅或玻璃制成的辅助内插板200,且半导体器件1通过附接至辅助内插板100的接线柱阵列300连接至印刷线路板。未示出印刷线路板。借助这种构造,通过薄膜形成或金属微加工而在内插板100上具有***电路可使半导体器件1具有多种功能。此外,如图12中所示,半导体器件1可被配置为半导体多芯片封装,以便进一步具有多功能性。半导体多芯片封装是通过具有多级构造而三维构造的,多级构造包括通过接线柱阵列30,300连接的多个内插板10,100。在这种情况下,除位于顶部的内插板之外的内插板都由玻璃制成,这是因为它们之间需要在先前和后续步骤之间形成用于电连接的通孔。
(7)在上述实施例中,如图5中所示,旁路电容器18被配置为以使连接至电源端子VDDQ和VSSQ中的一个的第一表面电极18A形成在内插板10的表面上,且连接至另一个的第二表面电极18布置在第一表面电极18A上,且以介电层18D置于其间。但是,本发明不限于此。可使用具有如图13中所示构造的旁路电容器65。在这种构造中,首先,中间电极61提供在内插板10的表面(优选地,整个表面)上。中间电极61可以是通过溅射或电镀形成的金属表面电极。如果内插板10由硅制成,则可使用具有低电阻(几十欧姆或以下)的P型或N型扩散层代替金属电极。随后,与上述实施例相同,介电层62提供在中间电极61的表面(优选地,整个表面)上。当中间电极61和介电层62提供在整个表面上时,无需用于掩模或蚀刻的光刻工艺。随后,可通过掩模或蚀刻形成第一表面电极63和第二表面电极64,并通过焊料连接至电源端子VDDQ和VSSQ。
附图标记说明
1:半导体器件,10,100:内插板,11:表面电路图案,12:芯片侧焊盘,13:接合焊盘,14:互连线,15:钳位二极管,18:旁路电容器,18A,18E:表面电极,20:半导体芯片,30,300:接线柱阵列,32:树脂层,34:金属线,40:焊接点,50:印刷线路板。
Claims (5)
1.一种要被安装到印刷线路板上的半导体器件,所述半导体器件包括:
半导体芯片,所述半导体芯片包括预定的半导体集成电路以及被配置为用于将所述半导体集成电路连接至外部电路的外部连接焊盘;
内插板,所述内插板由硅或玻璃制成;
表面电路图案,所述表面电路图案形成在所述内插板的一个表面上,所述表面电路图案包括:
芯片侧焊盘,所述芯片侧焊盘被提供在所述内插板的表面上并连接至所述半导体芯片的所述外部连接焊盘;
接合焊盘,以及
互连线,所述互连线具有连接至所述芯片侧焊盘的一端和连接至所述接合焊盘的另一端,所述互连线从所述芯片侧焊盘朝向所述内插板的外边缘延伸;
接线柱阵列,所述接线柱阵列包括多个导电路径以及将所述导电路径彼此绝缘的绝缘树脂,所述接线柱阵列被布置为以使得所述导电路径在与所述内插板的表面交叉的方向上延伸,所述导电路径各自具有被连接至所述接合焊盘的一端以及要被连接至所述印刷线路板的另一端;以及
用于所述半导体芯片的电源***的旁路电容器,所述旁路电容器形成在其上形成有所述表面电路图案的所述内插板的表面上,并且形成在与所述半导体芯片重叠的区域中。
2.根据权利要求1所述的半导体器件,其中,
通过焊接来将用于I/O电源的所述外部连接焊盘连接至表面电极,该表面电极形成在所述内插板的表面上并且被包含在所述旁路电容器中。
3.根据权利要求1所述的半导体器件,其中,
通过在与多个金属线相交的方向上切割包括所述多个金属线以及绝缘树脂的基础构件来制造所述接线柱阵列,所述多个金属线被布置为以使得各金属线的轴彼此平行并且通过所述绝缘树脂彼此分隔开。
4.根据权利要求2所述的半导体器件,其中,
通过在与多个金属线相交的方向上切割包括所述多个金属线以及绝缘树脂的基础构件来制造所述接线柱阵列,所述多个金属线被布置为以使得各金属线的轴彼此平行并且通过所述绝缘树脂彼此分隔开。
5.根据权利要求1至4中的任一项所述的半导体器件,其中,
所述接线柱阵列包括多个接线柱阵列,并且
所述接线柱阵列彼此分隔开并且被连接至所述半导体芯片。
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US (1) | US9153549B2 (zh) |
EP (1) | EP2704189B1 (zh) |
JP (1) | JP5474127B2 (zh) |
KR (1) | KR101531552B1 (zh) |
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2012
- 2012-05-14 JP JP2012110753A patent/JP5474127B2/ja not_active Expired - Fee Related
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2013
- 2013-02-12 US US14/005,941 patent/US9153549B2/en not_active Expired - Fee Related
- 2013-02-12 CN CN201380000972.4A patent/CN103582945B/zh not_active Expired - Fee Related
- 2013-02-12 EP EP13766876.0A patent/EP2704189B1/en not_active Not-in-force
- 2013-02-12 WO PCT/JP2013/053218 patent/WO2013172060A1/ja active Application Filing
- 2013-02-12 KR KR1020137024769A patent/KR101531552B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
EP2704189B1 (en) | 2018-08-29 |
JP5474127B2 (ja) | 2014-04-16 |
US20140070368A1 (en) | 2014-03-13 |
JP2013239530A (ja) | 2013-11-28 |
WO2013172060A1 (ja) | 2013-11-21 |
KR20140012680A (ko) | 2014-02-03 |
KR101531552B1 (ko) | 2015-06-26 |
EP2704189A4 (en) | 2015-10-07 |
CN103582945A (zh) | 2014-02-12 |
US9153549B2 (en) | 2015-10-06 |
EP2704189A1 (en) | 2014-03-05 |
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