CN103579030A - 一种新型芯片封装方法及芯片封装结构 - Google Patents
一种新型芯片封装方法及芯片封装结构 Download PDFInfo
- Publication number
- CN103579030A CN103579030A CN201310529964.0A CN201310529964A CN103579030A CN 103579030 A CN103579030 A CN 103579030A CN 201310529964 A CN201310529964 A CN 201310529964A CN 103579030 A CN103579030 A CN 103579030A
- Authority
- CN
- China
- Prior art keywords
- chip
- copper
- layer
- double face
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000005538 encapsulation Methods 0.000 title abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 106
- 229910052802 copper Inorganic materials 0.000 claims abstract description 104
- 239000010949 copper Substances 0.000 claims abstract description 104
- 239000002184 metal Substances 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002131 composite material Substances 0.000 claims abstract description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 16
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000012545 processing Methods 0.000 claims abstract description 11
- 229910052709 silver Inorganic materials 0.000 claims abstract description 9
- 239000004332 silver Substances 0.000 claims abstract description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 8
- 238000003825 pressing Methods 0.000 claims abstract description 8
- 229910052718 tin Inorganic materials 0.000 claims abstract description 8
- 239000003292 glue Substances 0.000 claims abstract description 5
- 239000003822 epoxy resin Substances 0.000 claims abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052737 gold Inorganic materials 0.000 claims abstract description 4
- 239000010931 gold Substances 0.000 claims abstract description 4
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 4
- 238000004806 packaging method and process Methods 0.000 claims description 33
- 238000012856 packing Methods 0.000 claims description 14
- 239000002002 slurry Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 239000011135 tin Substances 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 6
- 239000006071 cream Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 3
- 239000002003 electrode paste Substances 0.000 claims description 2
- 238000004070 electrodeposition Methods 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000007747 plating Methods 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract 2
- 238000000576 coating method Methods 0.000 abstract 2
- 239000011889 copper foil Substances 0.000 abstract 2
- 239000003795 chemical substances by application Substances 0.000 abstract 1
- 238000005520 cutting process Methods 0.000 abstract 1
- 238000004513 sizing Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000007731 hot pressing Methods 0.000 description 3
- 239000003550 marker Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 229920002472 Starch Polymers 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011469 building brick Substances 0.000 description 1
- 210000002421 cell wall Anatomy 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- ALKZAGKDWUSJED-UHFFFAOYSA-N dinuclear copper ion Chemical compound [Cu].[Cu] ALKZAGKDWUSJED-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005485 electric heating Methods 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- -1 octenyl succinate anhydride Chemical class 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000008107 starch Substances 0.000 description 1
- 235000019698 starch Nutrition 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4875—Connection or disconnection of other leads to or from bases or plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310529964.0A CN103579030B (zh) | 2013-10-30 | 2013-10-30 | 一种新型芯片封装方法及芯片封装结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310529964.0A CN103579030B (zh) | 2013-10-30 | 2013-10-30 | 一种新型芯片封装方法及芯片封装结构 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103579030A true CN103579030A (zh) | 2014-02-12 |
CN103579030B CN103579030B (zh) | 2016-01-13 |
Family
ID=50050529
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310529964.0A Active CN103579030B (zh) | 2013-10-30 | 2013-10-30 | 一种新型芯片封装方法及芯片封装结构 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN103579030B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106373897A (zh) * | 2015-07-23 | 2017-02-01 | 英飞凌科技股份有限公司 | 将半导体芯片定位在载体上并使其与载体连接的方法 |
CN107305875A (zh) * | 2016-04-19 | 2017-10-31 | 现代摩比斯株式会社 | 双向半导体封装件 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58139456A (ja) * | 1982-02-15 | 1983-08-18 | Hitachi Ltd | リ−ドフレ−ム |
US20030113947A1 (en) * | 2001-12-19 | 2003-06-19 | Vandentop Gilroy J. | Electrical/optical integration scheme using direct copper bonding |
US20050161682A1 (en) * | 2003-05-05 | 2005-07-28 | Joseph Mazzochette | Light emitting diodes packaged for high temperature operation |
US20090042336A1 (en) * | 2007-08-06 | 2009-02-12 | Kyung-Wook Paik | Fabrication method of an organic substrate having embedded active-chips |
CN101494175A (zh) * | 2008-01-22 | 2009-07-29 | 北京机械工业自动化研究所 | 一种三层立体功率封装方法及其结构 |
CN102789996A (zh) * | 2012-08-01 | 2012-11-21 | 卓盈微电子(昆山)有限公司 | 适用于倒装芯片嵌入线路板的封装工艺 |
-
2013
- 2013-10-30 CN CN201310529964.0A patent/CN103579030B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58139456A (ja) * | 1982-02-15 | 1983-08-18 | Hitachi Ltd | リ−ドフレ−ム |
US20030113947A1 (en) * | 2001-12-19 | 2003-06-19 | Vandentop Gilroy J. | Electrical/optical integration scheme using direct copper bonding |
US20050161682A1 (en) * | 2003-05-05 | 2005-07-28 | Joseph Mazzochette | Light emitting diodes packaged for high temperature operation |
US20090042336A1 (en) * | 2007-08-06 | 2009-02-12 | Kyung-Wook Paik | Fabrication method of an organic substrate having embedded active-chips |
CN101494175A (zh) * | 2008-01-22 | 2009-07-29 | 北京机械工业自动化研究所 | 一种三层立体功率封装方法及其结构 |
CN102789996A (zh) * | 2012-08-01 | 2012-11-21 | 卓盈微电子(昆山)有限公司 | 适用于倒装芯片嵌入线路板的封装工艺 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106373897A (zh) * | 2015-07-23 | 2017-02-01 | 英飞凌科技股份有限公司 | 将半导体芯片定位在载体上并使其与载体连接的方法 |
CN107305875A (zh) * | 2016-04-19 | 2017-10-31 | 现代摩比斯株式会社 | 双向半导体封装件 |
CN107305875B (zh) * | 2016-04-19 | 2019-11-05 | 现代摩比斯株式会社 | 双向半导体封装件 |
Also Published As
Publication number | Publication date |
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CN103579030B (zh) | 2016-01-13 |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A New Chip Packaging Method and Chip Packaging Structure Effective date of registration: 20221214 Granted publication date: 20160113 Pledgee: CITIC Bank Limited by Share Ltd. Shenzhen branch Pledgor: SHENZHEN ZHIJIN ELECTRONICS Co.,Ltd. Registration number: Y2022980027461 |
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PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20240102 Granted publication date: 20160113 Pledgee: CITIC Bank Limited by Share Ltd. Shenzhen branch Pledgor: SHENZHEN ZHIJIN ELECTRONICS Co.,Ltd. Registration number: Y2022980027461 |
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PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A New Chip Packaging Method and Chip Packaging Structure Granted publication date: 20160113 Pledgee: CITIC Bank Limited by Share Ltd. Shenzhen branch Pledgor: SHENZHEN ZHIJIN ELECTRONICS Co.,Ltd. Registration number: Y2024980000367 |