CN103576073A - System and method for testing functions of chips - Google Patents
System and method for testing functions of chips Download PDFInfo
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- CN103576073A CN103576073A CN201210265240.5A CN201210265240A CN103576073A CN 103576073 A CN103576073 A CN 103576073A CN 201210265240 A CN201210265240 A CN 201210265240A CN 103576073 A CN103576073 A CN 103576073A
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Abstract
The invention provides a system and method for testing functions of chips. The system and method for testing the functions of the chip is mainly used for completing various testing tasks carried out before the mass production of the chips to ensure the effect that the original designed functions of the chips meet requirements. The system comprises a hardware testing platform and a software architecture process. The hardware testing platform mainly provides a hardware testing environment for the whole testing system and comprises a main circuit system board with a system main controller and a carrier circuit system board where the chips to be tested located. According to the software architecture process, a software process mechanism is mainly proposed to control the normal execution of all the tested cases on the hardware testing platform.
Description
Technical field
The present invention proposes a kind of system and method for test chip function, can complete the functional test before listing to chip.
Background technology
In modulus mixture control design of integrated circuit and after producing, need to test this chip, to confirm whether this chip functions and performance parameter meet initial designing requirement, the foundation whether test result can carry out volume production or correcting as this chip.The present invention proposes a kind of test macro for this digital-to-analogue mixture control chip.The hardware platform of this test macro comprises the main circuit system plate with test macro master controller, the bearer circuit system board of tested chip, and the bearer circuit plate of tested chip is for to design and produce for specific tested chip.Simultaneously, for this hardware platform, proposed a kind of interactively software flow and method, guaranteed that each test example can normally carry out.
Summary of the invention
Patented claim of the present invention relates to a kind of system of test chip function, and this system comprises computing machine, main circuit system plate and the bearing system plate of chip under test is housed, wherein,
Main circuit system plate comprises: master controller chip, realize the needed various digital signal processing functions of test macro; Analog interface, for being connected with the analog interface of described bearing system plate, realizes data communication; Digital interface, for being connected with the digital interface of described bearing system plate, realizes data communication; Digital analog converter, for being converted to simulating signal from the digital signal of master controller chip output, exports to the analog module of the tested chip on bearing system plate and processes by analog interface; Analog-digital converter, for the simulating signal of the analog module output from tested chip internal is converted to digital signal, inputs to master controller chip and carries out data processing; With the interface of computer communication, so that computing machine and master controller chip swap data and communication;
Bearing system plate comprises: chip under test; Analog interface and digital interface, for connecting with analog interface and the digital interface of described main circuit system plate respectively, realize data communication, thereby carry out the test of chip under test; With the interface of computer communication, so as computing machine can with tested chip swap data and communication, to tested chip, download test procedure.
In addition, a kind of method of utilizing this system testing chip is also asked for protection in patented claim of the present invention, comprising:
1) software program corresponding to main circuit system plate and bearing system plate is loaded;
2) two block system plates are carried out to synchronous operation;
3) with after EOS, by main circuit system plate, to circuit-under-test system board, send relevant order, software systems on system under test (SUT) plate receive after this order, its order is carried out to dissection process, and the software test example that the content choice parsing according to it is preset on system under test (SUT) plate is in advance tested to system.
Accompanying drawing explanation
The general frame of the system of accompanying drawing 1 test chip function;
The hardware platform of the system of accompanying drawing 2 test chip functions build composition;
The front view (FV) of accompanying drawing 3 main circuit system plate member;
The back view of accompanying drawing 4 main circuit system plate member;
The front view (FV) of the bearer circuit board components of accompanying drawing 5 tested chips;
The back view of the bearer circuit board components of accompanying drawing 6 tested chips;
The annexation figure of accompanying drawing 7 test macros;
Accompanying drawing 8 software overview flow charts;
The particular flow sheet of accompanying drawing 9 synchronizing processes;
The process flow diagram of accompanying drawing 10 test case implementations
Embodiment
The present invention is mainly the function according to chip under test, makes the bearer circuit system board that meets chip under test test request, is then connected with main circuit system plate.By the software test example set of having selected in advance, chip under test to be tested. this system comprises hardware platform system and software system.By software and hardware system, work in coordination to reach the object of chip under test being carried out to functional test.The general frame of this system and method as shown in Figure 1.
This invention relates to two block system test boards: one is main circuit system plate, and another piece is the bearing system plate that chip under test is housed.The device comprising in main circuit system plate: master controller chip (large capacity fpga chip), permanent memory, DAC, ADC, SDRAM, CF card interface, power management, UART interface, USB interface, jtag interface, digital and analog interface.Master controller chip is large capacity fpga chip, why make such selection, be because be the most flexibly for whole system like this, can carry out software programming by hardware description language, realize the needed various digital signal processing functions of test macro; Permanent memory is that test macro master controller chip (large capacity fpga chip) provides jumbo outside permanent storage space, the test data of using for memory test system and test result data and related software code; DAC is digital analog converter, for being converted to simulating signal from the digital signal of master controller chip output, exports to the analog module of tested chip and processes; ADC is analog-digital converter, for the simulating signal of the analog module output from tested chip internal is converted to digital signal, inputs to master controller chip and carries out data processing; SDRAM high-speed read-write storer, is used to master controller chip that the exterior read-write storer of High rate and large capacity is provided, ephemeral data during storage system operation; CF card interface is used for connecting CF card memory, to hardware description language is downloaded in master controller chip; Power management module, for changing the power supply of outside access, provides required accurate DC voltage to master controller chip.UART, USB are used for being connected computing machine with jtag interface, so as computing machine can with master controller chip swap data and communication.Digital and analog interface is connected with the digital and analog interface of circuit-under-test system board, for realizing the data communication between two boards, thereby carries out the test to chip under test.
Can utilize this system board, the hardware description language program that is stored in advance CF card the inside is downloaded in jumbo fpga chip.After loading, can utilize PC that debugging software program is loaded in permanent memory, then PC end can detect by UART, USB or JTAG the running status of current system.
The device comprising in bearer circuit system board: chip under test, storer, UART interface, USB interface, jtag interface, digital and analog interface.Storer is not use while there is no storer in chip under test inside, is mainly storage testing software code.UART, USB are used for being connected computing machine with jtag interface, so that computing machine can with master controller chip swap data and communication, PC can download software test program to chip under test by any one of this three kinds of interfaces, and can debug and monitor the state of current plank.Digital and analog interface is corresponding connected with the digital and analog interface of main circuit system plate, for realizing the data communication between two boards, thereby carries out the test to chip under test.
If the present invention will complete chip checking work, the co-ordination of hardware and software is vital.Below just introduce in detail building details and coordinating the software flow of hardware normal operation of hardware platform
Building of 1 hardware platform
As shown in Figure 2, hardware platform system is comprised of two large parts, and parts 10 are the main circuit system plates with system master device processed, and parts 20 are the bearer circuit system boards that are mounted with tested chip.Parts 20 connect with digital interface plug-in unit 101 and analog interface plug-in unit 102 on corresponding parts 10 by digital interface plug-in unit 201 and analog interface plug-in unit 202, realize and the exchanges data of parts 10.Parts 10 support whole test macro by 4 copper post parts (109).
As shown in Figure 3, the front of the main circuit system plate member 10 of whole test macro is comprised of interface unit 101 and 102, master controller chip part 103, analog-digital converter parts 104, digital analog converter parts 105, power management module parts 106, SDRAM high-speed read-write memory member 107 and permanent memory parts 108.
Test macro master controller parts 103 carry out exchanges data or communication by digital interface parts 101 and analog interface parts 102 with tested chip part 203.Analog-digital converter parts 104, for the simulating signal of the analog module output from tested chip part 203 inside is converted to digital signal, input to master controller chip part 103 and carry out data processing.Digital analog converter parts 105, for being converted to simulating signal from the digital signal of master controller chip part 103 outputs, are exported to the analog module of tested chip part 203 and are processed.SDRAM high-speed read-write memory member 107 is used to master controller chip part 103 that the exterior read-write storer of High rate and large capacity is provided, ephemeral data during storage system operation.Permanent memory parts 108 provide jumbo outside permanent storage space, the test data of using for memory test system and test result data for test macro master controller chip part 103.Power management module parts 106, for changing the power supply of outside access, provide required accurate DC voltage to master controller chip part 103.
As shown in Figure 4, the back side of main circuit system plate member 10 forms by supporting copper post parts 109, usb interface module parts 110, UART interface module parts 111, jtag interface modular unit 113 and CF card interface module parts 112.Usb interface module parts 110, jtag interface modular unit 113 and UART interface module parts 111 are for connecting computing machine, so as computing machine can with master controller chip part 103 swap datas and communication.CF card interface module parts 112 are for connecting CF card memory, so that the program code that user writes can download in master controller chip part 103.
As shown in Figure 5, the front of the bearer circuit board components 20 of tested chip is comprised of tested chip part 203, UART interface module parts 204, jtag interface modular unit 207, usb interface module parts 205 and power management module parts 206.UART interface module parts 204 with usb interface module parts 205 for being connected PC or other equipment with UART/USB serial line interface, so that PC or other main equipments can carry out communication with tested chip part 203.Power management module parts 206, for changing the power supply of outside access, provide required accurate DC voltage to tested chip part 203.
As shown in Figure 6, the back side of the bearer circuit board components 20 of tested chip is comprised of digital interface parts 201 and analog interface parts 202.Tested chip part 203 carries out exchanges data or communication by digital interface parts 201 and analog interface parts 202 with test macro master controller parts 103.Test macro annexation as shown in Figure 7.
2 software flows
Hardware environment as above build complete after, will test the function of chip under test.Test has mainly communicated by main circuit system plate and circuit-under-test system board, and whole software flow as shown in Figure 8.First to the software program corresponding to main circuit system plate and circuit-under-test system board be loaded up by the jtag interface on two plates.Because the test of carrying out is mainly that software collaboration work by operating on main circuit system plate and circuit-under-test system board completes, therefore, after having loaded software program to two circuit boards, before testing, to carry out synchronous operation.After EOS, by main circuit system plate, to circuit-under-test system board, send relevant order, software systems on system under test (SUT) plate receive after this order, its order is carried out to dissection process, and the software test example that the content choice parsing according to it is preset on system under test (SUT) plate is in advance tested to system.
Introduce in detail testing process below:
1) software synchronization
Because this Design of Test System to two is test board piece independently, and guarantee that the prerequisite of this system normal operation is exactly that two system boards will act in agreement concerning a certain test case, co-ordination, can carry out according to demand dependence test like this.And will reach the method that two block system plates act in agreement, carry out exactly software synchronization.Below according to just having proposed to carry out synchronous specific implementation, as shown in Figure 9:
From the digital interface of two circuit boards, select Interface for digital communication (UART, I2C or SPI), by its corresponding being connected, then by communication interface, sending specific character and carry out synchronous operation.The UART interface of take carries out associated description (process of SPI and I2C is also identical therewith) as example: start circuit-under-test system board end and monitoring the data message on UART always, see whether be start character string.When the program of active circuits system board end completes after the arranging of hardware environment, when active circuits system board end can carry out dependence test, by UART interface, to circuit-under-test system board one end, send start character string, represent to be ready to, then wait for and receive the ack character string that circuit-under-test system board one end sends by UART interface.When circuit-under-test system board one end detects character string and is start, represent to have known that active circuits plate one end is ready to, the program of circuit-under-test system board one end starts its hardware environment to arrange.After accomplishing the setting up, by UART, to active circuits system board, send ack character string, represent that circuit-under-test system board is ready to.Active circuits system board is received after ack, represents to have known that circuit-under-test system board one end is ready to, at this moment same EOS.
2) transmission and the parsing of order
For completing two synchronous equipment, the most basic communication mechanism has been set up.What next step will be done so will select appropriate test case to test chip under test according to test request exactly.For this situation, we can be in advance all test case programs that chip under test is tested be all burnt in the storer of circuit-under-test system board one side (if chip under test inside comprises storer, burned chip under test storer; If the inner no memory of chip under test, in the chip external memory on burned plate).Then master controller is chosen and is called which test case chip under test is carried out to corresponding test by sending the good character string command of bilateral agreement.Give one example to illustrate detailed process and the method for utilizing communication interface UART (I2C and SPI process are also identical therewith) to realize this command analysis below, detailed process as shown in Figure 10.Test the function FUNC of chip under test, and the command string that we are this function FUNC definition is cmd.After synchronously completing, circuit-under-test system end program is waited for the order input of UART immediately.When active circuits system board end sends after cmd to circuit-under-test system end by UART, active circuits system board end starts to wait for test case execution end signal---character string end.When circuit-under-test system end program detects the character string transmitting on UART interface and is cmd, just program is jumped to the entrance of the test case program of corresponding test FUNC function.With regard to starting to carry out the test case of FUNC function, chip is tested subsequently.After test case program is carried out and finished, send test case carry out end signal---character string end to main circuit system plate end, main circuit system plate one end captures test case and carries out end signal---after character string end, represent that the test of this function FUNC finishes.
Be the process that a test case is carried out above, if want to carry out the automatic test of a plurality of test cases, also can utilize this system and flow process.Only need to add the process of a plurality of test cases both can realize the automatic test of many test cases at main circuit system program in machine code.
Claims (8)
1. a system for test chip function, comprises computing machine, main circuit system plate and the bearing system plate of chip under test is housed, wherein,
Main circuit system plate comprises: master controller chip, realize the needed various digital signal processing functions of test macro; Analog interface, for being connected with the analog interface of described bearing system plate, realizes data communication; Digital interface, for being connected with the digital interface of described bearing system plate, realizes data communication; Digital analog converter, for being converted to simulating signal from the digital signal of master controller chip output, exports to the analog module of the tested chip on bearing system plate and processes by analog interface; Analog-digital converter, for the simulating signal of the analog module output from tested chip internal is converted to digital signal, inputs to master controller chip and carries out data processing; With the interface of computer communication, so that computing machine and master controller chip swap data and communication;
Bearing system plate comprises: chip under test; Analog interface and digital interface, for connecting with analog interface and the digital interface of described main circuit system plate respectively, realize data communication, thereby carry out the test of chip under test; With the interface of computer communication, so as computing machine can with tested chip swap data and communication, to tested chip, download test procedure.
2. the system as claimed in claim 1, it is characterized in that described main circuit system plate arranges by described analog interface and digital interface on surface thereon, described bearing system plate is provided with described analog interface and digital interface at its lower surface, described bearing system plate is connected with digital interface by described analog interface with main circuit system plate, thereby the mode that is stacked on top of one another configures.
3. the system as claimed in claim 1, it is characterized in that described main circuit system plate also comprises: permanent memory, for test macro master controller chip provides jumbo outside permanent storage space, the test data that memory test system is used and test result data and related software code; SDRAM high-speed read-write storer, is used to master controller chip that the exterior read-write storer of High rate and large capacity is provided, ephemeral data during storage system operation; CF card interface, for connecting CF card memory, to hardware description language is downloaded in master controller chip.
4. the system as claimed in claim 1, is characterized in that described main circuit system plate also comprises power management module, for changing the power supply of outside access, required accurate DC voltage is provided to master controller chip.
5. the system as claimed in claim 1, is characterized in that described bearer circuit system board comprises storer, for when tested chip internal does not have storer, and storage testing software code.
6. adopt the method for system testing chip functions claimed in claim 1, comprising:
1) software program corresponding to main circuit system plate and bearing system plate is loaded;
2) two block system plates are carried out to synchronous operation;
3) with after EOS, by main circuit system plate, to circuit-under-test system board, send relevant order, software systems on system under test (SUT) plate receive after this order, its order is carried out to dissection process, and the software test example that the content choice parsing according to it is preset on system under test (SUT) plate is in advance tested to system.
7. method as claimed in claim 6, the step 2 of wherein two block system plates being carried out to synchronous operation) comprising:
Described active circuits system board end is sent and starts character string to bearing system plate by digital interface, then waits for that one section of bearing system plate sends it back the character string of answering;
Bearing system plate is after this startup character string being detected, and the program of bearing system plate one end is configured its hardware environment;
Bearing system plate completes after configuration, by digital interface, to active circuits system board, is sent it back and answers character string.
8. method as claimed in claim 6, wherein step 3) comprising:
Active circuits system board sends command string to bearing system plate one end by digital interface;
When the program of bearing system plate one end detects this command string, program is jumped to the entrance of corresponding test case program and start and carry out;
After test case program is carried out and finished, bearing system plate sends test execution example end signal to main circuit system plate end;
This end signal is caught in active circuits system board one end, and finishes test.
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| CN201210265240.5A CN103576073A (en) | 2012-07-30 | 2012-07-30 | System and method for testing functions of chips |
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| CN105227390A (en) * | 2014-06-27 | 2016-01-06 | 中兴通讯股份有限公司 | The method of quick test CPU forwarding performance and device |
| CN105975370A (en) * | 2015-07-23 | 2016-09-28 | 乐视致新电子科技（天津）有限公司 | Method and device for testing |
| CN106021056A (en) * | 2016-05-31 | 2016-10-12 | 四川九洲空管科技有限责任公司 | Automatic testing system and method for Arinc429 communication chip |
| CN106059582A (en) * | 2016-04-28 | 2016-10-26 | 芯海科技（深圳）股份有限公司 | System and method for testing digital-analog mixed signal chip |
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| CN111830390A (en) * | 2019-04-18 | 2020-10-27 | 中科寒武纪科技股份有限公司 | Test method and related product |
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| CN110275805A (en) * | 2019-06-13 | 2019-09-24 | 上海琪埔维半导体有限公司 | A kind of full-automatic test system for MCU chip |
| CN110888046A (en) * | 2019-11-25 | 2020-03-17 | 展讯通信（上海）有限公司 | System-on-chip and test method, storage medium and terminal thereof |
| CN116593874A (en) * | 2023-07-17 | 2023-08-15 | 宁波吉品科技有限公司 | Chip testing method |
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