CN103560146A - Epitaxy structure for manufacturing GaN hetero-junction filed-effect transistor and growing method thereof - Google Patents
Epitaxy structure for manufacturing GaN hetero-junction filed-effect transistor and growing method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000000407 epitaxy Methods 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000005036 potential barrier Methods 0.000 claims description 16
- 238000002360 preparation method Methods 0.000 claims description 16
- 229910002704 AlGaN Inorganic materials 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 230000005012 migration Effects 0.000 abstract description 3
- 238000013508 migration Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000004888 barrier function Effects 0.000 abstract description 2
- 238000003780 insertion Methods 0.000 abstract 4
- 230000037431 insertion Effects 0.000 abstract 4
- 230000003139 buffering effect Effects 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 7
- 230000005533 two-dimensional electron gas Effects 0.000 description 6
- 230000003446 memory effect Effects 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 238000010923 batch production Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001447 compensatory effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/205—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
- H01L21/2056—Epitaxial deposition of AIIIBV compounds
Abstract
The invention relates to the field of epitaxy growth of semiconductor materials and discloses an epitaxy structure for manufacturing a GaN hetero-junction filed-effect transistor and a growing method of the epitaxy structure. The epitaxy structure sequentially comprises a substrate, a stress buffering layer, a high-resistance GaN epitaxy layer, a novel insertion layer, a non-doped GaN channel layer and a hetero-junction barrier layer from bottom to top. The novel insertion layer comprises a P-type doping GaN insertion layer and an N-type doping GaN insetion layer. According to the epitaxy structure, a doping layer composed of a layer of P-type doping GaN and a layer of N-type doping GaN serves as the novel insertion layer. The novel epitaxy structure for manufacturing the GaN hetero-junction filed-effect transistor which is high in migration ratio, low in OFF leakage current and ultrahigh in switch ratio is realized.
Description
technical field
The present invention relates to epitaxial growth of semiconductor material growth field, more specifically, relate to a kind of epitaxial structure for the preparation of GaN HFET and growing method.
Background technology
The third generation semiconductor material with wide forbidden band that the GaN of take is representative has the good material property features such as broad stopband, high breakdown field strength, high saturated electron drift velocity, high heat conductance, heterogeneous interface two-dimensional electron gas height, than Si material, GaN is applicable to making the electronic device of high-power high power capacity, high switching speed and high frequency more.Compare with traditional Si device, GaN device can carry higher power density, has higher energy conversion efficiency, can make the volume and weight of whole system reduce, thereby reduce system cost.
The high-frequency power device that utilizes AlGaN/GaN heterojunction to prepare is the technical scheme being widely adopted at present.Simultaneously semi-insulating GaN epitaxial loayer (high resistant GaN epitaxial loayer) is the key of preparation AlGaN/GaN heterojunction HFET, because this semi-insulating GaN epitaxial loayer is being played the part of the key player that good raceway groove turn-off characteristic (voltage endurance) was led and guaranteed to parallel electricity between reduction device grids and drain electrode.
At present, the high resistant GaN epitaxial loayer of involuntary doping has been passed and has introduced the method realization that edge dislocation is carried out the remaining donor impurity of background N-shaped in compensative material.But due to the poor restriction of raceway groove place two-dimensional electron gas, the HFET device of preparing with the epitaxial loayer that the method realizes is running into bottleneck further reducing aspect leakage current, thereby may cause device short-channel effect under high-frequency work condition obvious.
In order to improve above-mentioned shortcoming, the technical scheme of the employing AlGaN/GaN/AlGaN double-heterostructure that the people such as Y.K.SU of Taiwan success university propose reaches the object of restriction raceway groove two-dimensional electron gas, has realized channel mobility 1180cm
2the HFET of/V.s; (referring to document Y. K. Su, S. J. Chang, T. M. Kuan, C. H. Ko, J. B. Webb, W. H. Lan, Y. T. Cherng, and S. C. Chen, Nitride-based HFETs with carrier confinement layers, Materials Science and Engineering:B 110 (2), 172 (2004) .).The people such as Shoou-Jinn Chang of Taiwan success university realize the target of constraint channel current by the technical scheme of employing Mg heavy doping GaN resilient coating, thereby have obtained 6mA/mm source electrode-drain leakage.(referring to document Shoou-Jinn Chang, Sun-Chin Wei, Yan-Kuin Su, Chun-Hsing Liu, Shih-Chih Chen, Uang-HeayLiaw, Tzong-Yow Tsai, and Tzu-Hsuan Hsu, AlGaN/GaN Modulation-Doped Field-Effect Transistors with An Mg-doped Carrier Confinement Layer, Japanese Journal of Applied Physics 42,3316 (2003)).But double-heterostructure and Mg heavy doping GaN resilient coating all can cause the significantly decline of whole epitaxial structure crystal mass, thereby cause the degeneration of crystal mass of the two-dimensional electron gas channel layer of subsequent growth.In addition, the Mg heavy doping GaN resilient coating of larger thickness can cause that serious Mg atom memory effect is (referring to document Y Ohba and A Hatano, A study on strong memory effects for Mg doping in GaN metalorganic chemical vapor deposition, Journal of crystal growth 145 (1), 214 (1994) .), the output characteristic of the HFET device of this follow-up preparation of impact accordingly is also unfavorable for epitaxially grown repeatability simultaneously very much.
Summary of the invention
In order to overcome the deficiencies in the prior art, first the present invention proposes that a kind of technique is simple, the epitaxial structure for the preparation of GaN HFET that stability is higher, reliability is stronger and that can repeat use.
To achieve these goals, technical scheme is as follows:
For the preparation of an epitaxial structure for GaN HFET, comprise successively from the bottom to top substrate, stress-buffer layer, high resistant GaN epitaxial loayer, P type Doped GaN insert layer, N-type Doped GaN insert layer, non-Doped GaN channel layer and potential barrier of heterogenous junction layer;
Described P type Doped GaN insert layer thickness is 1 ~ 50nm; N-type Doped GaN insert layer thickness is 1 ~ 50nm.
Preferably, described substrate is any in Si substrate, Sapphire Substrate, silicon carbide substrates.
Preferably, described stress-buffer layer is any or the combination of AlN, AlGaN, GaN; Stress buffer layer thickness is 100nm ~ 10 μ m.
Preferably, described high resistant GaN epitaxy layer thickness is 100nm ~ 5 μ m.
Preferably, described P type doped layer doped with Mg, Be or Zn; Described N-type doping Si or Ge.Wherein Mg gently mixes thin layer and can effectively weaken memory effect, and Si gently mixes thin layer can effectively be improved epitaxial growth and cross a layer Atom surface migration, and improves raceway groove crystal mass.
Preferably, described non-Doped GaN channel layer thickness is 5 ~ 200nm.
Preferably, described potential barrier of heterogenous junction layer is a kind of or any several combination in AlGaN, AlInN, AlInGaN, AlN material, and this potential barrier of heterogenous junction layer is non-doped layer or N-shaped doped layer, thickness 10 ~ 30 nm of potential barrier of heterogenous junction layer.
The present invention also proposes a kind of growing method of above-mentioned epitaxial structure, can be effectively improving back of the body potential barrier, reduce OFF leakage current, effectively improve crystal mass when realizing high on-off ratio, reduce defect concentration, reduce heterojunction surface roughness, increase two-dimensional electron gas mobility in heterojunction.
To achieve these goals, its technical scheme is:
A growing method for epitaxial structure, comprises the following steps:
1) at Grown stress-buffer layer;
2) one deck high resistant GaN epitaxial loayer of growing on stress-buffer layer;
3) one deck P type Doped GaN insert layer of growing on high resistant GaN epitaxial loayer, P type Doped GaN insert layer thickness is 1 ~ 50nm;
4) one deck N-type Doped GaN insert layer of growing in P type Doped GaN insert layer, N-type Doped GaN insert layer thickness is 1 ~ 50nm;
5) the non-Doped GaN channel layer of one deck of growing in N-type Doped GaN insert layer;
6) one deck potential barrier of heterogenous junction layer of growing on non-Doped GaN channel layer.
Preferably, the growing method of described stress-buffer layer, high resistant GaN epitaxial loayer, P type Doped GaN layer, N-type Doped GaN layer, non-Doped GaN channel layer and potential barrier of heterogenous junction layer comprises it being Metalorganic Chemical Vapor Deposition or molecular beam epitaxy.
Preferably, described P type doped layer doped with Mg, Be or Zn; Described N-type doping doping Si or Ge.Wherein Mg gently mixes thin layer and can effectively weaken memory effect, and Si gently mixes thin layer can effectively be improved epitaxial growth and cross a layer Atom surface migration, and improves raceway groove crystal mass.
Compared with prior art, beneficial effect of the present invention is: epitaxial structure is simple, can be effectively improving back of the body potential barrier, reduce OFF leakage current, effectively improve crystal mass when realizing high on-off ratio, reduce defect concentration, reduce heterojunction surface roughness, increase two-dimensional electron gas mobility in heterojunction.Outer layer growth method is simple simultaneously, and repeatability is good, easily batch production.
Accompanying drawing explanation
What Fig. 1-6 were the embodiment of the present invention 1 prepares epitaxial structure process schematic representation.
Fig. 7 is the on-off ratio performance plot that utilizes the field-effect transistor that shown in embodiment 1 prepared by epitaxial structure.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described further.
Be illustrated in figure 6 the epitaxial structure schematic diagram of the present embodiment, comprise substrate 1, stress-buffer layer 2, high resistant GaN epitaxial loayer 3, P type Doped GaN insert layer 4, N-type Doped GaN insert layer 5, involuntary Doped GaN channel layer 6 and the heterojunction channel barrier layer 7 on it.The growing method adopting in this programme is that the growth of one of molecular beam epitaxy or two kinds of methods of Metalorganic Chemical Vapor Deposition forms.
The above-mentioned epitaxial structure manufacture method for the preparation of GaN HFET, as shown in Fig. 1-6, comprises the following steps:
(1) utilize molecular beam epitaxy or the Metalorganic Chemical Vapor Deposition one deck stress-buffer layer 2 of growing on substrate 1, between thickness 100nm ~ 10 micron, as shown in Figure 1;
(2), on stress-buffer layer 2, by the method growth one deck high resistant GaN epitaxial loayer with identical in step (1), this high resistant GaN epitaxy layer thickness is 100nm ~ 5 μ m, as shown in Figure 2;
(3) utilize and method identical in step (1), continue to grow one deck P type Doped GaN insert layer on high resistant GaN epitaxial loayer; This N-type Doped GaN insert layer thickness is 1nm ~ 50nm, as shown in Figure 3;
(4) utilize and method identical in step (1), continue one deck N-type Doped GaN insert layer of growing in P type doping insert layer; This N-type Doped GaN insert layer thickness is 1nm ~ 50nm, as shown in Figure 4;
(5) utilize and method identical in step (1), continue to grow the involuntary Doped GaN channel layer of one deck in N-type Doped GaN insert layer; This involuntary Doped GaN channel layer thickness is 10nm ~ 200nm, as shown in Figure 5;
(6) utilize and method identical in step (1), continue to grow one deck potential barrier of heterogenous junction layer on involuntary Doped GaN channel layer; This potential barrier of heterogenous junction layer by layer thickness is 10nm ~ 30nm, as shown in Figure 6; So far, completed the preparation process of this epitaxial structure.Fig. 6 is the epitaxial structure schematic diagram for the preparation of GaN HFET of embodiment 1.
(7) Fig. 7 is the on-off ratio performance plot that utilizes the field-effect transistor that shown in embodiment 1 prepared by epitaxial structure.Wherein black dotted lines is the switching characteristic of the HFET device prepared of traditional epitaxial structure, and red solid line is to utilize the switching characteristic of the HFET that shown in embodiment 1 prepared by epitaxial structure; Adopt the on-off ratio of traditional epitaxial structure to only have 10
5magnitude, and the devices switch ratio that adopts the epitaxial structure shown in embodiment 1 to make can reach 10
9magnitude.
Claims (10)
1. the epitaxial structure for the preparation of GaN HFET, it is characterized in that, comprise successively from the bottom to top substrate, stress-buffer layer, high resistant GaN epitaxial loayer, P type Doped GaN insert layer, N-type Doped GaN insert layer, non-Doped GaN channel layer and potential barrier of heterogenous junction layer;
Described P type Doped GaN insert layer thickness is 1 ~ 50nm; N-type Doped GaN insert layer thickness is 1 ~ 50nm.
2. the epitaxial structure for the preparation of GaN HFET according to claim 1, is characterized in that, described substrate is any in Si substrate, Sapphire Substrate, silicon carbide substrates.
3. the epitaxial structure for the preparation of GaN HFET according to claim 1, is characterized in that, described stress-buffer layer is any or the combination of AlN, AlGaN, GaN; Stress buffer layer thickness is 100nm ~ 10 μ m.
4. the epitaxial structure for the preparation of GaN HFET according to claim 1, is characterized in that, described high resistant GaN epitaxy layer thickness is 100nm ~ 5 μ m.
5. according to the epitaxial structure for the preparation of GaN HFET described in claim 1 to 4 any one, it is characterized in that described P type doped layer doped with Mg, Be or Zn; Described N-type doping Si or Ge.
6. the epitaxial structure for the preparation of GaN HFET according to claim 1, is characterized in that, described non-Doped GaN channel layer thickness is 5 ~ 200nm.
7. the epitaxial structure for the preparation of GaN HFET according to claim 1, it is characterized in that, described potential barrier of heterogenous junction layer is a kind of or any several combination in AlGaN, AlInN, AlInGaN, AlN material, this potential barrier of heterogenous junction layer is non-doped layer or N-shaped doped layer, thickness 10 ~ 30 nm of potential barrier of heterogenous junction layer.
8. a growing method for epitaxial structure described in claim 1 to 7 any one, is characterized in that, comprises the following steps:
1) at Grown stress-buffer layer;
2) one deck high resistant GaN epitaxial loayer of growing on stress-buffer layer;
3) one deck P type Doped GaN insert layer of growing on high resistant GaN epitaxial loayer, P type Doped GaN insert layer thickness is 1 ~ 50nm;
4) one deck N-type Doped GaN insert layer of growing in P type Doped GaN insert layer, N-type Doped GaN insert layer thickness is 1 ~ 50nm;
5) the non-Doped GaN channel layer of one deck of growing in N-type Doped GaN insert layer;
6) one deck potential barrier of heterogenous junction layer of growing on non-Doped GaN channel layer.
9. growing method according to claim 7, it is characterized in that, the growing method of described stress-buffer layer, high resistant GaN epitaxial loayer, P type Doped GaN layer, N-type Doped GaN layer, non-Doped GaN channel layer and potential barrier of heterogenous junction layer comprises it being Metalorganic Chemical Vapor Deposition or molecular beam epitaxy.
10. growing method according to claim 8 or claim 9, is characterized in that described P type doped layer doped with Mg, Be or Zn; Described N-type doping doping Si or Ge.
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Cited By (2)
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| CN107195709A (en) * | 2017-05-19 | 2017-09-22 | 中山大学 | A kind of III-nitride base heterojunction phototransistor |
| CN112531015A (en) * | 2020-12-02 | 2021-03-19 | 北京大学东莞光电研究院 | Low-loss gallium nitride radio-frequency material epitaxial structure and preparation method |
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Application publication date: 20140205 |