CN103531466B - A kind of preparation method of island dynamic formula single-electronic transistor - Google Patents
A kind of preparation method of island dynamic formula single-electronic transistor Download PDFInfo
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- CN103531466B CN103531466B CN201210228473.8A CN201210228473A CN103531466B CN 103531466 B CN103531466 B CN 103531466B CN 201210228473 A CN201210228473 A CN 201210228473A CN 103531466 B CN103531466 B CN 103531466B
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- 238000002360 preparation method Methods 0.000 title claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 27
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 239000000084 colloidal system Substances 0.000 claims abstract description 10
- 238000001020 plasma etching Methods 0.000 claims abstract description 9
- 238000002164 ion-beam lithography Methods 0.000 claims abstract description 5
- 230000009471 action Effects 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract 2
- 239000010931 gold Substances 0.000 claims description 30
- 238000000151 deposition Methods 0.000 claims description 23
- WYTZZXDRDKSJID-UHFFFAOYSA-N (3-aminopropyl)triethoxysilane Chemical compound CCO[Si](OCC)(OCC)CCCN WYTZZXDRDKSJID-UHFFFAOYSA-N 0.000 claims description 20
- 230000008021 deposition Effects 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 17
- 238000010894 electron beam technology Methods 0.000 claims description 11
- 239000002096 quantum dot Substances 0.000 claims description 10
- 239000002105 nanoparticle Substances 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- HEDRZPFGACZZDS-UHFFFAOYSA-N Chloroform Chemical compound ClC(Cl)Cl HEDRZPFGACZZDS-UHFFFAOYSA-N 0.000 claims description 8
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 8
- 238000004630 atomic force microscopy Methods 0.000 claims description 7
- 239000002245 particle Substances 0.000 claims description 7
- 239000000523 sample Substances 0.000 claims description 7
- 239000008346 aqueous phase Substances 0.000 claims description 6
- 238000006757 chemical reactions by type Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 5
- 238000001704 evaporation Methods 0.000 claims description 5
- 230000008020 evaporation Effects 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 238000007737 ion beam deposition Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 238000000233 ultraviolet lithography Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 10
- 238000005516 engineering process Methods 0.000 abstract description 8
- 230000005641 tunneling Effects 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 abstract description 3
- 238000005036 potential barrier Methods 0.000 description 8
- 238000011160 research Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- FDWREHZXQUYJFJ-UHFFFAOYSA-M gold monochloride Chemical compound [Cl-].[Au+] FDWREHZXQUYJFJ-UHFFFAOYSA-M 0.000 description 3
- 238000002372 labelling Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- YTPLMLYBLZKORZ-UHFFFAOYSA-N Thiophene Chemical compound C=1C=CSC=1 YTPLMLYBLZKORZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
Abstract
The invention discloses a kind of method preparing island dynamic formula single-electronic transistor, the method is with silicon chip, source electrode, drain electrode, grid, island district and coulomb island for single-electronic transistor basic structure, source electrode, drain electrode, grid are integrally disposed in the silicon dioxide substrates that silicon substrate surface is formed, etching island district in the region surrounded between source electrode, drain electrode, grid, coulomb island is assembled in Zhong Bingke island district of island district activity.Island district utilizes focused-ion-beam lithography or reactive ion etching to prepare, and coulomb island can be movable in island district under electric field action, and between electrode and coulomb island, tunneling barrier changes along with the change of electric field；Coulomb island utilizes colloid Au technology of preparing to prepare, and its size has controllability.This device shows the comprehensive effect of Flied emission and coulomb blockade the most at last.The inventive method can accurately control the size on coulomb island and the assembling location on coulomb island, has avoided the problem that barrier layer needs accurately control, has significantly reduced single-electronic transistor and prepare difficulty.
Description
Technical field
The present invention relates to nano electron device technical field, particularly to the preparation method of a kind of island dynamic formula single-electronic transistor.
Background technology
The characteristic size of the integrated circuit with MOSFET device as main flow has evolved to nanometer scale, and application is restricted, and the electronic logic device of the nano-scale that research and development are new becomes growth requirement further.In main nanometer single-electron device, single-electronic transistor receives much concern due to advantages such as small size, high sensitivity and low-power consumption.It can realize logical operations and information storage under nanoscale, is novel nano electronic device based on coulomb blockade effect and single electron tunneling effect.
The research of Single-electron phenomena is abroad carried out relatively early, nineteen fifty-one, and the Cornellis Gorter of Holland's Ka Molinangneisi laboratory reports coulomb blockage.2008, M. Manoharan et al., on the SOI material that P element is adulterated, used the technological means such as beamwriter lithography, reactive ion etching and thermal oxide graphically to obtain the single-electronic transistor of a single island structure, and device maximum operating temperature reaches 12.5 K；Ray etc. utilize undersized Au nanoparticle to be prepared for the single-electronic transistor of room temperature operation, and its technique is compatible with CMOS technology；The Ponomarenko of Univ Manchester UK etc. then use Graphene as the tunneling structure of single-electronic transistor, at room temperature obtain coulomb staircase and coulomb oscillations curve clearly.2010, S. J. Shin et al., on SOI material, used electron beam exposure, the traditional handicraft means such as reactive ion etching and thermal oxide, prepares the single-electronic transistor having dimensions less than 5 nm coulomb islands；Hidehiro Yamaguchi et al. utilizes thiophen polymer (oligothiophene pentamer) to be assembled between nano-electrode by Au quantum dot, the single-electronic transistor worked under the conditions of preparing 12 K.
Eighties of last century nineties, Single-electron phenomena is paid close attention to by domestic beginning, Semiconductor institute, Chinese Academy of Sciences builds white academician the summer and the most once pointed out that single-electronic transistor will be being preferably selected of following mass storage, and thinks that the research of Single-electron phenomena will open up one new " artificial atom physics ".Many the units such as the once associating Chinese Academy of Sciences of the seminar CAS Institute of Physics of Peking University Wu Quande academician leader, Shanghai Communications University, Nanjing University, Jilin University carry out nanoelectronics basic research, achieve a lot of original achievement.2007, Microelectronics Institute of Chinese Academy of Sciences Liu Ming professor's seminar's employing electron beam exposure and reactive ion etching technology, SOI material is prepared for a coulomb single-electronic transistor of size ~ 10, island nm.Hunan University Wang Taihong teaches seminar and has carried out extensive work in terms of micro-nano device research, also a series of single-electronic transistor research work has been carried out, they utilize the metal gate potential barrier limited formation coulomb island to quantum wire, are prepared for coulomb adjustable single-electronic transistor of island effective dimensions
But, currently existing single-electronic transistor preparation generally three key technical problems of existence: the controlled preparation on small size coulomb island；The controlled location on coulomb island assembles；The accurate control of tunneling barrier size between coulomb island and electrode.This operating temperature being related to device and the concordance of performance thereof.Wherein, the potential barrier size accurately controlled between coulomb island and electrode is particularly difficult, if potential barrier size being determined, value changes a variable range into by a certain, will be substantially reduced the preparation difficulty of device, beneficially application.
2006, O. E. Raichev took the lead in proposing Flied emission and coulomb blockade the effect deposited, and based on this effect, we have proposed the preparation scheme of island dynamic formula single-electronic transistor.
Summary of the invention
The technical problem to be solved is: breaking potential barrier size in single-electronic transistor preparation needs the difficult problem accurately controlled, and preparation potential barrier size variable island dynamic formula single-electron device, device will show the effect that field emission effect combines with coulomb blockade.
In order to achieve the above object, the technical scheme that the present invention provides is:
The preparation method of described island dynamic formula single-electronic transistor, it is with silicon chip, source electrode, drain electrode, grid, island district and coulomb island for single-electronic transistor basic structure, source electrode, drain electrode, grid are integrally disposed in the silicon dioxide substrates that silicon substrate surface is formed, the region surrounded between source electrode, drain electrode, grid etches the island district as zone of action, coulomb island, coulomb island is assembled in the district of island；Specifically include following steps:
(1) silicon chip after thermal oxidation is cleaned, makes silicon substrate surface form the silicon dioxide insulating layer as substrate, i.e. silicon dioxide substrates；
(2) by focusing on e-beam induced deposition method, or electron beam exposure and evaporation coating method etc. prepare the source electrode of nano-scale, drain and gate in silicon dioxide substrates, and can be prepared the micron order lead-in wire electrode for island dynamic formula single-electronic transistor device is transitioned into macroscopic circuit being connected with source electrode, drain electrode, grid respectively on substrate by Ultraviolet lithography or focused ion beam deposition method etc.；
(3) by focused-ion-beam lithography method or reactive ion etching method, the region etch between source electrode, drain and gate goes out the pit as island district；
(4) silicon dioxide insulating layer is formed by thermal oxide or dual-beam equipment induced deposition Deng Shidao district's inside circumference and bottom surface；
(5) prepare, by aqueous phase reducing process, the gold nano grain that particle diameter is 2～15 nm, as coulomb island；
(6) utilize electrostatic self-assembled method, assist with reaction type atomic force microscopy probe, coulomb island is assembled in the district of island.
Wherein, described silicon dioxide substrates thickness is 200～500 nm；Described source electrode, drain and gate can use electron beam exposure and vapour deposition method to prepare, and now, use Ti as metal adhesion layers, and adhesion layer thickness is 2～3 nm, use Au as deposition material, and deposition material thickness is 5～25 nm；Described source electrode, drain and gate can also use focusing e-beam induced deposition technology to prepare, and now, use Pt or W for deposition material, and deposition material thickness is 15～30 nm；Described source electrode and the spacing of drain electrode, described grid suitably can adjust according to technique and design with the size in source electrode and the spacing of drain electrode and described island district, it is preferable that described source electrode and drain electrode spacing in silicon dioxide substrates are 30 nm；Spacing on substrate is 50～500 nm to described grid with source electrode and drain electrode, and the size in described island district is 20 × 30 × 10 nm3；Described coulomb island is Au nanoparticle.
In technique scheme, the focused ion bundle used/e-beam induced deposition, electron beam exposure, ultraviolet photolithographic, evaporation, thermal oxide etc. are mature technology well known in the art.Make equipment required in aforementioned manners the most commercially available: double-beam system can use the Helios of U.S. FEI
NanoLab 600i；Electron-beam exposure system can use the JBX5500ZA electron beam exposure apparatus of NEC；Ultraviolet lithographic system can use the SUSS MA/BA6 litho machine of SUSS MicroTec company of Germany；Electron beam evaporation deposition system can use the high vacuum evaporation coating system ei-5z of ULVAC company of Japan.
Below in conjunction with the design principle of the present invention and beneficial effect, the present invention will be further described:
In the present invention, silicon substrate surface is made to form the silicon dioxide insulating layer as substrate by thermal oxidation silicon chip, source electrode, drain electrode, grid are integrally disposed in silicon dioxide substrates, and region etch Chu Dao district Bing Shidao district inside circumference and bottom surface between source electrode, drain and gate form silicon dioxide insulating layer；Use ripe colloid Au technology of preparing, i.e. aqueous phase reducing process, obtain coulomb island, i.e. Au quantum dot, its particle diameter can be controlled between 2～15 nm, and is assembled in the district of island on coulomb island by electrostatic self-assembled, the atomic force microscopy probe technique that simultaneously may utilize feedback-type moves or carries a coulomb island, so that coulomb Dao Dao district accurate assembly, coulomb island is totally independent of source electrode, drain and gate, and grid is used for regulating and controlling a coulomb island energy level.
Compared with prior art, the beneficial effects of the present invention is: can be movable under the coulomb Dao Dao district electric field action of the present invention, the potential barrier size between electrode and coulomb island has variability, it is not necessary to accurately control potential barrier size；Utilize ripe colloid Au technology of preparing, can accurately prepare the coulomb island of a certain particle diameter between 2 ~ 15 nm；Utilize electrostatic self-assembled and reaction type atomic force microscopy probe technique, the Au quantum dot accurate assembly in island district can be realized.The present invention solves in single-electronic transistor preparation process, and coulomb island size and location thereof assemble uncontrollable problem, avoids the difficult problem that potential barrier size needs accurately to control, significantly reduces difficulty prepared by single-electronic transistor.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of island dynamic formula single-electronic transistor that the inventive method is prepared；
Fig. 2 is source, leakage and the grid of dynamic formula single-electronic transistor in island shown in Fig. 1, Yi Jiyuan, leakage and grid and the scanning electron microscope (SEM) photograph of external relation microelectrode；
Fig. 3 is Tu2Kuang district partial enlarged drawing；
Fig. 4 is Tu3Kuang district partial enlarged drawing；
Fig. 5 is Tu4Kuang district partial enlarged drawing；
Fig. 6 is the I-V characteristic curve that dynamic formula single-electronic transistor in island shown in Fig. 1 is depressed in specific gate.
In figure: 1, silicon chip；2, substrate；3, source electrode；4, coulomb island；5, grid；6, drain electrode；7, island district；8, the lead-in wire electrode being connected with source electrode；9, the lead-in wire electrode being connected with drain electrode；10, the lead-in wire electrode being connected with grid.
Detailed description of the invention
Embodiment 1
Prepared by island dynamic formula single-electronic transistor:
(1) silicon chip 1 is cleaned；
(2) in oxidation furnace, under the conditions of 1000 ° of C, silicon chip 1 is aoxidized 2h, make silicon chip 1 surface form the silicon dioxide insulating layer as substrate 2, silicon dioxide insulating layer thickness about 200 nm；
(3) source electrode 3, drain electrode 6 and grid 5 are prepared on the substrate 2 by electron beam exposure and evaporation coating method, now, use Ti as metal adhesion layers, adhesion layer thickness about 2 nm, use Au as deposition material, deposit material thickness about 5 nm, wherein, electrode minimum feature about 25 nm, described source electrode and drain electrode spacing about 30 nm on substrate；Described grid is spacing about 50 nm on substrate with source electrode and drain electrode；And the micron order lead-in wire electrode 8,9,10 for island dynamic formula single-electronic transistor device being transitioned into macroscopic circuit being connected with source electrode 3, drain electrode 6, grid 5 respectively is prepared on the substrate 2 by general lithographic processes or focused ion beam deposition method, wherein, electrode minimum feature about 2 μm；
(4) by focused-ion-beam lithography method or reactive ion etching method, the region etch between source electrode, drain and gate goes out 20 × 30 × 10 nm as island district 73Pit；
(5) under the conditions of 1000 ° of C, aoxidize 2h, Shi Dao district 7 inside circumference and bottom surface forms silicon dioxide insulating layer；So far, formation has prepared electrode and the transistor device in island district；
(6) method utilizing aqueous phase reduction gold chloride prepares the colloid solution of the Au nanoparticle of particle diameter about 5 nm；
(7) measure chloroform 20 mL, then with microscale sampler measure 3-aminopropyl triethoxysilane (3-aminopropyltriethoxysilane,
APTES) about 40 μ L, makes the chloroformic solution of APTES；
(8) the aforementioned transistor device prepared is immersed in APTES chloroformic solution, carry out sealing, 24 h are kept under room temperature, rinse with isopropanol after taking-up, dry up with nitrogen again, then it is immersed in the colloid solution of the made Au nanoparticle got ready of step (6), completes Au quantum dot Primary Location and assemble；
(9) utilizing sem observation device, labelling assembles unsuccessful island district；
(10) reaction type atomic force microscopy probe technique is utilized to make all islands district be equipped with Au quantum dot；
(11) use wiring machine to carry out gold ball bonding, transistor device is encapsulated on base, completes the preparation of this island dynamic formula single-electronic transistor.
The island dynamic formula single-electronic transistor prepared is carried out I-V characteristic curve test, it is contemplated that result as shown in Figure 6, will show regular electron emission and choking phenomenon.
Embodiment 2
Prepared by island dynamic formula single-electronic transistor:
(1) silicon chip 1 is cleaned；
(2) in oxidation furnace, under the conditions of 1000 ° of C, silicon chip 1 is aoxidized 2h, make silicon chip 1 surface form the silicon dioxide insulating layer as substrate 2, silicon dioxide insulating layer thickness about 300 nm；
(3) source electrode 3, drain electrode 6 and grid 5 are prepared on the substrate 2 by focused ion bundle/e-beam induced deposition method, now, use Pt or W as deposition material, deposition material thickness 15～30 nm, wherein, electrode minimum feature about 25 nm, described source electrode and drain electrode spacing about 30 nm on substrate；Described grid is spacing about 300 nm on substrate with source electrode and drain electrode；And the micron order lead-in wire electrode 8,9,10 for island dynamic formula single-electronic transistor device being transitioned into macroscopic circuit being connected with source electrode 3, drain electrode 6, grid 5 respectively is prepared on the substrate 2 by general lithographic processes or focused ion beam deposition method, wherein, electrode minimum feature about 2 μm；
(4) 20 × 30 × 10 nm as island district 7 are gone out by reactive ion etching method region etch between source electrode, drain and gate3Pit；
(5) under the conditions of 1000 ° of C, aoxidize 2h, Shi Dao district 7 inside circumference and bottom surface forms silicon dioxide insulating layer；So far, formation has prepared electrode and the transistor device in island district；
(6) method utilizing aqueous phase reduction gold chloride prepares the colloid solution of the Au nanoparticle that particle diameter is 2 nm；
(7) measure chloroform 20 mL, then with microscale sampler measure 3-aminopropyl triethoxysilane (3-aminopropyltriethoxysilane,
APTES) about 40 μ L, makes the chloroformic solution of APTES；
(8) the aforementioned transistor device prepared is immersed in APTES chloroformic solution, carry out sealing, 24 h are kept under room temperature, rinse with isopropanol after taking-up, dry up with nitrogen again, then it is immersed in the colloid solution of the made Au nanoparticle got ready of step (6), completes Au quantum dot Primary Location and assemble；
(9) utilizing sem observation device, labelling assembles unsuccessful island district；
(10) reaction type atomic force microscopy probe technique is utilized to make all islands district be equipped with Au quantum dot；
(11) use wiring machine to carry out gold ball bonding, transistor device is encapsulated on base, completes the preparation of this island dynamic formula single-electronic transistor.
Product checking effect is with embodiment 1.
Embodiment 3
Prepared by island dynamic formula single-electronic transistor:
(1) silicon chip 1 is cleaned；
(2) in oxidation furnace, under the conditions of 1000 ° of C, silicon chip 1 is aoxidized 2h, make silicon chip 1 surface form the silicon dioxide insulating layer as substrate 2, silicon dioxide insulating layer thickness about 500 nm；
(3) source electrode 3, drain electrode 6 and grid 5 are prepared on the substrate 2 by electron beam exposure and evaporation coating method, now, employing Ti is metal adhesion layers, adhesion layer thickness about 3 nm, use Au for deposition material, deposit material thickness about 25 nm, wherein, electrode minimum feature about 25 nm, described source electrode and drain electrode spacing about 30 nm on substrate；Described grid is spacing about 500 nm on substrate with source electrode and drain electrode；And the micron order lead-in wire electrode 8,9,10 for island dynamic formula single-electronic transistor device being transitioned into macroscopic circuit being connected with source electrode 3, drain electrode 6, grid 5 respectively is prepared on the substrate 2 by general lithographic processes or focused ion beam deposition method, wherein, electrode minimum feature about 2 μm；
(4) by focused-ion-beam lithography method or reactive ion etching method, the region etch between source electrode, drain and gate goes out 20 × 30 × 10 nm as island district 73Pit；
(5) under the conditions of 1000 ° of C, aoxidize 2h, Shi Dao district 7 inside circumference and bottom surface forms silicon dioxide insulating layer；So far, formation has prepared electrode and the transistor device in island district；
(6) method utilizing aqueous phase reduction gold chloride prepares the colloid solution of the Au nanoparticle of particle diameter about 15 nm；
(7) measure chloroform 20 mL, then with microscale sampler measure 3-aminopropyl triethoxysilane (3-aminopropyltriethoxysilane,
APTES) about 40 μ L, makes the chloroformic solution of APTES；
(8) the aforementioned transistor device prepared is immersed in APTES chloroformic solution, carry out sealing, 24 h are kept under room temperature, rinse with isopropanol after taking-up, dry up with nitrogen again, then it is immersed in the colloid solution of the made Au nanoparticle got ready of step (6), completes Au quantum dot Primary Location and assemble；
(9) utilizing sem observation device, labelling assembles unsuccessful island district；
(10) reaction type atomic force microscopy probe technique is utilized to make all islands district be equipped with Au quantum dot；
(11) use wiring machine to carry out gold ball bonding, transistor device is encapsulated on base, completes the preparation of this island dynamic formula single-electronic transistor.
Product checking effect is with embodiment 1.
Claims (8)
1. the preparation method of an island dynamic formula single-electronic transistor, it is characterized in that, with silicon chip, source electrode, drain electrode, grid, island district and coulomb island as basic structure, source electrode, drain electrode, grid are integrally disposed in the silicon dioxide substrates that silicon substrate surface is formed, the region surrounded between source electrode, drain electrode, grid etches the island district as zone of action, coulomb island, coulomb island is assembled in the district of island；Specifically include following steps:
(1) silicon chip after thermal oxidation is cleaned, makes silicon substrate surface form silicon dioxide substrates；
(2) in silicon dioxide substrates, source electrode, drain electrode, grid are prepared；
(3) region etch surrounded between source electrode, drain and gate goes out the pit as island district；
(4) silicon dioxide insulating layer is formed by thermal oxide or dual-beam equipment induced deposition Shi Dao district's inside circumference and bottom surface；
(5) prepare, by aqueous phase reducing process, the gold nano grain that particle diameter is 2～15 nm, as coulomb island；
(6) coulomb island is assembled in the district of island；It is to utilize electrostatic self-assembled method that described coulomb island is assembled in island district, assists with reaction type atomic force microscopy probe, is assembled in the district of island on coulomb island；
(7) measure chloroform 20 mL, then with microscale sampler measure 3-aminopropyl triethoxysilane (3-aminopropyltriethoxysilane,
APTES) about 40 μ L, makes the chloroformic solution of APTES；
(8) the aforementioned transistor device prepared is immersed in APTES chloroformic solution, carry out sealing, 24 h are kept under room temperature, rinse with isopropanol after taking-up, dry up with nitrogen again, then it is immersed in the colloid solution of the made Au nanoparticle got ready of step (6), completes Au quantum dot Primary Location and assemble.
2. the method for claim 1, it is characterised in that described step (2) is by focusing on e-beam induced deposition method, or utilizes electron beam exposure and evaporation coating method to prepare the source electrode of nano-scale, drain and gate in silicon dioxide substrates；And the micron order lead-in wire electrode for island dynamic formula single-electronic transistor device being transitioned into macroscopic circuit being connected with source electrode, drain electrode, grid respectively can be prepared on substrate by Ultraviolet lithography or focused ion beam deposition method.
3. the method for claim 1, it is characterised in that described silicon dioxide substrates thickness is 200～500 nm.
4. the method for claim 1, it is characterised in that described source electrode, drain and gate use electron beam exposure and vapour deposition method to prepare, wherein, employing Ti is metal adhesion layers, and adhesion layer thickness is 2～3 nm, using Au for deposition material, deposition material thickness is 5～25 nm.
5. the method for claim 1, it is characterised in that described source electrode, drain and gate use focusing e-beam induced deposition method to prepare, wherein, uses Pt or W for deposition material, and deposition material thickness is 15～30 nm.
6. the method for claim 1, it is characterised in that described source electrode and drain electrode spacing in silicon dioxide substrates are 30 nm；Spacing on substrate is 50～500 nm to described grid with source electrode and drain electrode.
7. the method for claim 1, it is characterised in that described etching island district refers to etch island district by focused-ion-beam lithography method or reactive ion etching method.
8. the method for claim 1, it is characterised in that the size in described island district is 20 × 30 × 10 nm3。
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| US10032897B2 (en) | 2016-06-01 | 2018-07-24 | International Business Machines Corporation | Single electron transistor with self-aligned Coulomb blockade |
| CN106935501B (en) * | 2016-10-19 | 2023-08-22 | 中国人民解放军国防科学技术大学 | Method for preparing single-electron transistor by assembling gold particles with polystyrene microsphere template |
| CN106383163B (en) * | 2016-10-19 | 2023-10-17 | 中国人民解放军国防科学技术大学 | Ionization type gas sensor based on single-electron transistor and preparation method thereof |
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| US5997958A (en) * | 1997-03-13 | 1999-12-07 | Hitachi Europe Limited | Method of depositing nanometer scale particles |
| CN101783364A (en) * | 2009-01-21 | 2010-07-21 | 中国科学院微电子研究所 | Nano electronic part and production method thereof |
| CN102169837A (en) * | 2011-03-12 | 2011-08-31 | 中国科学院苏州纳米技术与纳米仿生研究所 | Preparation method of single electron transistor at room temperature |
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| US5997958A (en) * | 1997-03-13 | 1999-12-07 | Hitachi Europe Limited | Method of depositing nanometer scale particles |
| CN101783364A (en) * | 2009-01-21 | 2010-07-21 | 中国科学院微电子研究所 | Nano electronic part and production method thereof |
| CN102169837A (en) * | 2011-03-12 | 2011-08-31 | 中国科学院苏州纳米技术与纳米仿生研究所 | Preparation method of single electron transistor at room temperature |
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