CN103529338B - A kind of fuse power-up state reading circuit of tandem and method - Google Patents
A kind of fuse power-up state reading circuit of tandem and method Download PDFInfo
- Publication number
- CN103529338B CN103529338B CN201310529936.9A CN201310529936A CN103529338B CN 103529338 B CN103529338 B CN 103529338B CN 201310529936 A CN201310529936 A CN 201310529936A CN 103529338 B CN103529338 B CN 103529338B
- Authority
- CN
- China
- Prior art keywords
- fuse
- array
- control signal
- fuses
- reading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Read Only Memory (AREA)
Abstract
The present invention relates to a kind of fuse power-up state reading circuit and method of tandem, comprise electrification reset and FUSE reading Waveform generating circuit, fuse terminal processing module and the delay cell equal with multiple array of fuses Fuse_ARRAY quantity, electrification reset and FUSE read Waveform generating circuit and produce the fuse_sense control signal and fuse_latch control signal that are used for fuse reading, are input to the input end of the array of fuses Fuse_ARRAY be positioned at foremost; Delay cell is arranged between two adjacent fuse arrays; Fuse terminal processing module is used for generating fuse_done signal when receiving the signal being positioned at rearmost end array of fuses Fuse_ARRAY transmission, and sends to electrification reset and FUSE to read Waveform generating circuit.More in order to solve existing fuse quantity, technical matters peak point current being brought excessive when chip power-up initializing, by the fuse number in tandem method restriction fuse reading process, reaches the object reading and reduce peak point current in fuse process.
Description
Technical field
The invention belongs to microelectronic circuit designing technique, the application based on laser fuse proposes a kind of fuse read method of tandem.
Background technology
Along with the complexity day by day of chip technology, the design objective of modular circuit is also more and more higher, but due to the existence of semiconductor process variation, in most cases, the parameter index of circuit design offsets within the specific limits, in order to improve yields, use the mode trimmed in the design more, and the net result trimmed needs to adopt certain form to fix, mostly adopt the mode of laser fuse or electric fuse at present, wherein laser fuse uses the most general.When chip functions is complicated, in order to ensure the yield of chip, usually a lot of fuses can be used to trim, state after trimming needs to read when chip power-up initializing, but because fuse quantity is more, although there are means to reduce the reading power consumption of unit fuse, if the excessive problem of peak point current can be brought to the reading that the fuse that nearly hundreds of is individual walks abreast thus may cause: 1, state initialization failure; 2, the problem such as bolt-lock or electromigration that causes of peak point current.
Summary of the invention
More in order to solve existing fuse quantity, technical matters peak point current being brought excessive when chip power-up initializing, the invention provides a kind of tandem fuse power-up state reading circuit and method, a kind of low-power consumption laser fuse read method, by the fuse number in tandem method restriction fuse reading process, reach the object reading and reduce peak point current in fuse process.
Technical solution of the present invention is:
A kind of fuse power-up state reading circuit of tandem, comprise electrification reset and FUSE reading Waveform generating circuit, fuse terminal processing module and the delay cell equal with multiple array of fuses Fuse_ARRAY quantity, wherein array of fuses Fuse_ARRAY is that electric current, the execution efficiency of needs and the sequencing read according to all fuses divides
Described electrification reset and FUSE read Waveform generating circuit and produce the fuse_sense control signal and fuse_latch control signal that are used for fuse reading, are input to the input end of the array of fuses Fuse_ARRAY be positioned at foremost;
Described delay cell is arranged between two adjacent fuse arrays; Described fuse terminal processing module is used for generating fuse_done signal when receiving the signal being positioned at rearmost end array of fuses Fuse_ARRAY transmission, and sends to electrification reset and FUSE to read Waveform generating circuit.
A kind of tandem fuse power-up state read method, comprises the following steps:
1] electrification reset and fuse read wave generating unit monitoring outer power voltage, first produce the Fuse_latch control signal and Fuse_sense control signal that read for fuse when voltage is enough high;
2] Fuse_latch control signal and Fuse_sense control signal enter the first array of fuses FUSE_ARRAY1 being positioned at front end;
3] state of the first array of fuses FUSE_ARRAY1 reads and terminates rear generation Fuse_latch2 control signal and Fuse_sense2 control signal enters into the first delay cell;
4] the feeding second array of fuses FUSE_ARRAY2 after Fuse_latch control signal and the delayed cell delay of Fuse_sense control signal;
5] repeat step 2], 3], 4] until Fuse_latch control signal and Fuse_sense control signal enter into last array of fuses FUSE_ARRAYN, after the reading of last array of fuses terminates, Fuse_latch control signal and Fuse_sense control signal enter fuse terminal processing module Fuse_end;
6] fuse terminal processing module Fuse_end produces fuse_done signal, and sends to electrification reset and FUSE to read Waveform generating circuit, represents that whole fuse has read.
Above-mentioned array of fuses Fuse_ARRAY is that electric current, the execution efficiency of needs and the sequencing read according to all fuses divides.
Advantage that the present invention has is:
1, modularization, is convenient to realize.The present invention uses the unit module of standard to build, compact conformation and power consumption is little, and area cost is lower.
2, applied range.Of the present inventionly allly need to use laser fuse to carry out powering on the field of initial value configuration.
3, the present invention is that application significantly can reduce the peak point current reading fuse and cause, and is conducive to the reliably working of chip power-up initializing state.
4, the invention provides fuse and read complete instruction, can be used for ensureing that the state of chip initiation is complete
5, use the present invention's success built-in 138 fuses in certain chip, realize powering on the control of original state, power on current spike surge current, and work reliably and with long-term.
Accompanying drawing explanation
Fig. 1 is circuit theory schematic diagram of the present invention; In figure: electrification reset and fuse waveform generation module produce the necessary sequential of read operation; FUSE_ARRAY1/FUSE_ARRAY2/FUSE_ARRAY3 is the array of fuses that tandem connects; Necessity that delay cell produces control signal postpones; FUSE_END is fuse terminal processing module.
Embodiment
The present invention is directed to the application of laser fuse, propose a kind of low-power consumption, the laser fuse state that the powers on reading circuit of tandem, its special character is: in chip power up, by the electrification reset module of chip under the enough state of external voltage, produce fuse_sense and the fuse_latch signal being used for fuse and reading, the fuse state that first signal controls Part I reads, after reading completes, through one section of delay, the fuse controlling Part II reads, perform according to tandem moor, until last fuse state has read, produce fuse_done, represent that whole fuse has read.
It is tandem relation between array of fuses Fuse_ARRAY.
Execution efficiency and the sequencing of the electric current that the arrangement of the fuse of One's name is legion can be read according to fuse and needs are divided into multiple array of fuses Fuse_ARRAY, each array of fuses Fuse_ARRAY comprise one to tens not wait fuse module, but each array of fuses Fuse_ARRAY) between be seen as tandem relation from signal control flow.
Delay cell is comprised between two array of fuses.After previous array of fuses Fuse_ARRAY has read, in stable condition for what guarantee after reading, simultaneously electric current has got back to normal value, needs delay cell to carry out necessary delay, avoid the superposition of electric current before starting next array of fuses Fuse_ARRAY and operating.
After fuse terminal processing module (Fuse_end) is placed on last array of fuses Fuse_ARRAY,
When signal arrives this module, represent that all fuses have read, and module sends fuse_done thus
Signal, indicating fuse reads complete.Fuse terminal processing module produces and is used to indicate fuse state reading
Complete fuse_done, and feed back to electrification reset and fuse reading wave generating unit.
Circuit theory signal of the present invention is see Fig. 1.
Step 1 electrification reset and fuse read wave generating unit monitoring outer power voltage, first produce the control signal Fuse_latch control signal and Fuse_sense control signal that read for fuse when voltage is enough high.
Step 2 control signal Fuse_latch control signal and Fuse_sense control signal enter tandem first array of fuses FUSE_ARRAY1.
The reading of step 3 first array of fuses FUSE_ARRAY1 terminates rear Fuse_latch control signal and Fuse_sense control signal enters into delay cell, and be delayed stablizing for fuse state.
Feeding second array of fuses FUSE_ARRAY2 after step 4Fuse_latch control signal and the delayed cell delay of Fuse_sense control signal control signal.
Step 5 repeats step 2,3,4 until Fuse_latch control signal and Fuse_sense control signal arrive last array of fuses, after the reading of last array of fuses state terminates, Fuse_latch4 and Fuse_sense4 enters into fuse terminal processing module (Fuse_end).
Step 6 fuse terminal processing module Fuse_end produces fuse_done signal, represents that whole fuse state reads complete, and returns to electrification reset and fuse reading wave generating unit.
Of the present inventionly mainly specially be that by the reading process of array of fuses be tandem work, only have an array to carry out the reading of fuse at every turn, the next one is performed again after having operated, each fuse only reading limited quantity in the course of work, reduce the peak power powered on, meanwhile, the reading sequencing of fuse state can be distinguished according to the practical application of chip, improve the reliability powered on.
Claims (3)
1. the fuse power-up state reading circuit of a tandem, it is characterized in that: comprise electrification reset and FUSE reading Waveform generating circuit, fuse terminal processing module and the delay cell equal with multiple array of fuses Fuse_ARRAY quantity, wherein array of fuses Fuse_ARRAY is that electric current, the execution efficiency of needs and the sequencing read according to all fuses divides
Described electrification reset and FUSE read Waveform generating circuit and produce the fuse_sense control signal and fuse_latch control signal that are used for fuse reading, and fuse_sense control signal and fuse_latch control signal are input to the input end of the array of fuses Fuse_ARRAY be positioned at foremost;
Described delay cell is arranged between two adjacent fuse array Fuse_ARRAY; Described fuse terminal processing module is used for generating fuse_done signal when receiving the signal being positioned at rearmost end array of fuses Fuse_ARRAY transmission, and sends to electrification reset and FUSE to read Waveform generating circuit.
2. a tandem fuse power-up state read method, is characterized in that: comprise the following steps:
1] electrification reset and fuse read Waveform generating circuit monitoring outer power voltage, first produce the Fuse_latch control signal and Fuse_sense control signal that read for fuse when voltage is enough high;
2] Fuse_latch control signal and Fuse_sense control signal enter the first array of fuses FUSE_ARRAY1 being positioned at front end;
3] state of the first array of fuses FUSE_ARRAY1 reads and terminates rear generation Fuse_latch2 control signal and Fuse_sense2 control signal enters into the first delay cell;
4] Fuse_latch2 control signal and the Fuse_sense2 control signal feeding second array of fuses FUSE_ARRAY2 after the first delay units delay;
5] repeat step 2], 3], 4] until Fuse_latchN control signal and Fuse_senseN control signal enter into last array of fuses FUSE_ARRAYN, after the reading of last array of fuses FUSE_ARRAYN terminates, Fuse_latchN control signal and Fuse_senseN control signal enter fuse terminal processing module Fuse_end;
6] fuse terminal processing module Fuse_end produces fuse_done signal, and sends to electrification reset and FUSE to read Waveform generating circuit, represents that whole fuse has read.
3. tandem fuse power-up state read method according to claim 2, is characterized in that: array of fuses Fuse_ARRAY is that electric current, the execution efficiency of needs and the sequencing read according to all fuses divides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310529936.9A CN103529338B (en) | 2013-10-30 | 2013-10-30 | A kind of fuse power-up state reading circuit of tandem and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310529936.9A CN103529338B (en) | 2013-10-30 | 2013-10-30 | A kind of fuse power-up state reading circuit of tandem and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103529338A CN103529338A (en) | 2014-01-22 |
| CN103529338B true CN103529338B (en) | 2016-02-24 |
Family
ID=49931503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310529936.9A Active CN103529338B (en) | 2013-10-30 | 2013-10-30 | A kind of fuse power-up state reading circuit of tandem and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103529338B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105281728B (en) * | 2014-06-12 | 2018-06-15 | 华邦电子股份有限公司 | Semiconductor device |
| CN105261399B (en) * | 2015-11-16 | 2018-05-18 | 西安紫光国芯半导体有限公司 | The method for improving slack storage array utilization ratio |
| CN108335717B (en) * | 2018-02-07 | 2020-12-01 | 深圳市创新微源半导体有限公司 | Permanent configuration circuit after encapsulation |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6459652B1 (en) * | 2001-07-04 | 2002-10-01 | Samsung Electronics Co., Ltd. | Semiconductor memory device having echo clock path |
| CN1941206A (en) * | 2005-09-26 | 2007-04-04 | 旺宏电子股份有限公司 | Method and circuit for reading fuse cells in a nonvolatile memory during power-up |
| CN1945744A (en) * | 2005-10-06 | 2007-04-11 | 国际商业机器公司 | Apparatus and method for using fuse to store PLL configuration data |
| CN101131874A (en) * | 2006-08-22 | 2008-02-27 | 富士通株式会社 | Semiconductor integrated circuit and test method thereof |
| CN201392350Y (en) * | 2009-03-18 | 2010-01-27 | 上海华岭集成电路技术有限责任公司 | Probe card for anti-interference asynchronous trimming wafer test |
| CN102749575A (en) * | 2011-04-18 | 2012-10-24 | 安凯(广州)微电子技术有限公司 | Electronic fuse state reader |
| CN103295640A (en) * | 2012-02-27 | 2013-09-11 | 三星电子株式会社 | Semiconductor device capable of rescuing defective characteristics occurring after packaging |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5459693A (en) * | 1990-06-14 | 1995-10-17 | Creative Integrated Systems, Inc. | Very large scale integrated planar read only memory |
| JP3898682B2 (en) * | 2003-10-03 | 2007-03-28 | 株式会社東芝 | Semiconductor integrated circuit |
| JP4761995B2 (en) * | 2006-02-16 | 2011-08-31 | 株式会社東芝 | Semiconductor integrated circuit and test method thereof |
-
2013
- 2013-10-30 CN CN201310529936.9A patent/CN103529338B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6459652B1 (en) * | 2001-07-04 | 2002-10-01 | Samsung Electronics Co., Ltd. | Semiconductor memory device having echo clock path |
| CN1941206A (en) * | 2005-09-26 | 2007-04-04 | 旺宏电子股份有限公司 | Method and circuit for reading fuse cells in a nonvolatile memory during power-up |
| CN1945744A (en) * | 2005-10-06 | 2007-04-11 | 国际商业机器公司 | Apparatus and method for using fuse to store PLL configuration data |
| CN101131874A (en) * | 2006-08-22 | 2008-02-27 | 富士通株式会社 | Semiconductor integrated circuit and test method thereof |
| CN201392350Y (en) * | 2009-03-18 | 2010-01-27 | 上海华岭集成电路技术有限责任公司 | Probe card for anti-interference asynchronous trimming wafer test |
| CN102749575A (en) * | 2011-04-18 | 2012-10-24 | 安凯(广州)微电子技术有限公司 | Electronic fuse state reader |
| CN103295640A (en) * | 2012-02-27 | 2013-09-11 | 三星电子株式会社 | Semiconductor device capable of rescuing defective characteristics occurring after packaging |
Non-Patent Citations (1)
| Title |
|---|
| 反熔丝FPGA的电离总剂量效应与加固技术;赵聚朝;《核电子学与探测技术》;20021130;第22卷(第6期);第559-562页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103529338A (en) | 2014-01-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102945217B (en) | Triple modular redundancy based satellite-borne comprehensive electronic system | |
| CN103529338B (en) | A kind of fuse power-up state reading circuit of tandem and method | |
| JP2011501850A5 (en) | ||
| CN103744803A (en) | Power supply component and storage system | |
| CN106200854A (en) | A kind of based on the dual master control modular system starting-up method under multiple powering mode | |
| CN103019127A (en) | Electrifying control circuit | |
| CN104461994A (en) | FPGA-based embedded processor dynamic configuration circuit and method | |
| CN105006961A (en) | Power on sequence control circuit on multi-channel power supply and method | |
| CN201707642U (en) | Device for reducing powering up instant power consumption of disk array | |
| CN203261080U (en) | Bi-directional switching type power supply device and control circuit thereof | |
| CN102403885A (en) | Multi-frequency division pulse width modulation control circuit for high-power laser power supply | |
| CN106502363A (en) | A kind of electric power system of multi-node server system | |
| CN104811032A (en) | Charge pump circuit | |
| CN102508536A (en) | One-button startup and shutdown circuit in embedded system and control method thereof | |
| CN105262183A (en) | Power-saving type USB charging structure | |
| CN102375516A (en) | Reset circuit and electronic device | |
| CN105404204A (en) | Control circuit of starting board of avionic device | |
| CN205281492U (en) | Circuit board based on programmable chip | |
| CN103686017A (en) | Power supply control circuit and method for rapidly starting intelligent device | |
| CN102025357A (en) | Discharge circuit | |
| CN101655731B (en) | Switch power supply, computer mainboard and computer | |
| CN107967041A (en) | A kind of power on configuration control method of more FPGA | |
| CN103247411B (en) | A kind of solenoid driver circuit | |
| CN103176583A (en) | Internal memory power supply system | |
| CN113098112A (en) | Charge-discharge controller and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221206 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: No.15, Jinye 2nd Road, Xi'an, Shaanxi 710119 Patentee before: 631ST Research Institute OF AVIC |
|
| TR01 | Transfer of patent right |