CN103528691B - The row strobe generation circuit of infrared focal plane array sensing circuit - Google Patents
The row strobe generation circuit of infrared focal plane array sensing circuit Download PDFInfo
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Abstract
The embodiment of the invention discloses a kind of row strobe generation circuit of infrared focal plane array sensing circuit, odd-numbered line and the even number line of this row strobe generation circuit adopt enable signal EN_R_1 with EN_R_2 be separated, clock signal clk _ R_1 and CLK_R_2 be separated, and output signal is carried out combination and can be realized pixel cell inter-bank gating by the signal be separated by these.Use unified latch clock control signal CLK_T, realize pulse signal and transmit step by step, make Signal transmissions accurate, simple and direct, stable, logical relation is tight.
Description
Technical field
The present invention relates to Infrared Focal plane Array Technologies field, especially relate to a kind of row strobe generation circuit of infrared focal plane array sensing circuit.
Background technology
Current infrared imaging system is just obtaining increasingly extensive application in military affairs, space technology, medical science and national economy association area.Infrared focal plane array assembly is the core light electrical part obtaining infrared image signal in infrared imagery technique.This assembly is made up of infrared eye and infrared focal plane read-out circuit (ROIC:readout integrated circuits).Along with the continuous expansion of infrared focal plane array assembly scale, as the serviceability that the infrared focal plane read-out circuit demand fulfillment of its important component part is high.
ROIC circuit is the highly integrated circuit of various function i ntegration in single semi-conductor chip focal plane, and its basic function carries out the conversion of infrared eye signal, amplification and transmission, is transferred to output terminal by data successively from many detector ends.Common ROIC circuit comprises element circuit, column readout stage and output buffer stage, timing sequence generating circuit, row strobe generation circuit, row strobe generation circuit.Row strobe generation circuit is the important component part of ROIC circuit, and its performance quality directly affects the performance of whole sensing circuit.
In existing infrared focal plane read-out circuit, row strobe generation circuit only has a kind of way of output, namely export from top to bottom line by line, therefore, each two field picture is lined by line scan excessive cycle, and available circuit complex structure, each control signal in circuit and back end signal processing unit are all had high requirements.
Summary of the invention
An object of the present invention is to provide a kind of row strobe generation circuit that can realize the infrared focal plane array sensing circuit of the multiple gated mode of pixel cell in infrared focal plane array.
Technical scheme disclosed by the invention comprises:
Provide a kind of row strobe generation circuit of infrared focal plane array sensing circuit, it is characterized in that, comprise: the basic row gating signal generation unit circuit of multiple mutual cascade, the basic row gating signal generation unit circuit of described multiple mutual cascade comprises odd-numbered line basic row gating signal generation unit circuit and even number line basic row gating signal generation unit circuit, wherein: the input end of each described odd-numbered line basic row gating signal generation unit circuit is connected respectively to downstream pulses signal input part IN_DOWN, the upstream bursts signal input part IN_UP of described row strobe generation circuit, control data input end IN<8:0>, the first control signal input end C_UP, the second control signal input end C_UPB, odd-numbered line input end of clock CLK_R_1 and the enable input end EN_R_1 of odd-numbered line, the input end of each described even number line basic row gating signal generation unit circuit is connected respectively to the described downstream pulses signal input part IN_DOWN of described row strobe generation circuit, described upstream bursts signal input part IN_UP, described control data input end IN<8:0>, described first control signal input end C_UP, described second control signal input end C_UPB, even number line input end of clock CLK_R_2 and the enable input end EN_R_2 of even number line.
In one embodiment of the present of invention, each basic row gating signal generation unit circuit in the basic row gating signal generation unit circuit of described multiple mutual cascade also comprises first module enable signal output terminal C_EN1, first module selects signal output part C_SEL1, second unit enable signal input end C_EN2 and second unit select signal input part C_SEL2, wherein, the first module enable signal output terminal C_EN1 of each basic row gating signal generation unit circuit is connected to the second unit enable signal input end C_EN2 of connected next basic row gating signal generation unit, and the second unit that the first module of each basic row gating signal generation unit circuit selects signal output part C_SEL1 to be connected to a connected upper basic row gating signal generation unit circuit selects signal input part C_SEL2.
In one embodiment of the present of invention, each basic row gating signal generation unit circuit in the basic row gating signal generation unit circuit of described multiple mutual cascade also comprises pulse signal output end OUT_TB, the pulse signal output end OUT_TB of each basic row gating signal generation unit circuit is connected to the downstream pulses signal input part IN_DOWN of connected next basic row gating signal generation unit circuit, and is connected to the upstream bursts signal input part IN_UP of a connected upper basic row gating signal generation unit circuit.
In one embodiment of the present of invention, each described odd-numbered line basic row gating signal generation unit circuit comprises the first transmission gate T1, the second transmission gate T2, the first Sheffer stroke gate AN1, the first phase inverter N1, the second phase inverter N2, the first d type flip flop D1, the first latch L1, the second latch L2 and the 3rd latch L3; First control end of described first transmission gate T1 is connected to described first control signal input end C_UP; Second control end of described first transmission gate T1 is connected to described second control signal input end C_UPB; The input end of described first transmission gate T1 is connected to described downstream pulses signal input part IN_DOWN; The output terminal of described first transmission gate T1 is connected to the output terminal of described second transmission gate T2; First control end of described second transmission gate T2 is connected to described second control signal input end C_UPB; Second control end of described second transmission gate T2 is connected to described first control signal input end C_UP; The input end of described second transmission gate T2 is connected to described upstream bursts signal input part IN_UP; Be connected to second input end of the first Sheffer stroke gate AN1 described in the output terminal of described first transmission gate T1 and described second transmission gate T2, the first input end of described first Sheffer stroke gate AN1 is connected to the enable input end EN_R_1 of described odd-numbered line; The output terminal of described first transmission gate T1 and described second transmission gate T2 is also connected to the second input end DB of described first latch L1 and is connected to the first input end D of described first latch L1 by described second phase inverter N2; The second output terminal QB of described first latch L1 is connected to the pulse signal output end OUT_TB of current odd capable basic row gating signal generation unit circuit; The output terminal of described first Sheffer stroke gate AN1 is connected to the first input end D of described first d type flip flop D1, and is connected to the second input end DB of described first d type flip flop D1 by described first phase inverter N1; The clock signal input terminal CLK_R of described first d type flip flop D1 is connected to described odd-numbered line input end of clock CLK_R_1; The first output terminal Q of described first d type flip flop D1 is connected to the first input end D of described second latch L2; The second output terminal QB of described first d type flip flop D1 is connected to the second input end DB of described second latch L2; The clock signal input terminal CLK of described second latch L2 is connected to described odd-numbered line input end of clock CLK_R_1; The first output terminal Q of described second latch L2 is connected to the first input end D of described 3rd latch L3; The second output terminal QB of described second latch L2 is connected to the second input end DB of described 3rd latch L3; The clock signal input terminal CLK of described 3rd latch L3 is connected to described odd-numbered line input end of clock CLK_R_1.
In one embodiment of the present of invention, each described even number line basic row gating signal generation unit circuit comprises the 9th transmission gate T9, the tenth transmission gate T10, the second Sheffer stroke gate AN2, the 4th phase inverter N4, the 5th phase inverter N5, the second d type flip flop D2, quad latch L4, the 5th latch L5 and the 6th latch L6; First control end of described 9th transmission gate T9 is connected to described first control signal input end C_UP; Second control end of described 9th transmission gate T9 is connected to described second control signal input end C_UPB; The input end of described 9th transmission gate T9 is connected to described downstream pulses signal input part IN_DOWN; The output terminal of described 9th transmission gate T9 is connected to the output terminal of described tenth transmission gate T10; First control end of described tenth transmission gate T10 is connected to described second control signal input end C_UPB; Second control end of described tenth transmission gate T10 is connected to described first control signal input end C_UP; The input end of described tenth transmission gate T10 is connected to described upstream bursts signal input part IN_UP; Be connected to second input end of the second Sheffer stroke gate AN2 described in the output terminal of described 9th transmission gate T9 and described tenth transmission gate T10, the first input end of described second Sheffer stroke gate AN2 is connected to the enable input end EN_R_1 of described even number line; The output terminal of described 9th transmission gate T9 and described tenth transmission gate T10 is also connected to the second input end DB of described quad latch L4 and is connected to the first input end D of described quad latch L4 by described 5th phase inverter N5; The second output terminal QB of described quad latch L4 is connected to the pulse signal output end OUT_TB of current even number line basic row gating signal generation unit circuit; The output terminal of described second Sheffer stroke gate AN2 is connected to the first input end D of described second d type flip flop D2, and is connected to the second input end DB of described second d type flip flop D2 by described 4th phase inverter N4; The clock signal input terminal CLK_R of described second d type flip flop D2 is connected to described even number line input end of clock CLK_R_2; The first output terminal Q of described second d type flip flop D2 is connected to the first input end D of described 5th latch L5; The second output terminal QB of described second d type flip flop D2 is connected to the second input end DB of described 5th latch L5; The clock signal input terminal CLK of described 5th latch L5 is connected to described even number line input end of clock CLK_R_2; The first output terminal Q of described 5th latch L5 is connected to the first input end D of described 6th latch L6; The second output terminal QB of described 5th latch L5 is connected to the second input end DB of described 6th latch L6; The clock signal input terminal CLK of described 6th latch L6 is connected to described even number line input end of clock CLK_R_2.
In the aforesaid embodiment of the present invention, the odd-numbered line that row gating signal produces integrated circuit adopts enable signal EN_R_1 with EN_R_2 be separated, clock signal clk _ R_1 and CLK_R_2 be separated with even number line, can realize pixel cell inter-bank gating by output signal being carried out combination.Use unified latch clock control signal CLK_T, realize pulse signal and transmit step by step, make Signal transmissions accurate, simple and direct, stable, logical relation is tight.
Accompanying drawing explanation
Fig. 1 is the port schematic diagram of the row strobe generation circuit of one embodiment of the invention.
Fig. 2 is the schematic diagram of the annexation of part (four) the basic row gating signal generation unit circuit of the row strobe generation circuit of one embodiment of the invention.
Fig. 3 is the structural representation of the odd-numbered line basic row gating signal generation unit circuit of one embodiment of the invention.
Fig. 4 is the structural representation of the even number line basic row gating signal generation unit circuit of one embodiment of the invention.
Fig. 5 be in one embodiment of the invention pixel cell line by line from top to bottom gating time signal sequence schematic diagram.
Fig. 6 be in one embodiment of the invention pixel cell line by line from bottom to top gating time signal sequence schematic diagram.
Fig. 7 be in one embodiment of the invention pixel cell even number line from top to bottom gating time signal sequence schematic diagram.
Fig. 8 be in one embodiment of the invention pixel cell even number line from bottom to top gating time signal sequence schematic diagram.
Fig. 9 be in one embodiment of the invention pixel cell odd-numbered line from top to bottom gating time signal sequence schematic diagram.
Figure 10 be in one embodiment of the invention pixel cell odd-numbered line from bottom to top gating time signal sequence schematic diagram.
Embodiment
The row strobe generation circuit of the infrared focal plane array sensing circuit of embodiments of the invention is described in detail below in conjunction with accompanying drawing.
Fig. 1 is the overall schematic of the row strobe generation circuit of one embodiment of the invention.As shown in Figure 1, the row strobe generation circuit of the embodiment of the present invention comprises downstream pulses signal input part IN_DOWN, upstream bursts signal input part IN_UP, control data input end IN<8:0>, first control signal input end C_UP, second control signal input end C_UPB, odd-numbered line input end of clock CLK_R_1, even number line input end of clock CLK_R_2, the enable input end EN_R_1 of odd-numbered line, the enable input end EN_R_2 of even number line, latch clock input end CLK_T, first output signal end OUT_SEL<n-1:0>, second output signal end OUT_SW<n-1:0>, 3rd output signal end OUT_EN<n-1:0>, 4th output signal end EN0, 5th output signal end SEL0, 6th output signal end EN1 and the 7th output signal end SEL1.
In embodiments of the invention, the row strobe generation circuit shown in Fig. 1 is formed by n+2 basic row gating signal generation unit circuits cascading, and wherein n is the line number of infrared focal plane array, and n is even number.
In n+2 basic row gating signal generation unit circuit of this cascade, the basic row gating signal generation unit circuit being positioned at odd-numbered line is odd-numbered line basic row gating signal generation unit circuit, and the basic row gating signal generation unit circuit being positioned at even number line is even number line basic row gating signal generation unit circuit.That is, n+2 basic row gating signal generation unit circuit of this cascade comprises (n+2)/2 odd-numbered line basic row gating signal generation unit circuit and (n+2)/2 even number line basic row gating signal generation unit circuit, these odd-numbered line basic row gating signal generation unit circuit and the interlaced other in cascade of even number line basic row gating signal generation unit circuit, namely, an odd-numbered line basic row gating signal generation unit circuit is connected to an even number line basic row gating signal generation unit circuit, this even number line basic row gating signal generation unit circuit is connected to again next odd-numbered line basic row gating signal generation unit circuit, and this next odd-numbered line basic row gating signal generation unit circuit is connected to next even number line basic row gating signal generation unit circuit, the like.
Fig. 2 shows interconnective 2 odd-numbered line basic row gating signal generation unit circuit and 2 even number line basic row gating signal generation unit circuit.Easy understand, in embodiments of the invention, remaining odd-numbered line basic row gating signal generation unit circuit is connected according to the mode similar with the connected mode in Fig. 2 with even number line basic row gating signal generation unit circuit.
As shown in Figure 2, each basic row gating signal generation unit circuit also comprises first module enable signal output terminal C_EN1, first module selection signal output part C_SEL1, second unit enable signal input end C_EN2 and second unit selection signal input part C_SEL2.Wherein, the first module enable signal output terminal C_EN1 of each basic row gating signal generation unit circuit is connected to the second unit enable signal input end C_EN2 of connected next basic row gating signal generation unit, and the second unit that the first module of each basic row gating signal generation unit circuit selects signal output part C_SEL1 to be connected to a coupled upper basic row gating signal generation unit circuit selects signal input part C_SEL2.
As shown in Figure 2, each odd-numbered line basic row gating signal generation unit circuit comprises multiple input end, and the plurality of input end correspondence is connected to control data input end IN<8:0>, the first control signal input end C_UP of aforesaid row strobe generation circuit, the second control signal input end C_UPB, odd-numbered line input end of clock CLK_R_1, the enable input end EN_R_1 of odd-numbered line and latch clock input end CLK_T.
When according to order from top to bottom to multiple basic row gating signal generation unit circuit by 1 from small to large open numbering time, wherein multiple output terminals of the 1st basic row gating signal generation unit circuit (it is odd-numbered line basic row gating signal generation unit circuit) are connected respectively the 4th output signal end EN0 and the 5th output signal end SEL0, multiple output terminals of the n-th+2 row basic row gating signal generation unit circuit (it is even number line basic row gating signal generation unit circuit) are connected respectively the 6th output signal end EN1 and the 7th output signal end SEL1.The multiple output terminals correspondence of all the other each odd-numbered line basic row gating signal generation unit circuit is connected to 1 in the first output signal end OUT_SEL<n-1:0> 1, in the second output signal end OUT_SW<n-1:0> 1 and the 3rd output signal end OUT_EN<n-1:0>.
An input end of the 1st basic row gating signal generation unit circuit (it is odd-numbered line basic row gating signal generation unit circuit) is connected to the downstream pulses signal input part IN_DOWN of aforesaid row strobe generation circuit, and another input end is connected to the upstream bursts signal input part IN_UP of the next even number line basic row gating signal generation unit circuit be adjacent.
In embodiments of the invention, each basic row gating signal generation unit circuit in the basic row gating signal generation unit circuit of multiple mutual cascade also comprises pulse signal output end OUT_TB, the pulse signal output end OUT_TB of each basic row gating signal generation unit circuit is connected to the downstream pulses signal input part IN_DOWN of connected next basic row gating signal generation unit circuit, and is connected to the upstream bursts signal input part IN_UP of a connected upper basic row gating signal generation unit circuit.
Such as, 1st basic row gating signal generation unit circuit also comprises pulse signal output end OUT_TB, and this pulse signal output end OUT_TB is connected to the downstream pulses signal input part IN_DOWN of coupled next even number line basic row gating signal generation unit circuit.
The pulse signal output end OUT_TB of remaining basic row gating signal generation unit circuit (it is even number line basic row gating signal generation unit circuit or odd-numbered line basic row gating signal generation unit circuit) is connected to the downstream pulses signal input part IN_DOWN of the next basic row gating signal generation unit circuit be adjacent, and is connected to the upstream bursts signal input part IN_UP of the upper basic row gating signal generation unit circuit be adjacent.
As shown in Figure 2, each even number line basic row gating signal generation unit circuit comprises multiple input end, and the plurality of input end correspondence is connected to control data input end IN<8:0>, the first control signal input end C_UP of aforesaid row strobe generation circuit, the second control signal input end C_UPB, even number line input end of clock CLK_R_2, the enable input end EN_R_2 of even number line and latch clock input end CLK_T.
Fig. 3 is the structural representation of the odd-numbered line basic row gating signal generation unit circuit of one embodiment of the invention.
As shown in Figure 3, each odd-numbered line basic row gating signal generation unit circuit comprises the first transmission gate T1, the second transmission gate T2, the first Sheffer stroke gate AN1, the first phase inverter N1, the second phase inverter N2, the first d type flip flop D1, the first latch L1, the second latch L2, the 3rd latch L3, first and door A1, the 3rd phase inverter N3, the 3rd transmission gate T3, the 4th transmission gate T4, the 5th transmission gate T5, the 6th transmission gate T6, the 7th transmission gate T7 and the 8th transmission gate T8.
In each transmission gate aforesaid, each transmission gate comprises the first control end, the second control end, input end and output terminal.
First control end of the first transmission gate T1 is connected to the first control signal input end C_UP; Second control end of the first transmission gate T1 is connected to the second control signal input end C_UPB; The input end of the first transmission gate T1 is connected to downstream pulses signal input part IN_DOWN; The output terminal of the first transmission gate T1 is connected to the output terminal of the second transmission gate T2.
First control end of the second transmission gate T2 is connected to the second control signal input end C_UPB; Second control end of the second transmission gate T2 is connected to the first control signal input end C_UP; The input end of the second transmission gate T2 is connected to upstream bursts signal input part IN_UP; The output terminal of the second transmission gate T2 is connected to the output terminal of the first transmission gate T1 as mentioned before.
The output terminal of the first transmission gate T1 and the second transmission gate T2 is interconnected, and is connected to second input end of the first Sheffer stroke gate AN1, and the first input end of this first Sheffer stroke gate AN1 is connected to the enable input end EN_R_1 of odd-numbered line.The output terminal of the first transmission gate T1 and the second transmission gate T2 is also connected to the second input end DB of the first latch L1 and is connected to the first input end D of the first latch L1 by the second phase inverter N2.
The input end of clock CLK of the first latch is connected to aforesaid latch clock input end CLK_T, and the second output terminal QB is connected to the pulse signal output end OUT_TB of this odd-numbered line basic row gating signal generation unit circuit.
The output terminal of the first Sheffer stroke gate AN1 is connected to the first input end D of the first d type flip flop D1, and is connected to the second input end DB of this first d type flip flop D1 by the first phase inverter N1.
The clock signal input terminal CLK_R of the first d type flip flop D1 is connected to odd-numbered line input end of clock CLK_R_1; The first output terminal Q of the first d type flip flop D1 is connected to the first input end D of the second latch L2, and is connected to the first input end of first and door A1; The second output terminal QB of the first d type flip flop D1 is connected to the second input end DB of the second latch L2, and is connected to the input end of the 3rd transmission gate T3.
The clock signal input terminal CLK of the second latch L2 is connected to odd-numbered line input end of clock CLK_R_1; The first output terminal Q of the second latch L2 is connected to the first input end D of the 3rd latch L3, and is connected to the input end of the 7th transmission gate by the 3rd Sheffer stroke gate N3; The second output terminal QB of the second latch L2 is connected to the second input end DB of the 3rd latch L3.
The clock signal input terminal CLK of the 3rd latch L3 is connected to odd-numbered line input end of clock CLK_R_1; First output terminal of the 3rd latch L3 is connected to second input end of first and door A1.
The output terminal of the 3rd transmission gate T3 is connected to the output terminal of the 4th transmission gate T4, and is connected in the 3rd output signal end OUT_EN<n-1:0>; First control end of the 3rd transmission gate T3 is connected to control data input end IN<1>; Second control end of the 3rd transmission gate T3 is connected to control data input end IN<2>; The input end of the 3rd transmission gate T3 is connected to first module enable signal output terminal C_EN1.
First control end of the 4th transmission gate T4 is connected to control data input end IN<3>; Second control end of the 4th transmission gate T4 is connected to control data input end IN<4>; The input end of the 4th transmission gate T4 is connected to second unit enable signal input end C_EN2.
First is connected to the input end of the 5th transmission gate T5 with the output terminal of door A1; The output terminal of the 5th transmission gate T5 is connected to one in the second output signal end OUT_SW<n-1:0>, and is connected to the output terminal of the 6th transmission gate T6; First control end of the 5th transmission gate T5 is connected to control data input end IN<5>; Second control end of the 5th transmission gate T5 is connected to control data input end IN<6>.
First control end of the 6th transmission gate T6 is connected to control data input end IN<6>; Second control end of the 6th transmission gate T6 is connected to control data input end IN<5>; The input end of the 6th transmission gate T6 is connected to system power supply VDD.
The output terminal of the 7th transmission gate T7 is connected to the output terminal of the 8th transmission gate T8, and is connected in the first output signal end OUT_SEL<n-1:0>; First control end of the 7th transmission gate T7 is connected to control data input end IN<7>; Second control end of the 7th transmission gate T7 is connected to control data input end IN<8>; The input end of the 7th transmission gate T7 is connected to first module and selects signal output part C_SEL1.
First control end of the 8th transmission gate T8 is connected to control data input end IN<8>; Second control end of the 8th transmission gate T8 is connected to control data input end IN<7>; The input end of the 8th transmission gate T8 is connected to second unit and selects signal input part C_SEL2.
In embodiment shown in Fig. 3, the first latch L1 is that high level is effective, and the second latch L2 is Low level effective.When pixel cell from top to bottom gating time, pulse signal direction of transfer is from top to bottom, and C_UP is low level, C_UPB is high level, transmission gate T1 conducting, transmission gate T2 ends, and pulse signal sends into basic row gating signal generation unit circuit at the corresponding levels by IN_DOWN port; When pixel cell from bottom to top gating time, pulse signal direction of transfer is from bottom to top, and C_UP is high level, C_UPB is low level, transmission gate T1 ends, transmission gate T2 conducting, and pulse signal sends into basic row gating signal generation unit circuit at the corresponding levels by IN_UP port.Pulse signal is sent to the first latch L1 and is controlled by signal CLK_T, is delivered to next stage basic row gating signal generation unit circuit, pulse signal is transmitted step by step.When pixel cell step by step gating or odd-numbered line gating time, EN_R_1 is high level, and pulse signal is sent into the second latch L2 of the first d type flip flop D1 and serial connection and the 3rd latch L3 and controlled by clock signal clk _ R_1, produces three tunnel control signals; When pixel cell is even number line gating, EN_R_1, CLK_R_1 are low level, and pulse signal no longer transmits to the first d type flip flop D1.When pixel cell step by step gating time, transmission gate T3, T5, T7 conducting, transmission gate T4, T6, T8 end, three row gate control signal are sent by OUT_EN, OUT_SW, OUT_SEL respectively; When pixel cell odd-numbered line gating, transmission gate T5 conducting, transmission gate T3, T4, T6, T7, T8 end, three tunnel control signals respectively by C_EN1 port send into next stage basic row gating signal generation unit circuit C_EN2 port, directly to be exported by OUT_SW port at the corresponding levels and to be sent into the C_SEL2 port of upper level basic row gating signal generation unit circuit by C_SEL1 port; When pixel cell even number line gating, transmission gate T4, T6, T8 conducting, transmission gate T3, T5, T7 end, the signal sent into by the C_EN1 port of C_EN2 port accepts upper level basic row gating signal generation unit circuit, and exported by OUT_EN port, meanwhile, the signal sent into by the C_SEL1 port of C_SEL2 port accepts next stage basic row gating signal generation unit circuit, and exported by OUT_SEL port, export after OUT_SW port accepts high level.
Fig. 4 is the structural representation of the even number line basic row gating signal generation unit circuit of one embodiment of the invention.
As shown in Figure 4, each odd-numbered line basic row gating signal generation unit circuit comprise the 9th transmission gate T9, the tenth transmission gate T10, the second Sheffer stroke gate AN2, the 4th phase inverter N4, the 5th phase inverter N5, the second d type flip flop D2, quad latch L4, the 5th latch L5, the 6th latch L6, second and door A2, hex inverter N6, the 11 transmission gate T11, the 12 transmission gate T12, the 13 transmission gate T13, the 14 transmission gate T14, the 15 transmission gate T15 and the 16 transmission gate T16.
In each transmission gate aforesaid, each transmission gate comprises the first control end, the second control end, input end and output terminal.
First control end of the 9th transmission gate T9 is connected to the first control signal input end C_UP; Second control end of the 9th transmission gate T9 is connected to the second control signal input end C_UPB; The input end of the 9th transmission gate T9 is connected to downstream pulses signal input part IN_DOWN; The output terminal of the 9th transmission gate T9 is connected to the output terminal of the tenth transmission gate T10.
First control end of the tenth transmission gate T10 is connected to the second control signal input end C_UPB; Second control end of the tenth transmission gate T10 is connected to the first control signal input end C_UP; The input end of the tenth transmission gate T10 is connected to upstream bursts signal input part IN_UP; The output terminal of the tenth transmission gate T10 is connected to the output terminal of the 9th transmission gate T9 as mentioned before.
The output terminal of the 9th transmission gate T9 and the tenth transmission gate T10 is interconnected, and is connected to second input end of the second Sheffer stroke gate AN2, and the first input end of this second Sheffer stroke gate AN2 is connected to the enable input end EN_R_2 of odd-numbered line.The output terminal of the 9th transmission gate T9 and the tenth transmission gate T10 is also connected to the second input end DB of quad latch L4 and is connected to the first input end D of quad latch L4 by the 5th phase inverter N5.
The input end of clock CLK of the first latch is connected to aforesaid latch clock input end CLK_T; Second output terminal QB of the first latch is connected to the pulse signal output end OUT_TB of this odd-numbered line basic row gating signal generation unit circuit.
The output terminal of the second Sheffer stroke gate AN2 is connected to the first input end D of the second d type flip flop D2, and is connected to the second input end DB of this second d type flip flop D2 by the 4th phase inverter N4.
The clock signal input terminal CLK_R of the second d type flip flop D2 is connected to odd-numbered line input end of clock CLK_R_2; The first output terminal Q of the second d type flip flop D2 is connected to the first input end D of the 5th latch L5, and is connected to the first input end of second and door A2; The second output terminal QB of the second d type flip flop D2 is connected to the second input end DB of the 5th latch L5, and is connected to the input end of the 11 transmission gate T11.
The clock signal input terminal CLK of the 5th latch L5 is connected to odd-numbered line input end of clock CLK_R_2; The first output terminal Q of the 5th latch L5 is connected to the first input end D of the 6th latch L6, and is connected to the input end of the 7th transmission gate by the 3rd Sheffer stroke gate N3; The second output terminal QB of the 5th latch L5 is connected to the second input end DB of the 6th latch L6.
The clock signal input terminal CLK of the 6th latch L6 is connected to odd-numbered line input end of clock CLK_R_2; First output terminal of the 6th latch L6 is connected to second input end of second and door A2.
The output terminal of the 11 transmission gate T11 is connected to the output terminal of the 12 transmission gate T12, and is connected in the 3rd output signal end OUT_EN<n-1:0>; First control end of the 11 transmission gate T11 is connected to control data input end IN<1>; Second control end of the 11 transmission gate T11 is connected to control data input end IN<2>; The input end of the 11 transmission gate T11 is connected to first module enable signal output terminal C_EN1.
First control end of the 12 transmission gate T12 is connected to control data input end IN<3>; Second control end of the 12 transmission gate T12 is connected to control data input end IN<4>; The input end of the 12 transmission gate T12 is connected to second unit enable signal input end C_EN2.
Second is connected to the input end of the 13 transmission gate T13 with the output terminal of door A2; The output terminal of the 13 transmission gate T13 is connected to one in the second output signal end OUT_SW<n-1:0>, and is connected to the output terminal of the 14 transmission gate T14; First control end of the 13 transmission gate T13 is connected to control data input end IN<5>; Second control end of the 13 transmission gate T13 is connected to control data input end IN<6>.
First control end of the 14 transmission gate T14 is connected to control data input end IN<6>; Second control end of the 14 transmission gate T14 is connected to control data input end IN<5>; The input end of the 14 transmission gate T14 is connected to system power supply VDD.
The output terminal of the 15 transmission gate T15 is connected to the output terminal of the 16 transmission gate T16, and is connected in the first output signal end OUT_SEL<n-1:0>; First control end of the 15 transmission gate T15 is connected to control data input end IN<7>; Second control end of the 15 transmission gate T15 is connected to control data input end IN<8>; The input end of the 15 transmission gate T15 is connected to first module and selects signal output part C_SEL1.
First control end of the 16 transmission gate T16 is connected to control data input end IN<8>; Second control end of the 16 transmission gate T16 is connected to control data input end IN<7>; The input end of the 16 transmission gate T16 is connected to second unit and selects signal input part C_SEL2.
In embodiment shown in Fig. 4, quad latch L4 is Low level effective, and the 5th latch L5 is that high level is effective.When pixel cell from top to bottom gating time, pulse signal direction of transfer is from top to bottom, and C_UP is low level, C_UPB is high level, transmission gate T9 conducting, transmission gate T10 ends, and pulse signal sends into basic row gating signal generation unit circuit at the corresponding levels by IN_DOWN port; When pixel cell from bottom to top gating time, pulse signal direction of transfer is from bottom to top, and C_UP is high level, C_UPB is low level, transmission gate T9 ends, transmission gate T10 conducting, and pulse signal sends into basic row gating signal generation unit circuit at the corresponding levels by IN_UP port.Pulse signal is sent to quad latch L4 and is controlled by signal CLK_T, is delivered to next stage basic row gating signal generation unit circuit, pulse signal is transmitted step by step.When pixel cell step by step gating or even number line gating time, EN_R_2 is high level, and pulse signal is sent into the 5th latch L5 of the second d type flip flop D2 and serial connection and the 6th latch L6 and controlled by clock signal clk _ R_2, produces three tunnel control signals; When pixel cell is odd-numbered line gating, EN_R_2, CLK_R_2 are low level, and pulse signal no longer transmits to the second d type flip flop D2.When pixel cell step by step gating time, transmission gate T11, T13, T15 conducting, transmission gate T12, T14, T16 end, three row gate control signal are sent by OUT_EN, OUT_SW, OUT_SEL respectively; When pixel cell even number line gating, transmission gate T13 conducting, transmission gate T11, T12, T14, T15, T16 end, three tunnel control signals respectively by C_EN1 port send into next stage basic row gating signal generation unit circuit C_EN2 port, directly to be exported by OUT_SW port at the corresponding levels and to be sent into the C_SEL2 port of upper level basic row gating signal generation unit circuit by C_SEL1 port; When pixel cell odd-numbered line gating, transmission gate T12, T14, T16 conducting, transmission gate T11, T13, T15 end, the signal sent into by the C_EN1 port of C_EN2 port accepts upper level basic row gating signal generation unit circuit, and exported by OUT_EN port, meanwhile, the signal sent into by the C_SEL1 port of C_SEL2 port accepts next stage basic row gating signal generation unit circuit, and exported by OUT_SEL port, export after OUT_SW port accepts high level.
In the aforesaid embodiment of the present invention, the odd-numbered line that row gating signal produces integrated circuit adopts enable signal EN_R_1 with EN_R_2 be separated, clock signal clk _ R_1 and CLK_R_2 be separated with even number line, and output signal is carried out combination and can be realized pixel cell inter-bank gating by the signal be separated by these.Use unified latch clock control signal CLK_T, realize pulse signal and transmit step by step, make Signal transmissions accurate, simple and direct, stable, logical relation is tight.
Fig. 5 be in the present invention pixel cell line by line from top to bottom gating time corresponding row gating signal sequential chart, now, each basic row gating signal generation unit circuit produces three row gating signals, and these three row gating signals correspondences control one-row pixels gatings.Article two, be in strobe state for this row pixel between dotted line, OUT_SW<k> is low level, OUT_EN<k>, OUT_SEL<k> are high level, pixel cell gating from top to bottom line by line, wherein k is integer, 0≤k≤n-1.
Fig. 6 be in the present invention pixel cell line by line from bottom to top gating time corresponding row gating signal sequential chart, now, each basic row gating signal generation unit circuit produces three row gating signals, and these three row gating signals correspondences control one-row pixels gatings.Article two, be in strobe state for this row pixel between dotted line, OUT_SW<k> is low level, OUT_EN<k>, OUT_SEL<k> are high level, pixel cell gating from bottom to top line by line, wherein k is integer, 0≤k≤n-1.
Fig. 7 be in the present invention pixel cell even number line from top to bottom gating time corresponding row gating signal sequential chart, now, each pulse signal IN_DOWN is by after the latch effect of d type flip flop and serial connection, generate three tunnel control signals, i.e. C_EN1, OUT_SW, C_SEL1, C_EN1 sends into the C_EN2 port of next stage basic row gating signal generation unit circuit, and export as the OUT_EN<k+1> signal of next stage, C_SEL1 sends into the C_SEL2 port of upper level basic row gating signal generation unit circuit, and export as the OUT_SEL<k-1> signal of upper level, OUT_SW<k> is exported by basic row gating signal generation unit circuit at the corresponding levels, OUT_SEL<k-1>, OUT_SW<k>, these three row gating signal correspondences of OUT_EN<k+1> control row k pixel gating, wherein k is integer, 0≤k≤n-2, distinguishingly, by SEL0 for the 0th row pixel cell, OUT_SW<0>, these three row gating signals of OUT_EN<1> control gating.Article two, be in strobe state for corresponding row k pixel between dotted line, OUT_SW<k> is low level, OUT_EN<k+1>, OUT_SEL<k-1> is high level, according to pixel cell structure, by OUT_SEL<k-1>, OUT_SW<k>, OUT_EN<k+1> has combined the gating of pixel cell even number line, realize pixel cell even number line gating from top to bottom.
Fig. 8 be in the present invention pixel cell even number line from bottom to top gating time corresponding row gating signal sequential chart, now, each pulse signal IN_UP is by after the latch effect of d type flip flop and serial connection, generate three tunnel control signals, i.e. C_EN1, OUT_SW, C_SEL1, C_EN1 sends into the C_EN2 port of next stage basic row gating signal generation unit circuit, and export as the OUT_EN<k+1> signal of next stage, C_SEL1 sends into the C_SEL2 port of upper level basic row gating signal generation unit circuit, and export as the OUT_SEL<k-1> signal of upper level, OUT_SW<k> is exported by basic row gating signal generation unit circuit at the corresponding levels.These three row gating signal correspondences of OUT_SEL<k+1>, OUT_SW<k>, OUT_EN<k-1> control row k pixel gating, wherein k is integer, 0≤k≤n-2, distinguishingly, be control gatings by these three row gating signals of OUT_SEL<1>, OUT_SW<0>, EN0 for the 0th row pixel cell.Article two, be in strobe state for corresponding row k pixel between dotted line, OUT_SW<k> is low level, and OUT_EN<k-1>, OUT_SEL<k+1> are high level.According to pixel cell structure, combined the gating of pixel cell even number line by OUT_SEL<k+1>, OUT_SW<k>, OUT_EN<k-1>, realize pixel cell even number line gating from bottom to top.
Fig. 9 be in the present invention pixel cell odd-numbered line from top to bottom gating time corresponding row gating signal sequential chart, now, each pulse signal IN_DOWN is by after the latch effect of d type flip flop and serial connection, generate three tunnel control signals, i.e. C_EN1, OUT_SW, C_SEL1, C_EN1 sends into the C_EN2 port of next stage basic row gating signal generation unit circuit, and export as the OUT_EN<k+1> signal of next stage, C_SEL1 sends into the C_SEL2 port of upper level basic row gating signal generation unit circuit, and export as the OUT_SEL<k-1> signal of upper level, OUT_SW<k> is exported by basic row gating signal generation unit circuit at the corresponding levels.These three row gating signal correspondences of OUT_SEL<k-1>, OUT_SW<k>, OUT_EN<k+1> control row k pixel gating, wherein k is integer, 0≤k≤n-1, distinguishingly, be control gatings by these three row gating signals of OUT_SEL<n-2>, OUT_SW<n-1>, EN1 for the (n-1)th row pixel cell.Article two, be in strobe state for corresponding row k pixel between dotted line, OUT_SW<k> is low level, OUT_EN<k+1>, OUT_SEL<k-1> is high level, according to pixel cell structure, by OUT_SEL<k-1>, OUT_SW<k>, OUT_EN<k+1> has combined the gating of pixel cell odd-numbered line, realize pixel cell odd-numbered line gating from top to bottom.
Figure 10 be in the present invention pixel cell odd-numbered line from bottom to top gating time corresponding row gating signal sequential chart, now, each pulse signal IN_UP is by after the latch effect of d type flip flop and serial connection, generate three tunnel control signals, i.e. C_EN1, OUT_SW, C_SEL1, C_EN1 sends into the C_EN2 port of next stage basic row gating signal generation unit circuit, and export as the OUT_EN<k+1> signal of next stage, C_SEL1 sends into the C_SEL2 port of upper level basic row gating signal generation unit circuit, and export as the OUT_SEL<k-1> signal of upper level, OUT_SW<k> is exported by basic row gating signal generation unit circuit at the corresponding levels.These three row gating signal correspondences of OUT_SEL<k+1>, OUT_SW<k>, OUT_EN<k-1> control row k pixel gating, wherein k is integer, 0≤k≤n-1, distinguishingly, be control gatings by these three row gating signals of SEL1, OUT_SW<n-1>, OUT_EN<n-2> for the (n-1)th row pixel cell.Article two, be in strobe state for corresponding row k pixel between dotted line, OUT_SW<k> is low level, OUT_EN<k-1>, OUT_SEL<k+1> is high level, according to pixel cell structure, by OUT_SEL<k+1>, OUT_SW<k>, OUT_EN<k-1> has combined the gating of pixel cell odd-numbered line, realize pixel cell odd-numbered line gating from bottom to top.
The row strobe generation circuit tool of embodiments of the invention has the following advantages.
(1) the generation circuit of row gating signal can realize six kinds of gated mode of pixel cell in infrared focal plane array, and circuit structure is simple, very easy to the control of circuit itself, and the row gating signal that circuit produces is accurate, stable.
(2) corresponding row gating signal can be produced by the control signal in setting basic row gating signal generation unit circuit, realize pixel cell in infrared focal plane array gating, line by line gating, odd-numbered line gating, odd-numbered line gating, even number line gating from top to bottom from bottom to top from top to bottom from bottom to top from top to bottom line by line, and even number line these six kinds of pixel gated mode of gating from bottom to top.
(3) the row strobe generation circuit of odd-numbered line and even number line level can be linked togather, not need independent design, separately layout, improve the integrated level of integrated circuit.
(4) output signal of row strobe generation circuit can meet pixel cell inter-bank gating in infrared focal plane array, achieves the rapid scanning to infrared focal plane array, thus improves frame frequency, saves time.
Described the present invention by specific embodiment above, but the present invention is not limited to these specific embodiments.It will be understood by those skilled in the art that and can also make various amendment, equivalent replacement, change etc. to the present invention, as long as these conversion do not deviate from spirit of the present invention, all should within protection scope of the present invention.In addition, " embodiment " described in above many places represents different embodiments, can certainly by its all or part of combination in one embodiment.
Claims (5)
1. a row strobe generation circuit for infrared focal plane array sensing circuit, is characterized in that, comprising:
The basic row gating signal generation unit circuit of multiple mutual cascade, the basic row gating signal generation unit circuit of described multiple mutual cascade comprises odd-numbered line basic row gating signal generation unit circuit and even number line basic row gating signal generation unit circuit; Wherein:
The input end of each described odd-numbered line basic row gating signal generation unit circuit is connected respectively to the downstream pulses signal input part (IN_DOWN) of described row strobe generation circuit, upstream bursts signal input part (IN_UP), control data input end (IN<8:0>), first control signal input end (C_UP), second control signal input end (C_UPB), odd-numbered line input end of clock (CLK_R_1) and the enable input end of odd-numbered line (EN_R_1),
The input end of each described even number line basic row gating signal generation unit circuit is connected respectively to the described downstream pulses signal input part (IN_DOWN) of described row strobe generation circuit, described upstream bursts signal input part (IN_UP), described control data input end (IN<8:0>), described first control signal input end (C_UP), described second control signal input end (C_UPB), even number line input end of clock (CLK_R_2) and the enable input end of even number line (EN_R_2).
2. row strobe generation circuit as claimed in claim 1, is characterized in that:
Each basic row gating signal generation unit circuit in the basic row gating signal generation unit circuit of described multiple mutual cascade also comprises first module enable signal output terminal (C_EN1), first module selects signal output part (C_SEL1), second unit enable signal input end (C_EN2) and second unit to select signal input part (C_SEL2), wherein
The first module enable signal output terminal (C_EN1) of each basic row gating signal generation unit circuit is connected to the second unit enable signal input end (C_EN2) of connected next basic row gating signal generation unit, and the second unit that the first module of each basic row gating signal generation unit circuit selects signal output part (C_SEL1) to be connected to a connected upper basic row gating signal generation unit circuit selects signal input part (C_SEL2).
3. row strobe generation circuit as claimed in claim 1, is characterized in that:
Each basic row gating signal generation unit circuit in the basic row gating signal generation unit circuit of described multiple mutual cascade also comprises pulse signal output end (OUT_TB), the pulse signal output end (OUT_TB) of each basic row gating signal generation unit circuit is connected to the downstream pulses signal input part (IN_DOWN) of connected next basic row gating signal generation unit circuit, and is connected to the upstream bursts signal input part (IN_UP) of a connected upper basic row gating signal generation unit circuit.
4. row strobe generation circuit as claimed in claim 3, is characterized in that:
Each described odd-numbered line basic row gating signal generation unit circuit comprises the first transmission gate (T1), the second transmission gate (T2), the first Sheffer stroke gate (AN1), the first phase inverter (N1), the second phase inverter (N2), the first d type flip flop (D1), the first latch (L1), the second latch (L2) and the 3rd latch (L3);
First control end of described first transmission gate (T1) is connected to described first control signal input end (C_UP); Second control end of described first transmission gate (T1) is connected to described second control signal input end (C_UPB); The input end of described first transmission gate (T1) is connected to described downstream pulses signal input part (IN_DOWN); The output terminal of described first transmission gate (T1) is connected to the output terminal of described second transmission gate (T2);
First control end of described second transmission gate (T2) is connected to described second control signal input end (C_UPB); Second control end of described second transmission gate (T2) is connected to described first control signal input end (C_UP); The input end of described second transmission gate (T2) is connected to described upstream bursts signal input part (IN_UP);
Be connected to the second input end of the first Sheffer stroke gate (AN1) described in the output terminal of described first transmission gate (T1) and described second transmission gate (T2), the first input end of described first Sheffer stroke gate (AN1) is connected to the enable input end of described odd-numbered line (EN_R_1); The output terminal of described first transmission gate (T1) and described second transmission gate (T2) is also connected to second input end (DB) of described first latch (L1) and passes through the first input end (D) that described second phase inverter (N2) is connected to described first latch (L1);
Second output terminal (QB) of described first latch (L1) is connected to the pulse signal output end (OUT_TB) of current odd capable basic row gating signal generation unit circuit;
The output terminal of described first Sheffer stroke gate (AN1) is connected to the first input end (D) of described first d type flip flop (D1), and is connected to second input end (DB) of described first d type flip flop (D1) by described first phase inverter (N1);
The clock signal input terminal (CLK_R) of described first d type flip flop (D1) is connected to described odd-numbered line input end of clock (CLK_R_1); First output terminal (Q) of described first d type flip flop (D1) is connected to the first input end (D) of described second latch (L2); Second output terminal (QB) of described first d type flip flop (D1) is connected to second input end (DB) of described second latch (L2);
The clock signal input terminal (CLK) of described second latch (L2) is connected to described odd-numbered line input end of clock (CLK_R_1); First output terminal (Q) of described second latch (L2) is connected to the first input end (D) of described 3rd latch (L3); Second output terminal (QB) of described second latch (L2) is connected to second input end (DB) of described 3rd latch (L3);
The clock signal input terminal (CLK) of described 3rd latch (L3) is connected to described odd-numbered line input end of clock (CLK_R_1).
5. row strobe generation circuit as claimed in claim 3, is characterized in that:
Each described even number line basic row gating signal generation unit circuit comprises the 9th transmission gate (T9), the tenth transmission gate (T10), the second Sheffer stroke gate (AN2), the 4th phase inverter (N4), the 5th phase inverter (N5), the second d type flip flop (D2), quad latch (L4), the 5th latch (L5) and the 6th latch (L6);
First control end of described 9th transmission gate (T9) is connected to described first control signal input end (C_UP); Second control end of described 9th transmission gate (T9) is connected to described second control signal input end (C_UPB); The input end of described 9th transmission gate (T9) is connected to described downstream pulses signal input part (IN_DOWN); The output terminal of described 9th transmission gate (T9) is connected to the output terminal of described tenth transmission gate (T10);
First control end of described tenth transmission gate (T10) is connected to described second control signal input end (C_UPB); Second control end of described tenth transmission gate (T10) is connected to described first control signal input end (C_UP); The input end of described tenth transmission gate (T10) is connected to described upstream bursts signal input part (IN_UP);
Be connected to the second input end of the second Sheffer stroke gate (AN2) described in the output terminal of described 9th transmission gate (T9) and described tenth transmission gate (T10), the first input end of described second Sheffer stroke gate (AN2) is connected to the enable input end of described even number line (EN_R_1); The output terminal of described 9th transmission gate (T9) and described tenth transmission gate (T10) is also connected to second input end (DB) of described quad latch (L4) and passes through the first input end (D) that described 5th phase inverter (N5) is connected to described quad latch (L4);
Second output terminal (QB) of described quad latch (L4) is connected to the pulse signal output end (OUT_TB) of current even number line basic row gating signal generation unit circuit;
The output terminal of described second Sheffer stroke gate (AN2) is connected to the first input end (D) of described second d type flip flop (D2), and is connected to second input end (DB) of described second d type flip flop (D2) by described 4th phase inverter (N4);
The clock signal input terminal (CLK_R) of described second d type flip flop (D2) is connected to described even number line input end of clock (CLK_R_2); First output terminal (Q) of described second d type flip flop (D2) is connected to the first input end (D) of described 5th latch (L5); Second output terminal (QB) of described second d type flip flop (D2) is connected to second input end (DB) of described 5th latch (L5);
The clock signal input terminal (CLK) of described 5th latch (L5) is connected to described even number line input end of clock (CLK_R_2); First output terminal (Q) of described 5th latch (L5) is connected to the first input end (D) of described 6th latch (L6); Second output terminal (QB) of described 5th latch (L5) is connected to second input end (DB) of described 6th latch (L6);
The clock signal input terminal (CLK) of described 6th latch (L6) is connected to described even number line input end of clock (CLK_R_2).
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| CN103795413B (en) * | 2014-01-27 | 2017-04-12 | 无锡艾立德智能科技有限公司 | Infrared focal plane array reading circuit |
| CN110138376B (en) * | 2019-05-21 | 2023-02-24 | 电子科技大学 | Bad row protection circuit applied to uncooled infrared focal plane reading circuit |
| CN110530528A (en) * | 2019-08-20 | 2019-12-03 | 北京安酷智芯科技有限公司 | A kind of pixel circuit and its row choosing method, row select logic circuit |
| CN110530527B (en) * | 2019-08-20 | 2021-08-31 | 北京安酷智芯科技有限公司 | Pixel circuit, row selection method thereof and row selection logic circuit |
| CN112799465A (en) * | 2019-10-28 | 2021-05-14 | 京东方科技集团股份有限公司 | Control signal generator and driving method thereof |
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| CN101009762A (en) * | 2007-01-26 | 2007-08-01 | 东南大学 | Read-out circuit of infrared focal plane |
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