Summary of the invention
It is an object of the invention to, for the problems overcoming prior art to exist, the invention provides one and be applicable to
The arrow of sounding rocket carries image acquisition and compression method and system.To achieve these goals, the invention provides one
Plant arrow load image acquisition and the compressibility being applicable to sounding rocket, it is characterised in that described system comprises:
Arrow carries simulation photographic head 2, is used for obtaining image and producing analog picture signal;
Image/video decoding unit 3, for carrying the analog picture signal number that simulation photographic head 2 obtains by described arrow
Word, output data image is to image compression unit;
Image compression unit 4, for carrying out wavelet transformation and compression by the view data after digitized;
Central control unit 5, is used for controlling described image compression unit and image/video decoding unit and carries mould at multiple arrows
Intend completing between photographic head 2 switching, be used for image/video decoding unit 3, the initialization of image compression unit 4,
And use interrupt mode to read the compression data that image compression unit 4 obtains, the compression data of acquisition are packed
Process and output;
Power management module 1, provides power supply for each module in whole system;With
Data for receiving the data of central control unit output, and are buffered and data by data transmission unit 6,
Parallel bus data is converted into synchronization 422 bus datas.
In technique scheme, described system also comprises watchdog unit 7, for supervising the software of whole system
Control, prevents software race and flies.
In technique scheme, described arrow carries simulation photographic head and uses the simulation photographic head of low-power consumption.
In technique scheme, described image processing board each unit module all uses the design of technical grade chip to realize.
In technique scheme, described power management module comprises further: Power convert submodule, for complete
Become 5V voltage to the conversion between 1.2V, 1.8V, 2.5V and 3.3V voltage, by some electricity of Linear company
Source chip is constituted;With
Power supply conveying submodule, for above-mentioned power supply is delivered to image/video decoding unit, central control unit,
Data transmission unit and watchdog unit.
In technique scheme, described image compression unit uses wavelet compression to process chip, this chip and central authorities
Control unit is connected with address bus through data/address bus.
In technique scheme, described central control unit uses LPC2214 based on ARM7TDMI-S kernel.
In technique scheme, described central control unit 5 passes through I2C bus is to described image/video decoding unit 3
It is controlled.
In technique scheme, described synchronization 422 data/address bus is made up of data wire, clock line and data active line,
Every holding wire all uses differential transfer mode, and the data signal of described data active line carrying is along with clock letter
The clock signal of number line carrying, synchronization be sent to circuit system, the rising edge corresponding data hopping edge of clock signal,
Valid data signal shows that the data signal that it is corresponding when high level is valid data, valid data signal low level
Time corresponding data signal be invalid number.
In technique scheme, described switching photographic head concretely comprises the following steps: the every field picture of described image compression unit
Process produces a field after completing and processes interrupt signal, and every two field picture forms a two field picture, and described central authorities control single
After unit count down to two field interrupt signals, pass through I2C bus sends control instruction to described image/video decoding unit,
This image/video decoding unit carries out passage switching, and the data of next photographic head are carried out video decoding operation.
Present invention also offers a kind of arrow being applicable to sounding rocket based on said system and carry image acquisition and compression side
Method, the method comprises based on the system described in claim 1, described method:
Image compression unit 4 is controlled by central control unit 5 in real time, it is ensured that image compression unit 4 constant
Bit stream exports, and the most also according to predetermined format, the compression data inputting this central control unit is carried out packing process,
By the data after packing by data bus transmission to data transmission unit 6, complete the reception of compressed images data with
Send, the compressing image data conversion that data transmission unit 6 will obtain from central control unit 5 according to interface protocol
Becoming to synchronize 422 bus datas to be transmitted, feeding-dog signal is also sent to house dog by data transmission unit 6, wherein,
Feeding-dog signal is upset each second square-wave signal once.
It is an advantage of the current invention that:
The chip that the present invention uses is all the components and parts of low-power consumption, and the power consumption that image processing board runs is less than 3W, single
The power consumption of simulation photographic head is less than 1W, and compared with other designs, system power dissipation is substantially reduced;
Present invention employs ARM7 as central control unit, use FPGA as the core unit of data transmission unit
Part, has given full play to the advantage of the two, and has made it organically combine, with other independent FPGA and also in FPGA
The design embedding control kernel compares, and significantly reduces system design complexity, is beneficial to the realization of its space application;
Present invention employs the components and parts of technical grade, on the premise of meeting sounding rocket detection and working environment, have
Effect reduces cost, is beneficial to it and extensively applies;
The technical grade components and parts operating temperature that the present invention uses can reach-25 DEG C~+85 DEG C, has splendid temperature
Adaptability, compared with commercial image collecting device, the reliability that the system that improves is applied on sounding rocket;
The present invention uses 3 arrows to carry photographic head (quantity can be 1~4), and under the control of central controller
The plurality of photographic head has the function switched in turn, expands systematic difference scope, enhances it at sounding fire
The suitability on arrow;
The system of the present invention has the uniqueness at this of uniqueness refer to not find to synchronize in other picture system
422 buses, other picture system many employings Ethernet interface, USB interface, I2C interface, or asynchronous 232 connect
Mouthful.The advantage synchronizing 422 interfaces is on the premise of meeting message transmission rate, simplifies interface transmission protocols;
Due to the programmable features of FPGA and ARM in the system of the present invention, easily facilitate system hardware upgrading in the future
And extension.
In a word, the technical grade device that use cost of the present invention is relatively low replaces expensive space flight level device, reduction system
System complexity, reduces power consumption, designs and meets image acquisition and the compressibility that sounding rocket flight test requires,
This systematic function is reliable, has the function switching multiple photographic head and being compressed, can realize space multiple image
Continuously acquire and transmit.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples
The present invention is described in further details.
The object of the present invention is achieved like this:
The sounding rocket image acquisition that the present invention provides includes with compressibility:
Power management module 1, is provided power supply for each module in whole system, is converted by DC-DC, output 3.3V,
The voltage of 2.5V, 1.8V, 1.2V, powers to other unit modules;
Arrow carries simulation photographic head 2, is used for obtaining image and producing analog picture signal;
Image/video decoding unit 3, for the view data digitized by simulation photographic head, exports 8 bit image numbers
According to image compression unit;
Image compression unit 4, for carrying out wavelet transformation and compression by the view data after digitized;
Central control unit 5, for being controlled image compression unit, image/video decoding unit, takes the photograph multiple
As completing switching between head, gather view data and carry out packing transmission;
Data transmission unit 6, has been used for buffering and the transmission of view data, is converted into by parallel bus data same
Walk 422 bus datas;
Watchdog unit 7, for being monitored the software of whole system, once occurs that software runs and flies, house dog is single
Whole system is resetted by unit.
Image/video decoding unit, image compression unit, central control unit, data transmission unit, house dog list
Unit constitutes image processing board.
In above-mentioned technical scheme, power management module 1 had 5V voltage to 1.2V, 1.8V, 2.5V,
The function of the voltage transformation of 3.3V;
In above-mentioned technical scheme, described image decoding unit uses a kind of video decoding chip, and it is to input
4 road analog video signals change, input can be 4 road CVBS or 2 road S-video (Y/C) signals,
Export 8 VPO buses, for ITU656, YUV4:2:2 form of standard.Image decoding unit compatibility PAL, NTSC
Multiple types, internal depositor can be used to the brightness to image, colourity is controlled, and the read-write of depositor is led to
Cross I2C bus is carried out.
In above-mentioned technical scheme, image compression unit is the monolithic Real Time Compression coding and decoding video of a kind of low-power consumption
Chip, can be used for video signal and processes, have accurate rate control.
In above-mentioned technical scheme, but central control unit is the CPU that a kind of low-profile performance is high, components and parts
Power consumption and price the most relatively low.
In above-mentioned technical scheme, data transmission unit is the technical grade FPGA of a kind of Xilinx company, this
FPGA has the feature of low-power consumption, low cost, has the electrical interface of fast and flexible.As it is shown in figure 1, this figure is this
The a kind of of invention offer is applicable to sounding rocket, the image acquisition of micro-gravity rocket and the composition frame chart of compressibility,
Described system is carried simulation photographic head 2, image/video decoding unit 3, compression of images list by power management module 1, arrow
Unit 4, central control unit 5, data transmission unit 6 and watchdog unit 7 form;Wherein, the enforcement of the present invention
Example uses ARM7 as central control unit, has been used for image/video decoding unit 3, image compression unit 4
Initialize, and use interrupt mode to read the compression data that image compression unit 4 obtains, by central control unit 5
The brightness of 4, colourity, the depositor such as coefficient of compressibility in configuration image compression unit, produce chip selection signal and reading,
Write enable signal.In image compression process, image compression unit 4 is controlled by central control unit 5 in real time,
Ensure the constant bit stream output of image compression unit 4, the most also to the compression data inputting this central control unit
Packing process is carried out according to predetermined format, by the data after packing by data bus transmission to data transmission unit 6,
Completing reception and the transmission of compressed images data, data transmission unit 6 will control single according to interface protocol from central authorities
The compressing image data that unit 5 obtains is converted into synchronization 422 bus datas and is transmitted, and data transmission unit 6 also will
Feeding-dog signal is transferred to house dog by control signal wire, and wherein, feeding-dog signal is upset each second square wave once
Signal.
Described synchronization 422 data/address bus is made up of data wire, clock line and data active line, and every holding wire is all adopted
Use differential transfer mode, and the clock that the data signal of described data active line carrying carries along with clock cable
Signal, synchronization be sent to circuit system, the rising edge corresponding data hopping edge of clock signal, valid data signal table
Its data signal corresponding when high level bright is valid data, data letter corresponding during valid data signal low level
Number it it is invalid number.As shown in Figure 3.Power management module 1 uses the LT196 series of Linear company, this power supply
Management 1 supply voltage 5V of module, is converted in the voltage supply data transmission unit of 1.2V, 2.5V and 3.3V
Core parts FPGA.Outfan 2.5V and 3.3V of power management module 1 connects in the Vint(of FPGA respectively
Core voltage), Vcco (Bank voltage), GND end is the earth terminal of whole equipment.
Image/video decoding unit 3 uses the 3.3V power supply through supply module conversion, and this unit module uses
The technical grade chip SAF7113 of Philips company, it is decoded into " VPO " of standard the analog video signal of input
Digital signal.The analog picture signal of photographic head is by the analog video input pin phase of filter circuit with SAF7113
Even, the depositor of SAF7113 is passed through I by central control unit 52C bus configures, the RTS0 of SAF7113
Pin is not over 3.3K Europe resistive pull-downs to ground, now I2Reading, writing address under C bus protocol is 4BH respectively
And 4AH.SAF7113 has 256 internal registers, and wherein 00H is chip version information depositor: 01H~05H
It is front-end configuration status register, for arranging the duty of chip front end analogue signal processing channel, concrete root
Classification and form according to input analog video signal are configured;06H~13H, 15H~17H are the works of decoded portion
Making mode configuration register, wherein 12H depositor is used for arranging the function of RTS0, RTS1;1FH is read-only decoding
Status register, the various signal conditions during report decoding: 40H~60H, 60H~62H are the controls of row/field picture
System, status register, for arranging the data form etc. of VPO;14H, 18H~1EH, 20H~3FH and 63H~
FFH retains use.
Image compression unit 4 uses the image compression chip ADV612 based on wavelet transformation of Analog Device company
Have employed based on the compression algorithm of sub-band coding in double orthogonal basis wavelet transformation and frame with a piece of DRAM, ADV612, and
Having interframe compression function, compression ratio reaches as high as 7500:1 in theory.An external 256K is needed during ADV612 work
The DRAM of Byte and 60ns speed, ADV612 are internally embedded a DRAM manager, for carrying out ADV612
Pipeline stages buffers, and can support that ADV612 completes when previous field picture statistical value calculates.
Central control unit 5 uses the employing LPC2214 chip based on ARM7TDMI-S kernel of Philips company,
The high speed flash storage of built-in 256KB and the SRAM of 16KB, maximum clock frequency can reach 60MHz, from
Band external bus controller and I2C interface controller.LPC2214 is respectively by 32 bit data bus and I2C bus pair
ADV612 and SAF7113 is controlled, and also having joined 2 block sizes for LPC2214 owing to data volume is bigger is 4Mbits
Off-chip SRAM.
Data transmission unit 6 uses the XC3S200 of Xilinx company, and its technical grade product is in temperature characterisitic, speed
The demand of sounding rocket application is all met or exceeded in characteristic.Configuration is started, also in order to carry out program to XC3S200
Have selected program storage chip XCF02S.
As it is shown in figure 1, simulated image data is connected on the analog video input interface of SAF7113, SAF7113 pair
The analog video signal of input is decoded into " VPO " digital data transmission of standard to image compression chip.Analog video
Signal arrives after video acquisition module, be through anti-aliasing filter, 9-bitA/D conversion, automatic growth control, bright
Degree/contrast/saturation adjusts, and final coding becomes the form of standard ITU-R BT 656YUV 4:2:2, passes through
8 bit data bus are transferred to image compression unit.SAF7113 can input 4 road analog video signals, it is achieved 4 tunnels
The switching of video signal.Operationally, SAF7113 needs the crystal of external 24.576MHz, and inside has phaselocked loop
(LLC), the system clock of output 27MHz is to ADV612.ARM passes through I2The depositor of SAF7113 is entered by C bus
Row accesses and controls, and mainly completes the configuration of the depositors such as brightness, colourity, Synchronization Control, output control.
Central control unit 5 is connected with the respective pins of ADV612 by data/address bus, address bus, and by ADV612
Interrupt signal line be connected on the interrupt source pin of ARM, the interrupt signal in interrupt pin is configured to difference by ARM
Priority process.Central control unit is also by I2C bus is connected with image/video decoding unit, passes through
I2Its depositor is configured by C bus.After image processing board powers up, central control unit is first to picture decoding list
Unit SAF7113 and image compression unit ADV612 carry out initial configuration.
The data/address bus of SAF7113 is connected in the respective pins of ADV612, the VPO that SAF7113 is exported by ADV612
Data carry out wavelet compression and conversion, the data after compression are stored in the data buffering FIFO of chip internal, when
Data in FIFO reach the numerical value being pre-configured with, and trigger corresponding interrupt signal immediately, and ARM responds this interruption,
Reading the data in FIFO and remove interruption, during reading data, letter is also interrupted in the field of ADV612 by ARM
Number LCODE judges, once receives this interrupt signal and carries out quick-speed interruption process immediately.LCODE interrupts showing one
The end of field, the data obtained from ADV612 are carried out packing process and transmission by ARM.Every twice LCODE interrupts
Signal shows that the collection of a two field picture completes, and every two two field pictures, central control unit just passes through I2C bus marco figure
As decoding unit switches photographic head according to predefined procedure.ARM is to the interrupt processing process of ADV612 as shown in Figure 2.
The compression of view data is completed by the ADV612 chip of compression unit.ADV612 is mainly combined by wavelet filter
The distance of swimming/Huffman encodes two parts composition, and after small echo processes, signal can decompose 42 different subbands, every height
The corresponding RBW depositor of band, the quantization parameter that the input of each depositor real-time adaptive is suitable, then ADV612
Desired constant code stream can be obtained according to these quantization parameter re-quantization, coding.The quantization that ADV612 chip uses
Scheme is scalar quantization, and 42 subbands use different quantization systems according to them to the difference of original image importance
Number.According to the dependency between image every, system use this size variable to calculate the quantization of next
Coefficient.When realizing, the adoption rate integral calculus i.e. principle of PID regulator realizes.
Central control unit mainly completes following function: (1) system initialization, initial including operating system
Change and the initialization of SAF7113H and ADV612;(2) after obtaining the view data after compression, according to predetermined
Data form is packed, for different photographic head, different figure sequence numbers, the packing of bag sequence number.According to CCSDS
Standard, every 428 view data break into a bag, are transferred to FPGA by data/address bus and address bus.Beat
The data form of bag is as shown in table 1;(3) based on the quantization to ADV612 of proportional-integral-differential (PID) algorithm
Device is controlled so that it is the bit rate of output keeps constant;(4) control image capture module and carry out cutting of video camera
Change;(5) clockwise system interface module per second sends a feeding-dog signal.
Table 1 arrow carries image capture device data packet format
In order to meet reliability and the requirement of real-time of system, system transplantation real-time multi-task embedded OS
uC/OS-II.This system is used widely at world wide, including numerous areas, such as mobile phone, aircraft, instrument
Instruments and meters, armarium and Industry Control etc..That operating system version is selected is V2.52, and the system of this version exists
Within 2000, obtained NASA(The National Aeronautics and Space Administration) (FAA) to for commercial aircraft, meet RTCA DO-178B
The certification of standard, shows that uC/OS-II has enough safety and stabilities, may be used for aerospace equipment.
The flow chart of embedded software is as shown in Figure 2.After system electrification starts, first operating system can initialize,
Subsequently into task task 0, Task0 can perform a series of initialization function, including TargetInit (),
ADV612Init () and SAF7113Init (), these 3 functions are respectively intended to LPC2214, ADV612 and SAF7113H
Initialize.Initialization is just medium to be interrupted in task 0 after completing, and has 4 possible interruptions, wherein
Three external interrupt, respectively STATS_R interrupts, FIFO_SRQ interrupts and LCODE interrupts, and is all by ADV612
Produce;1 internal interrupt, is produced by intervalometer 0.
Can trigger STATS_R to interrupt when the statistical data in ADV612 is ready to, system responds has no progeny in this and can adjust
With interrupt service routine STATSR_Exception (), the content reading field sized registers gives PID as input
Controller, calculates and produces new quantization parameter RBW and BW, and be written to RBW and BW depositor, thus control
The compression data of ADV612 output constant bit rate.
When the data in the FIFO of ADV612 reach half-full, FIFO_SRQ can be triggered and interrupt.Interrupting service journey
In sequence FIFOSRQ_Exception (), 250 data fifos can be read continuously, and wrap according to CCSDS remote measurement source
Form pack after be sent to FPGA.
Triggered this to interrupt when last 32 bit data of a field data will read in FIFO, so this
Interrupt being only possible to occur in FIFO_SRQ interrupts, owing to selected LPC2214 does not support interrupt nesting, so
LCODE is interrupted being set to quick-speed interruption, and quick-speed interruption can interrupt regular interrupt.
UC/OS-II operating system needs to provide cyclical signal source, is used for realizing time delays and confirming time-out, this
System uses intervalometer 0 to be set to 50ms as timeticks source, timeticks, and namely every 50ms can trigger once
Intervalometer 0 interrupts.At intervalometer 0 interrupt service routine Timer0_Exception () inner meeting calling system function
OSTimeTick () to provide timeticks for whole operating system, and can enter the number of times entering intervalometer 0 interruption
Row counting, sends once hello Canis familiaris L. data when arriving 200 numbers.FPGA receives after feeding Canis familiaris L. data, feeds Canis familiaris L. by transmission
Signal is to watchdog unit.During image processing board works, ARM sent out once hello Canis familiaris L. data and gives every 1 second
FPGA, FPGA produce feeding-dog signal.If being spaced 1.6 seconds house dogs to can not receive feeding-dog signal, watchdog circuit will
Reset whole system.
Data through ARM packing are sent to FPGA by data/address bus, FPGA carry out the conversion of EBI,
Transform the data into into synchronization 422 bus data of agreement, produce corresponding clock signal, useful signal, data letter
Number it is sent to interface circuit.The clock signal of FPGA, useful signal, data signal output pin respectively with transmission
The TXD pin of chip is connected, and additionally has 32 pins to be connected with the data/address bus of ARM, and 10 pins are with ARM's
Address bus is connected, wherein data bus transmission compression data, and address bus gating is corresponding to be deposited for view data
Buffering FIFO of storage.
It should be noted that and understand, without departing from the spirit and scope of the present invention required by appended claims
In the case of, it is possible to the present invention of foregoing detailed description is made various modifications and improvements.It is therefore desirable to protection
The scope of technical scheme is not limited by given any specific exemplary teachings.