CN104679605B - A kind of soft hardened system of space flight based on commercial goods shelf productses - Google Patents
A kind of soft hardened system of space flight based on commercial goods shelf productses Download PDFInfo
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- CN104679605B CN104679605B CN201510082161.4A CN201510082161A CN104679605B CN 104679605 B CN104679605 B CN 104679605B CN 201510082161 A CN201510082161 A CN 201510082161A CN 104679605 B CN104679605 B CN 104679605B
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Abstract
A kind of soft hardened system of space flight based on commercial goods shelf productses, including fpga chip, dsp chip, the first watchdog chip and the second watchdog chip, wherein fpga chip includes image forwarding module, fpga chip monitoring module, and dsp chip includes image compression module, dsp chip monitoring module.Fpga chip, dsp chip mutual monitoring state while data interaction is carried out, when other side's working condition exception, initialization to square chip can be carried out by triggering watchdog chip, as long as problem asynchronously occurs for fpga chip, dsp chip, whole floppy disk system can independently recover normal operating conditions.The soft hardened system of the present invention can improve the reliability of commercial goods shelf productses, and a kind of preventive means is provided in AEROSPACE APPLICATION for commercial goods shelf productses, promotes use of the commercial goods shelf productses in space industry.
Description
Technical field
The present invention relates to a kind of reset system, the soft hardened system of particularly a kind of space flight based on commercial goods shelf productses.
Background technology
The device of AEROSPACE APPLICATION is mostly high-grade special chip and device at present, and with high costs is that such devices lack jointly
Point, the volume of high-grade device is several times of commercial goods shelf productses in addition, is not easy to the system integration, while device procurement cycle
The problems such as long, also greatly constrains the progress of project.Therefore the AEROSPACE APPLICATION of commercial goods shelf productses is just particularly important, but
It is the main restricting factor that reliability is commercial goods shelf productses AEROSPACE APPLICATION, therefore in face of aerospace level device cost, cycle
With the predicament of supply channel, it is that future development becomes that aerospace applications are carried out after commercial goods shelf productses are reinforced by technological means
Gesture.Under conditions of space environment is harsh, the AEROSPACE APPLICATION of commercial goods shelf productses just receives great restriction, using reinforcing hand
Duan Tigao system reliabilities need a kind of soft reinforcing suitable for commercial goods shelf productses into necessary condition to solve this problem
System improves commercial goods shelf productses applied to the reliability in space equipment.
Space application research of the China to commercial goods shelf productses at present is in the junior stage, and is begun with from 1999 less than 10
The AEROSPACE APPLICATION of money commercialization goods shelf productses, application of the external advanced country to the direction are in the all-round developing stage, but still
Prematurity.
The content of the invention
The technology of the present invention solves problem:Overcome in the prior art commercial goods shelf productses it is not high in AEROSPACE APPLICATION reliability
The defects of, it is proposed that it is capable of the soft hardened system of the space flight based on commercial goods shelf productses of automatic detection and reparation, business is greatly improved
With the space environment adaptability of goods shelf productses.
The present invention technical solution be:A kind of soft hardened system of space flight based on commercial goods shelf productses, including FPGA
Chip, dsp chip, the first watchdog chip, the second watchdog chip, wherein
Fpga chip, including image forwarding module and fpga chip monitoring module;Image forwarding module, receive camera
View data is sent to dsp chip after the view data of transmission, receives the compression that image compression module is sent in dsp chip
View data simultaneously exports;Fpga chip monitoring module, monitoring image forwarding module receive the sequential of transmission view data simultaneously
Judgement, if the sequential that image forwarding module receives transmission view data meets built-in FPGA reception transmission view data
Sequence, then produce and send DSP feed dog instruct into dsp chip dsp chip monitoring module, otherwise do not produce DSP feed dog refer to
Order;It is time that image forwarding module received and sent view data in fpga chip that the FPGA, which is received and sent view data sequential,
Sequence and time;When receiving FPGA hello the dog instructions that dsp chip monitoring module is sent in dsp chip, produce and feed dog triggering
Signal refers to the second watchdog chip when being not received by FPGA hello the dogs that dsp chip monitoring module is sent in dsp chip
When making, do not produce and feed dog trigger signal to the second watchdog chip;
Dsp chip, including image compression module and dsp chip monitoring module;Image compression module, receive FPGA cores
It is compressed after the view data that image forwarding module is sent in piece, and the view data of compression is sent in fpga chip
Image forwarding module;Dsp chip monitoring module, refer to when receiving DSP hello the dogs that monitoring module is sent in fpga chip
When making, produce and feed dog trigger signal to the first watchdog chip, when monitoring module transmission in no reception fpga chip
When DSP feeds dog instruction, do not produce and feed dog trigger signal to the first watchdog chip;Monitoring image compression module receives compression and hair
Send the sequential of view data and judgement, if image compression module receive compression and send view data sequential meet it is built-in
DSP receive compression and send view data sequential, then produce and send FPGA feed dog instruct to fpga chip, otherwise do not produce
FPGA feeds dog instruction;It is image compression module reception, compression and hair in dsp chip that the DSP, which is received and sent view data sequential,
Send order and the time of view data;
First watchdog chip, if receiving hello the dog trigger signal that monitoring module in dsp chip is sent, do not produce
Raw reset trigger signal, otherwise produce reset trigger signal control fpga chip initialization;
Second watchdog chip, if receiving hello the dog trigger signal that monitoring module in fpga chip is sent, no
Reset trigger signal is produced, otherwise produces reset trigger signal control dsp chip initialization.
The present invention compared with prior art the advantages of be:
(1) the soft hardened system of the present invention solves the problems, such as that commercial goods shelf productses reliability is low, simultaneously as commercial shelf
Product is mostly ripe technical grade chip or device, and cost is relatively low and small volume is easily integrated, and AEROSPACE APPLICATION is realized light smallization,
And reduce load and volume;
(2) the soft hardened system of the present invention makes it possible the AEROSPACE APPLICATION of commercial goods shelf productses by system means, shortens
The delivery cycle of AEROSPACE APPLICATION product;
(3) the soft hardened system of the present invention is realized that FPGA or DSP one of both normal works can by FPGA+DSP frameworks
Ensure the normal operation of floppy disk system, system operation reliability height.
Brief description of the drawings
Fig. 1 is a kind of soft hardened system principle framework figure of space flight based on commercial goods shelf productses.
Embodiment
The present invention will be further described below in conjunction with the accompanying drawings.
As shown in figure 1, a kind of soft hardened system of space flight based on commercial goods shelf productses, including fpga chip, dsp chip,
Fpga chip, the first watchdog chip, the second watchdog chip, wherein fpga chip include image forwarding module and fpga chip
Monitoring module.
Dsp chip includes image compression module and dsp chip monitoring module, and fpga chip is each only with dsp chip
Vertical operation, image forwarding module receive the view data that extraneous camera is sent, and view data is carried out subpackage processing transmit to
The image compression module of dsp chip, the image compression module of dsp chip are transferred to FPGA after raw image data is compressed
The image forwarding module of chip, image forwarding module again export the view data of compression;In fpga chip, image forwarding mould
The time sequence status of itself is fed back to fpga chip monitoring module, fpga chip state prison by block in real time in the process of running
This timing is received transmission view data sequential with the FPGA built in fpga chip monitoring module and contrasted by control module, when
When state meets to require, i.e., produced to dsp chip transmission and feed dog instruction, DSP monitoring modules produce hello dog trigger signal and given
First watchdog chip, the first watchdog chip do not produce reset trigger signal;Production is not sent then when state is unsatisfactory for requiring
Raw to feed dog instruction, DSP monitoring modules, which do not produce then, feeds dog trigger signal, and the first watchdog chip can then produce FPGA resets
Trigger signal resets FPGA, can now ensure the sequential stable operation of fpga chip.
The image compression module of dsp chip receives raw image data, carries out the compression of images of specific format, this compressed package
Include H.264 compression and JPEG compression, the image forwarding module that the data after compression are sent to FPGA after the completion of compression and carry out figure
As data output;In dsp chip, the sequential of image compression module operationally Real-time Feedback itself condensing routine is to DSP's
DSP built in this timing and DSP monitoring modules is received and is sent picture number by monitoring module, DSP monitoring modules
It is compared according to sequential, both sent to produce to fpga chip when state meets to require and feed dog instruction, fpga chip condition monitoring
Module produces hello dog trigger signal and gives the second watchdog chip, and the second watchdog chip does not produce reset trigger signal;Work as state
Not sending generation when being unsatisfactory for requiring then and feed dog instruction, fpga chip monitoring module, which does not produce then, feeds dog trigger signal, the
Two watchdog chips, which can then produce DSP reset trigger signals, resets DSP, can now ensure that the sequential of dsp chip is stable and transport
OK, wherein, it is that image forwarding module receives and sent view data in fpga chip that FPGA, which is received and sent view data sequential,
Order and time, it is that image compression module receives, compresses and sent image in dsp chip that DSP, which is received and sent view data sequential,
The order of data and time.
Claims (1)
1. the soft hardened system of a kind of space flight based on commercial goods shelf productses, it is characterised in that including fpga chip, dsp chip,
One watchdog chip, the second watchdog chip, wherein
Fpga chip, including image forwarding module and fpga chip monitoring module;Image forwarding module, receive camera and send
View data after view data is sent to dsp chip, receive the image of the compression that image compression module is sent in dsp chip
Data simultaneously export;Fpga chip monitoring module, monitoring image forwarding module receive the sequential for sending view data and judgement,
If the sequential that image forwarding module receives transmission view data meets built-in FPGA reception transmission view data sequential, produce
Give birth to and send DSP hello dogs and instruct into dsp chip dsp chip monitoring module, otherwise do not produce DSP and feed dog instruction;It is described
It is that image forwarding module receives in fpga chip and the order of transmission view data is timely that FPGA, which is received and sent view data sequential,
Between;When receiving FPGA hello the dog instructions that dsp chip monitoring module is sent in dsp chip, produce and feed dog trigger signal extremely
Second watchdog chip, when being not received by FPGA hello the dog instructions that dsp chip monitoring module is sent in dsp chip,
Do not produce and feed dog trigger signal to the second watchdog chip;
Dsp chip, including image compression module and dsp chip monitoring module;Image compression module, receive in fpga chip
It is compressed after the view data that image forwarding module is sent, and the view data of compression is sent to the image in fpga chip
Forwarding module;Dsp chip monitoring module, when receiving DSP hello the dog instructions that monitoring module is sent in fpga chip,
Produce and feed dog trigger signal to the first watchdog chip, when the DSP that monitoring module is sent in no reception fpga chip is fed
When dog instructs, do not produce and feed dog trigger signal to the first watchdog chip;Monitoring image compression module receives compression and sends figure
Sequential and judgement as data, if image compression module receives compression and the sequential of transmission view data meets built-in DSP
Receive compression and send view data sequential, then produce and send FPGA feed dog instruct to fpga chip, otherwise do not produce FPGA
Feed dog instruction;The DSP receive compression and send view data sequential be in dsp chip image compression module receive, compression and
Send order and the time of view data;
First watchdog chip, if receiving hello the dog trigger signal that monitoring module in dsp chip is sent, do not produce multiple
Position trigger signal, otherwise produce reset trigger signal control fpga chip initialization;
Second watchdog chip, if receiving hello the dog trigger signal that monitoring module in fpga chip is sent, do not produce
Reset trigger signal, otherwise produce reset trigger signal control dsp chip initialization.
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CN104679605B true CN104679605B (en) | 2018-03-09 |
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CN102186076A (en) * | 2011-04-29 | 2011-09-14 | 中国科学院光电技术研究所 | Image compression method and image compression device for real-time code rate pre-allocation |
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KR20120120767A (en) * | 2011-04-25 | 2012-11-02 | 국방과학연구소 | Co-design method and apparatus using DSP and FPGA for JPEG2000 Video Compression |
CN202661570U (en) * | 2012-06-28 | 2013-01-09 | 华南理工大学 | Power distribution network power quality integrated monitor based on double DSPs (Digital Signal Processor) |
CN103517081A (en) * | 2012-06-26 | 2014-01-15 | 中国科学院空间科学与应用研究中心 | Rocket-borne image acquisition and compression system suitable for sounding rocket |
CN103853626A (en) * | 2012-12-07 | 2014-06-11 | 深圳航天东方红海特卫星有限公司 | Duplex redundant backup bus communication method and device for satellite-borne electronic equipment |
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2015
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Patent Citations (6)
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KR20120120767A (en) * | 2011-04-25 | 2012-11-02 | 국방과학연구소 | Co-design method and apparatus using DSP and FPGA for JPEG2000 Video Compression |
CN102186076A (en) * | 2011-04-29 | 2011-09-14 | 中国科学院光电技术研究所 | Image compression method and image compression device for real-time code rate pre-allocation |
CN102708012A (en) * | 2012-04-23 | 2012-10-03 | 航天恒星科技有限公司 | Parallel-processing dual fault-tolerant on-satellite processing system |
CN103517081A (en) * | 2012-06-26 | 2014-01-15 | 中国科学院空间科学与应用研究中心 | Rocket-borne image acquisition and compression system suitable for sounding rocket |
CN202661570U (en) * | 2012-06-28 | 2013-01-09 | 华南理工大学 | Power distribution network power quality integrated monitor based on double DSPs (Digital Signal Processor) |
CN103853626A (en) * | 2012-12-07 | 2014-06-11 | 深圳航天东方红海特卫星有限公司 | Duplex redundant backup bus communication method and device for satellite-borne electronic equipment |
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