CN103515450B - 一种沟槽电荷补偿肖特基半导体装置及其制造方法 - Google Patents
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- 125000004429 atom Chemical group 0.000 description 1
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Abstract
本发明公开了一种沟槽电荷补偿肖特基半导体装置,其中具有电荷补偿结构,当半导体装置接一定的反向偏压时,第一导电半导体材料与第二导电半导体材料可以形成电荷补偿,提高器件的反向阻断特性;通过沟槽上部引入多晶半导体材料,可以降低半导体装置接反向偏压时肖特基结表面的峰值电场强度,从而进一步提高器件的反向阻断特性。本发明还提供了一种沟槽电荷补偿肖特基半导体装置的制造方法。
Description
技术领域
本发明涉及到一种沟槽电荷补偿肖特基半导体装置,本发明还涉及一种沟槽电荷补偿肖特基半导体装置的制造方法。本发明的半导体装置是制造功率整流器件的基本结构。
背景技术
功率半导体器件被大量使用在电源管理和电源应用上,特别涉及到肖特基结的半导体器件已成为器件发展的重要趋势,肖特基器件具有正向开启电压低开启关断速度快等优点,同时肖特基器件也具有反向漏电流大,不能被应用于高压环境等缺点。
肖特基二极管可以通过多种不同的布局技术制造,最常用的为平面布局,传统的平面肖特基二极管在漂移区具有突变的电场分布曲线,影响了器件的反向击穿特性,同时传统的平面肖特基二极管具有较高的导通电阻。
发明内容
本发明针对上述问题提出,提供一种沟槽电荷补偿肖特基半导体装置及其制造方法。
一种沟槽电荷补偿肖特基半导体装置,其特征在于:包括:衬底层,为半导体材料构成;漂移层,为第一导电半导体材料构成,位于衬底层之上;多个沟槽结构,沟槽位于漂移层中,漂移层中临靠沟槽内壁区域设置有第二导电半导体材料,沟槽内下部填充有绝缘材料,沟槽内上部填充半导体材料;肖特基势垒结,位于漂移层第一导电半导体材料上表面。
一种沟槽电荷补偿肖特基半导体装置的制造方法,其特征在于:包括如下步骤:在衬底层表面形成第一导电半导体材料层,然后表面形成绝缘材料层;进行光刻腐蚀工艺去除表面部分绝缘介质,然后刻蚀去除部分裸露半导体材料形成沟槽;在沟槽内进行第二导电杂质扩散;在沟槽内淀积绝缘材料,反刻蚀绝缘材料,淀积多晶半导体材料,反刻蚀多晶半导体材料,去除表面绝缘材料;淀积势垒金属,进行烧结形成肖特基势垒结。
当半导体装置接一定的反向偏压时,第一导电半导体材料与第二导电半导体材料可以形成电荷补偿,提高器件的反向击穿电压。因此也可以提高漂移区的杂质掺杂浓度,从而可以降低器件的正向导通电阻,改善器件的正向导通特性。
通过沟槽上部引入多晶半导体材料,可以改变肖特基表面电场分布,降低半导体装置接反向偏压时肖特基结表面的峰值电场强度,从而进一步提高器件的反向阻断特性。
附图说明
图1为本发明的一种沟槽电荷补偿肖特基半导体装置剖面示意图;
图2为本发明的一种沟槽电荷补偿肖特基半导体装置剖面示意图。
其中,
1、衬底层;
2、二氧化硅;
3、第一导电半导体材料;
4、第二导电半导体材料;
5、肖特基势垒结;
6、氮化硅;
7、多晶第二导电半导体材料;
10、上表面金属层;
11、下表面金属层。
具体实施方式
实施例1
图1为本发明的一种沟槽电荷补偿肖特基半导体装置剖面图,下面结合图1详细说明本发明的半导体装置。
一种肖特基半导体装置,包括:衬底层1,为N导电类型半导体硅材料,磷原子的掺杂浓度为1E19/CM3,在衬底层1下表面,通过下表面金属层11引出电极;第一导电半导体材料3,位于衬底层1之上,为N传导类型的半导体硅材料,磷原子的掺杂浓度为1E16/CM3;第二导电半导体材料4,位于沟槽内壁附近,为P传导类型的半导体硅材料,硼原子的掺杂浓度为3E16/CM3;肖特基势垒结5,位于第一导电半导体材料3的表面,为半导体硅材料与势垒金属形成的硅化物;二氧化硅2,位于沟槽内下部;多晶第二导电半导体材料7,为高浓硼掺杂的多晶半导体硅材料,位于沟槽内上部;器件上表面附有上表面金属层10,为器件引出另一电极。
其制作工艺包括如下步骤:
第一步,在衬底层1表面外延形成第一导电半导体材料层,淀积形成氮化硅层;
第二步,进行光刻腐蚀工艺,半导体材料表面去除部分氮化硅,然后刻蚀去除部分裸露半导体硅材料形成沟槽;
第三步,在沟槽内进行硼杂质扩散;
第四步,在沟槽内淀积形成二氧化硅2,反刻蚀二氧化硅2,淀积多晶第二导电半导体材料7,反刻多晶第二导电半导体材料7,蚀腐蚀去除氮化硅层;
第五步,在半导体材料表面淀积势垒金属,进行烧结形成肖特基势垒结5,然后在表面淀积金属形成上表面金属层10;
第六步,进行背面金属化工艺,在背面形成下表面金属层11,如图1所示。
实施例2
图2为本发明的一种沟槽电荷补偿肖特基半导体装置剖面图,下面结合图2详细说明本发明的半导体装置。
一种肖特基半导体装置,包括:衬底层1,为N导电类型半导体硅材料,磷原子的掺杂浓度为1E19/CM3,在衬底层1下表面,通过下表面金属层11引出电极;第一导电半导体材料3,位于衬底层1之上,为N传导类型的半导体硅材料,磷原子的掺杂浓度为1E16/CM3;第二导电半导体材料4,位于沟槽内壁附近,为P传导类型的半导体硅材料,硼原子的掺杂浓度为3E16/CM3;肖特基势垒结5,位于第一导电半导体材料3的表面,为半导体硅材料与势垒金属形成的硅化物;二氧化硅2,位于沟槽内壁;氮化硅6,位于沟槽内下部;多晶第二导电半导体材料7,为高浓硼掺杂的多晶半导体硅材料,位于沟槽内上部;器件上表面和沟槽内上部附有上表面金属层10,为器件引出另一电极。
其制作工艺包括如下步骤:
第一步,在衬底层1表面外延形成第一导电半导体材料层,淀积形成氮化硅层;
第二步,进行光刻腐蚀工艺,半导体材料表面去除部分氮化硅,然后刻蚀去除部分裸露半导体硅材料形成沟槽;
第三步,在沟槽内进行硼杂质扩散,同时在沟槽内壁形成二氧化硅2;
第四步,在沟槽内淀积形成氮化硅6,反刻蚀氮化硅6,淀积多晶第二导电半导体材料7,反刻多晶第二导电半导体材料7;
第五步,在半导体材料表面淀积势垒金属,进行烧结形成肖特基势垒结5,然后在表面淀积金属形成上表面金属层10;
第六步,进行背面金属化工艺,在背面形成下表面金属层11,如图2所示。
通过上述实例阐述了本发明,同时也可以采用其它实例实现本发明,本发明不局限于上述具体实例,因此本发明由所附权利要求范围限定。
Claims (7)
1.一种沟槽电荷补偿肖特基半导体装置,其特征在于:包括:
衬底层,为半导体材料构成;
漂移层,为第一导电半导体材料构成,位于衬底层之上;多个
沟槽结构,沟槽位于漂移层中,漂移层中临靠沟槽内壁区域设置有第二导电半导体材料,沟槽内下部填充有绝缘材料,沟槽内上部填充高浓度杂质掺杂多晶第二导电半导体材料,第二导电半导体材料与沟槽内上部填充多晶半导体材料直接相连或者具有绝缘材料层进行隔离;
肖特基势垒结,位于漂移层第一导电半导体材料上表面。
2.如权利要求1所述的半导体装置,其特征在于:所述的衬底层为高浓度杂质掺杂的半导体材料。
3.如权利要求1所述的半导体装置,其特征在于:所述的衬底层为高浓度杂质掺杂的半导体材料层和低浓度杂质掺杂的半导体材料层的叠加层。
4.如权利要求1所述的半导体装置,其特征在于:所述的沟槽内下部填充的绝缘材料为二氧化硅。
5.如权利要求1所述的半导体装置,其特征在于:所述的第二导电半导体材料与漂移层第一导电半导体材料形成电荷补偿结构。
6.如权利要求1所述的半导体装置,其特征在于:所述的肖特基势垒结为势垒金属与第一导电半导体材料形成的势垒结。
7.如权利要求1所述的一种沟槽电荷补偿肖特基半导体装置的制造方法,其特征在于:包括如下步骤:
1)在衬底层表面形成第一导电半导体材料层,然后表面形成绝缘材料层氮化硅;
2)进行光刻腐蚀工艺去除表面部分绝缘介质,然后刻蚀去除部分裸露半导体材料形成沟槽;
3)在沟槽内进行第二导电杂质扩散;
4)在沟槽内淀积绝缘材料二氧化硅,反刻蚀绝缘材料二氧化硅,淀积多晶半导体材料,反刻蚀多晶半导体材料,去除表面绝缘材料;
5)淀积势垒金属,进行烧结形成肖特基势垒结。
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