CN103515231B - FinFET manufacture method - Google Patents
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- CN103515231B CN103515231B CN201210206310.XA CN201210206310A CN103515231B CN 103515231 B CN103515231 B CN 103515231B CN 201210206310 A CN201210206310 A CN 201210206310A CN 103515231 B CN103515231 B CN 103515231B
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Abstract
The present invention provides a kind of FinFET manufacture method, on the premise of not increasing device size, by dielectric layer etching groove on a semiconductor substrate, described groove filled by the stressed semiconductor material using lattice to be different from described Semiconductor substrate again, removal medium layer i.e. autoregistration defines the fin standing on substrate, fin and the lattice mismatch of Semiconductor substrate below, make the channel region of fin produces stress, improve channel carrier mobility, and then improve the driving electric current of FinFET；Further, described fin is carried out carbon and/or N~+ implantation, to reduce the ion implanting defect when source/drain region that fin is carried out and channel region doping, improve the interface quality in fin channel district simultaneously, improve FinFET performance.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of FinFET manufacture method.
Background technology
MOSFET(metal oxide semiconductor field effect answers transistor) be major part semiconductor device main member, work as raceway groove
Length less than 100nm time, in traditional MOSFET, due to be surrounded with the semi-conducting material of the Semiconductor substrate of source region make source electrode and
Drain electrode is interval interactive, and the distance with source electrode that drains shortens the most therewith, produces short-channel effect, the so grid control to raceway groove
Making less able, the difficulty of grid voltage pinch off (pinch off) raceway groove is the most increasing, the most just makes sub-threshold values electric leakage
(Subthrehhold leakage) phenomenon is easier to occur.
Fin field-effect transistor (Fin Field effect transistor, FinFET) is a kind of new burning
Semiconductor field effect transistor, its structure silicon (SOI) substrate the most on insulator is formed, including narrow and isolated silicon strip
(i.e. the channel structure of vertical-type, also referred to as fin), fin both sides are with grid structure.FinFET structure makes device less, property
Can be higher.
As it is shown in figure 1, the structure of a kind of FinFET in prior art, including substrate (not shown) and stand on lining
Fin at the end, described fin is typically formed by the silicon epitaxial layers in etched substrate, and described fin generally includes source region 11, leakage
District 12, fin channel district 13 between source region 11 and drain region 12, the structure of described FinFET also includes being centered around fin
The grid structure 14 of type channel region 13 both sides and top.Wherein, described fin channel district 13 very thin thickness, and itself and grid structure
Three faces of 14 contacts are controlled, by the control of grid structure 14, can construct fully-depleted structure, thorough kerf
The conductive path in road.
In prior art, a kind of method improving FinFET driving electric current is on the FinFET surface shown in Fig. 1
Deposition stressor layers to introduce stress to fin channel district 13, improve fin channel district 13 carrier mobility, but this side
Method makes the size of the FinFET manufactured increase, it is impossible to the manufacture of the FinFET meeting below 22nm technology node is wanted
Ask.
Summary of the invention
It is an object of the invention to provide a kind of FinFET manufacture method, on the premise of not increasing device size, it is possible to
Increase carrier mobility, improve the driving electric current of FinFET.
For solving the problems referred to above, the present invention proposes a kind of FinFET manufacture method, comprises the following steps:
Semiconductor substrate, on the semiconductor substrate metallization medium layer are provided；
Etch described dielectric layer extremely described semiconductor substrate surface, form at least one groove；
Fill lattice in the trench and be different from the stressed semiconductor material of described Semiconductor substrate；
Remove described dielectric layer；
Formed stand on the fin in described Semiconductor substrate, described fin include source region, drain region and be positioned at source region and
Fin channel district between drain region；
Formed around described both sides, fin channel district and the gate stack structure of top.
Further, described Semiconductor substrate is silicon-Germanium substrate, and the stressed semiconductor material filled in the trench is
Silicon.
Further, described Semiconductor substrate is silicon substrate, and the stressed semiconductor material filled in the trench is silicon
Germanium.
Further, epitaxially grown mode is used to fill stressed semiconductor material in the trench.
Further, formed after standing on the fin in described Semiconductor substrate, described fin channel district is carried out N-type
Or P-type channel ion implanting.
Further, the dosage of described N-type or P-type channel ion implanting is 1.0E18/cm2~1.0E20/cm2。
Further, formed after standing on the fin in described Semiconductor substrate, described fin is carried out carbon and/or nitrogen
Ion implanting.
Further, the energy of described carbon and/or N~+ implantation is 0.3KeV ~ 1.5KeV, and dosage is 1E19/cm2~
1E21/cm2。
Further, formed before the gate stack structure of described both sides, fin channel district and top, also include:
Stressor layers is deposited in described Semiconductor substrate and described fin surface；
Described stressor layers is removed after annealing.
Further, the deposit thickness of described stressor layers is 20nm ~ 50nm, and stress is 0.7GPa ~ 2GPa.
Further, described dielectric layer is silicon oxide or silicon nitride.
Further, described gate stack structure includes gate dielectric layer and is formed at the grid that described gate dielectric layer is peripheral
Layer.
Further, all grooves are completely independent.
Further, each groove includes source range, drain region section and the ditch between described source range and drain region section
Road section, fluted source range is mutually communicated becomes an entirety, and drain region section is mutually communicated becomes an entirety, channel region
Section is separate.
Compared with prior art, the FinFET manufacture method that the present invention provides, on the premise of not increasing device size, logical
Cross dielectric layer on a semiconductor substrate and etch groove, then use lattice to be different from the stressed semiconductor of described Semiconductor substrate
Described groove filled by material, and removal medium layer i.e. autoregistration defines the fin standing on substrate, fin and half below
The lattice mismatch of conductor substrate so that produce stress in the channel region of fin, improves channel carrier mobility, and then improves
The driving electric current of FinFET；Further, described fin is carried out carbon and/or N~+ implantation, carry out source/drain to reduce
Ion implanting defect when district and channel region doping, improves the interface quality in fin channel district simultaneously, improves FinFET
Performance；Further, before forming gate stack structure, first on fin, form a stressor layers, should by the machinery of stressor layers
Power transfers to fin channel district, then removes described stressor layers, improves the driving electric current of FinFET, then removes stress
Layer, controls FinFET size.
Accompanying drawing explanation
Fig. 1 is the perspective view of a kind of FinFET of prior art；
Fig. 2 is the FinFET manufacture method flow chart of the specific embodiment of the invention；
Fig. 3 A ~ 3F is the device architecture schematic diagram of the FinFET manufacturing process of the specific embodiment of the invention.
Detailed description of the invention
The FinFET manufacture method that the present invention provides, forms fin with direct etching substrate upper epitaxial layer in prior art
Mode is different, it is critical only that and forms the fin with substrate lattice mismatch by self-aligned manner, and introducing in fin channel district should
Power, to improve carrier mobility, and then improves FinFET driveability.
The FinFET manufacture method proposed the present invention below in conjunction with the drawings and specific embodiments is described in further detail.
As in figure 2 it is shown, the present invention provides a kind of FinFET manufacture method, comprise the following steps:
S21, it is provided that Semiconductor substrate, on the semiconductor substrate metallization medium layer；
S22, etches described dielectric layer extremely described semiconductor substrate surface, forms at least one groove；
S23, fills lattice in the trench and is different from the stressed semiconductor material of described Semiconductor substrate；
S24, removes described dielectric layer；
S25, is formed and stands on the fin in described Semiconductor substrate, and described fin includes source region, drain region and is positioned at source
Fin channel district between district and drain region；
S26, is formed around described both sides, fin channel district and the gate stack structure of top.
Refer to Fig. 3 A, in the step s 21, it is provided that Semiconductor substrate 300 can be silicon-Germanium substrate, it is also possible to for silicon serve as a contrast
The end, it is preferred that Semiconductor substrate 300 is carried out N-type or P type trap zone ion implanting, form N-type well region or P type trap zone；Then,
Forming dielectric layer 301 by techniques such as CVD in Semiconductor substrate 300, the material of this dielectric layer 301 can be silicon nitride or oxygen
The single layer structure of SiClx, it is also possible to be the composite construction of silicon nitride and silicon oxide.
Please continue to refer to Fig. 3 A, in step S22, first can form photoresist layer on dielectric layer 301, then use manufacture
Photoresistance is exposed by the mask plate of FinFET fin sheet, it is not necessary to the mask plate that extra manufacture is new, then carves with this photoresistance for mask
Erosion dielectric layer 301, to exposing described Semiconductor substrate 300 surface, forms one or more groove 301a, this groove 301a and uses
Forming FinFET fin sheet in follow-up autoregistration, this groove 301a includes source range, drain region section and is positioned at source range and drain region section
Between channel section (not shown).The all grooves formed can be completely independent (not shown), separate for manufacturing
FinFET；The all grooves formed can also be common source section and drain region section, i.e. fluted source range is mutually communicated into
Being an entirety, drain region section is mutually communicated becomes an entirety, and channel section is separate, is used for manufacturing many raceway grooves FinFET
(not shown, to refer to Fig. 1).
Refer to Fig. 3 B, in step S23, can fill out in described groove 301a to use the mode such as epitaxial growth or CVD
Fill stressed semiconductor material 302.The lattice of stressed semiconductor material 302 is different from Semiconductor substrate 300, to cause lattice to lose
Join, in the fin channel district of the FinFET being subsequently formed, introduce stress, improve carrier mobility；Such as, partly lead when described
When body substrate 300 is silicon-Germanium substrate, the stressed semiconductor material 302 filled in described groove 301a is silicon；Partly lead when described
When body substrate 300 is silicon substrate, the stressed semiconductor material 302 filled in described groove 301a is SiGe.
Refer to Fig. 3 C, in step s 24, removal medium layer 301, and then expose the stressed semiconductor material of filling
302。
Please continue to refer to Fig. 3 C, in step s 25, in the semi-conducting material filled, inject ion, form fin, described
Fin includes source region, drain region and the fin channel district (not shown) between source region and drain region, the side of this formation fin
Formula is a kind of self-aligned manner, and the lattice of the stressed semiconductor material 302 of fin is different from Semiconductor substrate 300, Ke Yizao
Become lattice mismatch, in the fin channel district of the FinFET formed, introduce stress, improve carrier mobility, such that it is able to improve
The driving electric current of the FinFET prepared.
Further, carry out N-type or P-type channel ion implanting to the fin channel district of described fin, to form N fin ditch
Road or P fin channel, the dosage carrying out N-type or P-type channel ion implanting is preferably 1.0E18/cm2~1.0E20/cm2。
Refer to Fig. 3 D, in the present embodiment, after step s25, also described fin is carried out carbon and/or the nitrogen of multi-angle
Ion implanting (as shown by arrows), carries out short annealing or laser annealing, so that the ion diffusion injected is uniformly, and ion implanting
Energy be preferably 0.3KeV ~ 1.5KeV, dosage is preferably 1E19/cm2~1E21/cm2.Carbon and/or N~+ implantation, on the one hand
Can reduce the ion implanting defect when source/drain region carrying out fin and channel region doping, N-type or p-type ditch are injected in suppression
The diffusion that road ion and follow-up heavy-doped source/drain ion are injected；On the other hand can also be at the interface in fin channel district
Form protective layer 302a, improve the interface quality in fin channel district, reduce leakage current, thus improve FinFET performance.
Refer to Fig. 3 E, in the present embodiment, in order to increase the stress in fin channel district further, described fin is being carried out
After the carbon of multi-angle and/or N~+ implantation, also deposit stressor layers in described Semiconductor substrate 300 and described fin surface
303, the deposit thickness of described stressor layers 303 is 20nm ~ 50nm, and stress is 0.7GPa ~ 2GPa；Then, annealing process is carried out, will
The mechanical stress of stressor layers 303 transfers to fin channel district, improves the driving electric current of FinFET；Then, refer to Fig. 3 F,
Remove described stressor layers 303.
Please continue to refer to Fig. 3 F, after step S26, can be sequentially formed around institute by methods such as chemical gaseous phase depositions
Stating the gate stack structure of both sides, fin channel district and top, this gate stack structure includes gate dielectric layer 304 and periphery thereof
Grid layer 305.Wherein, grid layer 305 can be polysilicon, and gate dielectric layer 304 can be silicon oxide or silicon oxynitride；Grid layer
305 can also be metal material, and gate dielectric layer 304 can be high K dielectric material.
Please continue to refer to Fig. 3 F, after forming gate stack structure, it is also possible to carry out the following step:
With described gate stack structure as mask, described source region and drain region are lightly doped (LDD) ion implanting；
Sidewall at described gate stack structure forms side wall (not shown)；
With described gate stack structure and side wall as mask, described source region and drain region are carried out heavy doping source/drain (S/D)
Ion implanting.
In sum, the FinFET manufacture method that the present invention provides, on the premise of not increasing device size, by half
Dielectric layer on conductor substrate etches groove, then the stressed semiconductor material using lattice to be different from described Semiconductor substrate is filled out
Filling described groove, removal medium layer i.e. autoregistration defines the fin standing on substrate, fin and quasiconductor lining below
The lattice mismatch at the end so that produce stress in the channel region of fin, improves channel carrier mobility, and then improves FinFET
The driving electric current of device；Further, described fin is carried out carbon and/or N~+ implantation, with reduce carry out source/drain region and
Ion implanting defect during channel region doping, improves the interface quality in fin channel district simultaneously, improves FinFET performance；More
Further, before forming gate stack structure, first on fin, form a stressor layers, the mechanical stress of stressor layers is shifted
To fin channel district, then remove described stressor layers, improve the driving electric current of FinFET, then remove stressor layers, control
FinFET size.
Obviously, those skilled in the art can carry out various change and the modification spirit without deviating from the present invention to invention
And scope.So, if the present invention these amendment and modification belong to the claims in the present invention and equivalent technologies thereof scope it
In, then the present invention is also intended to comprise these change and modification.
Claims (14)
1. a FinFET manufacture method, it is characterised in that including:
Semiconductor substrate, on the semiconductor substrate metallization medium layer are provided；
Etch described dielectric layer extremely described semiconductor substrate surface, form at least one groove；
Fill lattice in the trench and be different from the stressed semiconductor material of described Semiconductor substrate；
Remove described dielectric layer；
Being formed and stand on the fin in described Semiconductor substrate, described fin includes source region, drain region and is positioned at source region and drain region
Between fin channel district；
Described fin is carried out carbon and/or the N~+ implantation of multi-angle, forms protective layer on the surface in described fin channel district；
Formed around described both sides, fin channel district and the gate stack structure of top.
2. FinFET manufacture method as claimed in claim 1, it is characterised in that described Semiconductor substrate is silicon-Germanium substrate,
The stressed semiconductor material filled in described groove is silicon.
3. FinFET manufacture method as claimed in claim 1, it is characterised in that described Semiconductor substrate is silicon substrate, in institute
Stating the stressed semiconductor material filled in groove is SiGe.
4. FinFET manufacture method as claimed in claim 1, it is characterised in that use epitaxially grown mode at described groove
Middle filling stressed semiconductor material.
5. FinFET manufacture method as claimed in claim 1, it is characterised in that formed and stand in described Semiconductor substrate
The step of fin includes: described fin channel district is carried out N-type or P-type channel ion implanting.
6. FinFET manufacture method as claimed in claim 5, it is characterised in that described N-type or the agent of P-type channel ion implanting
Amount is 1.0E18/cm2～1.0E20/cm2。
7. FinFET manufacture method as claimed in claim 1, it is characterised in that described carbon and/or the energy of N~+ implantation
For 0.3KeV～1.5KeV, dosage is 1.0E19/cm2～1.0E21/cm2。
8. FinFET manufacture method as claimed in claim 1, it is characterised in that formed around described both sides, fin channel district and
Before the gate stack structure of top, also include:
Stressor layers is deposited in described Semiconductor substrate and described fin surface；
Remove described stressor layers.
9. FinFET manufacture method as claimed in claim 8, it is characterised in that the thickness of described stressor layers be 20nm～
50nm, stress is 0.7GPa～2GPa.
10. FinFET manufacture method as claimed in claim 1, it is characterised in that described dielectric layer is silicon oxide or silicon nitride.
11. FinFET manufacture methods as claimed in claim 1, it is characterised in that described gate stack structure includes gate medium
Layer and be formed at the grid layer that gate dielectric layer is peripheral.
12. FinFET manufacture methods as claimed in claim 1, it is characterised in that all grooves are completely independent.
13. FinFET manufacture methods as claimed in claim 1, it is characterised in that each groove include source range, drain region section with
And the channel section between described source range and drain region section.
14. FinFET manufacture methods as claimed in claim 13, it is characterised in that fluted source range is mutually communicated into
Being an entirety, drain region section is mutually communicated becomes an entirety, and channel section is separate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201210206310.XA CN103515231B (en) | 2012-06-20 | 2012-06-20 | FinFET manufacture method |
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| CN201210206310.XA CN103515231B (en) | 2012-06-20 | 2012-06-20 | FinFET manufacture method |
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| CN103515231B true CN103515231B (en) | 2016-12-07 |
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| CN105097536A (en) * | 2014-05-12 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure |
| CN110323136B (en) * | 2018-03-29 | 2023-06-13 | 中芯国际集成电路制造(上海)有限公司 | FinFET manufacturing process |
| CN110970300B (en) * | 2018-09-29 | 2023-09-22 | 中芯国际集成电路制造(上海)有限公司 | Stacked gate-all-around fin field effect transistor and forming method thereof |
| CN113363145B (en) * | 2020-03-05 | 2023-12-22 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| WO2023044924A1 (en) * | 2021-09-27 | 2023-03-30 | 西门子股份公司 | Method and apparatus for determining geometric structure of radiator fin, and storage medium |
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| JP4504214B2 (en) * | 2005-02-04 | 2010-07-14 | 株式会社東芝 | MOS type semiconductor device and manufacturing method thereof |
| KR100653536B1 (en) * | 2005-12-29 | 2006-12-05 | 동부일렉트로닉스 주식회사 | Method for fabricating fin fet of semiconductor device |
| US7341902B2 (en) * | 2006-04-21 | 2008-03-11 | International Business Machines Corporation | Finfet/trigate stress-memorization method |
| EP2073267A1 (en) * | 2007-12-19 | 2009-06-24 | INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) | Method of fabricating multi-gate semiconductor devices and devices obtained |
| CN102347350A (en) * | 2010-07-30 | 2012-02-08 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
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