CN103515207B - Oxide layer, HKMG structure median surface layer, MOS transistor forming method and MOS transistor - Google Patents

Oxide layer, HKMG structure median surface layer, MOS transistor forming method and MOS transistor Download PDF

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CN103515207B
CN103515207B CN201210203540.0A CN201210203540A CN103515207B CN 103515207 B CN103515207 B CN 103515207B CN 201210203540 A CN201210203540 A CN 201210203540A CN 103515207 B CN103515207 B CN 103515207B
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layer
gas
substrate
boundary layer
forming method
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CN103515207A (en
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洪中山
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity

Abstract

The embodiment of the invention discloses the boundary layer forming method between Semiconductor substrate and high-K dielectric layer in a kind of HKMG structure, including: a) provide Semiconductor substrate；B) using the reacting gas comprising hydroxyl and described substrate surface contact, the hydroxyl in described reacting gas forms intermediate material with the atom of substrate surface by chemical bonds；C) described reacting gas is removed；D) described substrate is annealed, remove the protium in described intermediate material, form atomic layer at described substrate surface；E) repeat step b) step d), until the ulking thickness of described atomic layer reaches the target thickness of described boundary layer, obtain described boundary layer.It is more preferable that the embodiment of the present invention uses the form piled up layer by layer to form boundary layer, relatively prior art, the consistency of this boundary layer and the uniformity, and under identical gate dielectric layer depth information, the dielectric constant of the gate dielectric layer in the embodiment of the present invention is bigger.

Description

Oxide layer, HKMG structure median surface layer, MOS transistor forming method and MOS transistor
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of oxide layer, HKMG structure median surface Layer, MOS transistor forming method and MOS transistor.
Background technology
Along with the reduction of semiconductor process technique node, traditional silicon dioxide gate dielectric layer and polysilicon gate The MOS device of electrode layer occurs in that the problems such as electrical leakage quantity increase and gate electrode layer loss, asks for solving this Topic, proposes employing hafnium and replaces silicon dioxide to make gate dielectric layer, use metal in prior art Material for polysilicon makes gate electrode layer (being called for short high-K metal gate, HKMG).
The side of metal gates is formed below with " post tensioned unbonded prestressed concrete " technique provided in United States Patent (USP) US6664195 As a example by method, the forming process of HKMG is described, including: Semiconductor substrate, described Semiconductor substrate are provided On be formed with alternative gate structure and be positioned in described Semiconductor substrate the interlayer covering described alternative gate structure Dielectric layer；Using described alternative gate structure as stop-layer, described interlayer dielectric layer is carried out chemical machinery and grinds Grinding process (CMP)；Groove is formed after removing described alternative gate structure；Boundary layer is formed at channel bottom, Interface layer surfaces is formed high-K dielectric layer, here the lamination of described boundary layer and high-K dielectric layer is claimed For gate dielectric layer (lower same)；Again by forming gold in PVD method high-K dielectric layer in described groove Belong to layer, and metal level is filled full groove, to form grid metal level；Grid are ground with chemical mechanical milling method Metal level, to exposing interlayer dielectric layer, forms metal gates.
Wherein, the existence of the boundary layer between high-K dielectric layer and underlying substrate helps to maintain interface Step response also forms the interface of good electrical character, and owing to boundary layer is connected closely with the raceway groove of transistor, Therefore, the quality of boundary layer can affect the performance of device.
The mode forming boundary layer in prior art mostly is two kinds, and a kind of is that the mode using thermal oxide is formed Boundary layer, this mode is similar with the mode forming regular oxidation layer；A kind of side being to use chemical oxidation Formula forms boundary layer, as formed boundary layer in the water-bath containing deionized water and ozone, concrete as beautiful Described in state's patent US2010/028597.
But, find in actual production process, use the good of the transistor produced of above two method Rate is the most undesirable, and the especially total dielectric constant of gate dielectric layer does not reaches theory calls.
Summary of the invention
For solving above-mentioned technical problem, embodiments provide in a kind of oxide layer, HKMG structure Boundary layer and MOS transistor forming method, and use the MOS transistor of said method formation, should Boundary layer in MOS transistor is finer and close compared with the boundary layer that art methods is formed, and the uniformity is more preferable, Meet yield and the performance requirement of transistor.
For solving the problems referred to above, embodiments provide following technical scheme:
A kind of HKMG structure median surface layer forming method, described boundary layer is positioned at Semiconductor substrate and high K Between dielectric layer, including: a) provide Semiconductor substrate；B) reacting gas and the institute comprising hydroxyl is used Stating substrate surface contact, the hydroxyl in described reacting gas passes through chemical bonds with the atom of substrate surface Form intermediate material；C) described reacting gas is removed；D) described substrate is annealed, remove described Protium in intermediate material, forms atomic layer at described substrate surface；E) step b)-step d) is repeated, Until the ulking thickness of described atomic layer reaches the target thickness of described boundary layer, obtain described boundary layer.
Preferably, described substrate includes that unsaturation silicon atom, described intermediate material are described reacting gas In hydroxyl be combined with the unsaturation silicon atom of substrate surface formed-Si-OH dangling bonds.
Preferably, described reacting gas is H2O gas, D2O gas, H2O2Gas, CH3OH gas At least one in body and HCOOH gas.
The embodiment of the invention also discloses a kind of MOS transistor forming method, have employed above-described boundary Surface layer forming method, this MOS transistor forming method includes: a) provide Semiconductor substrate, described Substrate surface forms replacement gate structure；B) with replacement gate structure as mask, in substrate formed source/ Drain electrode；C) formation interlayer dielectric layer on described substrate surface, and described interlayer dielectric layer surface and replacement Grid structure top flushes；D) with described interlayer dielectric layer as mask, described replacement gate structure is removed, Form groove；E) reacting gas comprising hydroxyl and described substrate surface contact, described reacting gas are used In the atom of hydroxyl and substrate surface form intermediate material by chemical bonds；F) described reaction is removed Gas；G) described substrate is annealed, remove the protium in described intermediate material, at described substrate Surface forms atomic layer；H) step e)-step g) is repeated, until the ulking thickness of described atomic layer reaches The target thickness of described boundary layer, obtains described boundary layer；I) on described interface layer surfaces, high K is formed Dielectric layer；J) on described high-K dielectric layer surface, form the metal gates of the full described groove of filling.
The embodiment of the invention also discloses a kind of MOS transistor forming method, have employed above-described boundary Surface layer forming method, it is characterised in that this MOS transistor forming method includes: a) provide quasiconductor Substrate；B) reacting gas comprising hydroxyl and described substrate surface contact are used, in described reacting gas Hydroxyl forms intermediate material with the atom of substrate surface by chemical bonds；C) described reacting gas is removed； D) described substrate is annealed, remove the protium in described intermediate material, in described substrate surface shape Become atomic layer；E) step b)-step d) is repeated, until the ulking thickness of described atomic layer reaches described boundary The target thickness of surface layer, obtains described boundary layer；F) on described interface layer surfaces, high-K dielectric layer is formed； G) on described high-K dielectric layer surface, replacement gate is formed；H) with described replacement gate as mask, Source/drain is formed in substrate surface；I) interlayer dielectric layer is formed on the surface of a substrate, and described inter-level dielectric Layer surface flushes with replacement gate structural top；J) with described interlayer dielectric layer as mask, replace described in removal For grid structure, form groove；K) in described groove, fill up metal, form metal gates.
The embodiment of the invention also discloses a kind of MOS transistor, there is HKMG structure, and this MOS Boundary layer in transistor uses above-described boundary layer forming method to be formed, and this boundary layer is positioned at partly leads Between body substrate and high-K dielectric layer, its consistency is formed more than thermal oxidation technology and chemical oxidation process Boundary layer.
The embodiment of the invention also discloses a kind of oxide layer forming method, including: a) provide Semiconductor substrate； B) use and comprise the reacting gas of hydroxyl and described substrate surface contact, the hydroxyl in described reacting gas with The atom of substrate surface forms intermediate material by chemical bonds；C) described reacting gas is removed；D) Described substrate is annealed, removes the protium in described intermediate material, formed at described substrate surface Atomic layer；E) step b)-step d) is repeated, until the ulking thickness of described atomic layer reaches described oxidation The target thickness of layer, obtains described oxide layer.
Compared with prior art, technique scheme has the advantage that
The technical scheme that the embodiment of the present invention is provided, is passed through the reacting gas comprising hydroxyl in reaction chamber, Reacting gas carries out chemical reaction with the atom of semiconductor substrate surface, the hydroxyl in reacting gas and substrate The atom on surface passes through chemical bonds, as a example by silicon substrate, owing to the silicon atom of substrate surface is non-full And silicon atom, these unsaturated silicon atoms combine formation-Si-OH dangling bonds with hydroxyl by absorption, by Adhesion in hydroxyl with silicon atom is more than the adhesion of oxygen atom and silicon atom, therefore, the oxygen in hydroxyl Atom is tightr with the combination of silicon atom, is difficult to desorption, during subsequent anneal, removable-Si-OH Protium in dangling bonds, and then the atomic layer comprising mono-layer oxidized silicon atom is formed at substrate surface, it Afterwards by the forming process of atomic layer is repeated several times, the ulking thickness of atomic layer is made to reach the target of boundary layer Thickness, i.e. obtains boundary layer.
It is more preferable owing to using the form piled up layer by layer to form boundary layer, the consistency of this boundary layer and the uniformity, And be far longer than the consistency of the oxide layer that thermal oxide and chemical oxidation process are formed, thus at identical grid In the case of thickness of dielectric layers, the dielectric constant of the gate dielectric layer in the embodiment of the present invention is bigger, and it is right to meet The requirement of gate dielectric layer dielectric constant, in other words, wanting at the same dielectric constant to gate dielectric layer Asking down, it is thinner that the boundary layer in the present embodiment can do, and the boundary layer of relatively prior art drops further Low the equivalent oxide thickness of gate dielectric layer (EOT).
Accompanying drawing explanation
Fig. 1 is the flow chart of HKMG structure median surface layer forming method disclosed in the embodiment of the present invention；
Fig. 2-4 the cuing open of the HKMG structure median surface each step of layer forming method disclosed in the embodiment of the present invention Face figure；
The profile of each step of MOS transistor forming method disclosed in Fig. 5-Figure 11 embodiment of the present invention；
The section of each step of MOS transistor forming method disclosed in Figure 12-Figure 19 another embodiment of the present invention Figure.
Detailed description of the invention
The most as described in the background section, the semiconductor device that method of the prior art produces is used Yield tends not to meet requirement, and the especially total dielectric constant of gate dielectric layer is less than theory calls.
Inventor studies discovery, occurs that the basic reason of this problem is, produces in prior art The difficult quality of the boundary layer between high-K dielectric layer and substrate reaches desirable, uses thermal oxide The thickness of the boundary layer that technique is formed is the most excessive, and the existence of blocked up boundary layer will necessarily reduce grid and be situated between The dielectric constant that matter layer is total；And the boundary layer quality of chemical oxidation process formation is the highest, major embodiment Poor for consistency, in the case of gate dielectric layer dielectric constant is fixing, be difficult to do boundary layer is thinner, And the gate dielectric layer that compactness is poor and thickness is thicker inevitably results in the load in the channel region of MOS device Stream transport factor declines, and grid leakage current improves, and makes device electrical performance be deteriorated.
Inventor further study show that, the oxidation controlling one atomic layer of monocrystalline silicon surface contributes to obtaining The thickness of controlled silicon oxide, i.e. uses the silicon oxide that the mode of silicon oxide atomic layer of being layering formed Thickness can be precisely controlled, and the consistency of the silicon oxide formed is good, this process particularly as follows: The surface of silicon (or silicon oxide) can controllably be formed uniform "-Si-OH " dangling bonds (i.e. unsaturated bond or Scission of link), surface "-Si-OH " is carried out heat treatment, the silicon oxide of monoatomic layer can be formed, through repeatedly Circulation, it is possible to obtain the silicon oxide layer of specific thicknesses.
It is above the core concept of the application, for enabling the above-mentioned purpose of the present invention, feature and advantage more For becoming apparent, below in conjunction with the accompanying drawings the specific embodiment of the present invention is described in detail.
Embodiment one
Embodiments provide a kind of semiconductor integrated device manufacture method, the profile of its each step As shown in figs 2-4, this manufacture method is retouched by profile below in conjunction with Fig. 1 and each step in detail State.
Step S101: as shown in Figure 2, it is provided that Semiconductor substrate 100；In described Semiconductor substrate 100 Being formed with isolation area 101 and the active area between isolation area, wherein isolation area 101 can be shallow ridges Groove isolation (STI) district, it is also possible to be locos region；
Semiconductor substrate in the present embodiment can be planar substrate, it is also possible to for non-planar substrate, For non-planar substrate, its surface can include fin type transistor structure or nanowire crystal tubular construction, separately May also include outward the alternative gate structure etc. in HKMG technique.
Semiconductor substrate in the present embodiment can include silicon or the SiGe of monocrystalline, polycrystalline or non crystalline structure (SiGe), it is also possible to include the semiconductor structure of mixing, such as carborundum (SiC), indium antimonide, tellurium Change lead, indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or a combination thereof；Can also be Silicon-on-insulator (SOI).Additionally, Semiconductor substrate can also include other material, such as epitaxial layer Or the multiple structure of oxygen buried layer.Although there is described herein several examples of the material that can form substrate, but It is can to each fall within the spirit and scope of the present invention as any material of Semiconductor substrate.In the present embodiment Only illustrate as a example by plane silicon substrate.
Afterwards, described substrate is carried out pre-treatment, remove oxide layer and impurity particle, the institute of substrate surface State pretreatment process to include:
Step S102: described substrate carries out Chemical cleaning, the oxide layer removing substrate surface (includes certainly So oxide layer) and impurity particle, the mixing that solution is HF and HCl that described Process of Chemical Cleaning uses Solution or HF and NH3Mixed solution or HF solution, this Process of Chemical Cleaning use HF molten Liquid is preferably dilute HF solution, and its concentration range can refer to go in prior art HF solution during removing oxide layer Concentration.
Step S103: anneal the substrate after Chemical cleaning, to repair the lattice of substrate surface Defect, the forming process for follow-up boundary layer haves laid a good foundation, and the atomic layer making formation is more equal Even and fine and close, the gas in the atmosphere of described annealing process includes: H2、D2、N2、NH3And He In at least one, the most highly purified H2、D2、N2、NH3Or He, or it is H2And N2's Mixed gas, concrete annealing temperature and time are similar equal to routine techniques, repeat no more here.
After pre-treatment, enter step S104: this Semiconductor substrate be transferred in a reaction chamber, Described reaction chamber is passed through the reacting gas comprising hydroxyl, i.e. uses and comprise the reacting gas of hydroxyl with described Substrate surface contact, the hydroxyl in described reacting gas passes through chemical bonds shape with the atom of substrate surface Become intermediate material；
The present embodiment preferably employs and is passed through reacting gas in reaction chamber with impulse form, and reacting gas Protium in hydroxyl can be the various isotopes of hydrogen.Reacting gas in the present embodiment is H2O gas, D2O gas, H2O2Gas, CH3One in OH gas and HCOOH gas or combination, this enforcement Intermediate material 102 in example is "-Si-OH " dangling bonds.
It should be noted that the reaction chamber in the present embodiment can be ald (Atomic Layer Deposition, ALD) reaction chamber of technique, it is also possible to deposit (Chemical Vapor for chemical gaseous phase Deposition, CVD) reaction chamber of technique, the present embodiment is preferably the reaction chamber of ALD technique. Further, temperature in course of reaction, pressure etc. can change according to the change of reacting gas, if energy Reacting gas is made to form "-Si-OH " dangling bonds with the unsaturation silicon atom of substrate surface by chemical bonds , with H2O2As a example by gas, H2O2Molecular Adsorption is on unsaturated silicon atom, because the silicon on surface is former Son is the silicon atom (i.e. unsaturation silicon atom) of activation, forms "-Si-OH " dangling bonds.Owing to being formed The process of "-Si-OH " dangling bonds is adsorption process, and therefore reaction temperature can be between room temperature-200 DEG C.
Step 105: remove described reacting gas；
The present embodiment preferably employ by impulse form in the way of being passed through flushing gas in described reaction chamber, Remove unnecessary reacting gas and the by-product of chemical reaction, it is preferred that described flushing gas includes: He、N2, at least one in Ne, Ar and Xe, more preferably He.Further, the purity of flushing gas Higher.Certainly, the mode of suction also can be used to be extracted out by the gas in reaction chamber, it is possible to use suction and Rinse the gas of the mode cleaning reaction intracavity combined.
Step S106: as it is shown on figure 3, described substrate is carried out high annealing, remove described intermediate material Protium in "-Si-OH " dangling bonds, forms atomic layer 102, this atomic layer 102 at described substrate surface By the SiO of monolayer2Molecular composition, owing to intermediate material "-Si-OH " dangling bonds is equal in the distribution of substrate surface Even and fine and close, therefore this SiO2Atomic layer is the most evenly and fine and close；
Annealing process in this step is rapid thermal anneal process, the annealing temperature of described rapid thermal anneal process Degree is 500 DEG C-1100 DEG C, preferably 550 DEG C, 650 DEG C, 700 DEG C, 800 DEG C, 900 DEG C, 1000 DEG C, Annealing time is 1ms-100 μ s, i.e. annealing temperature is the highest, and the time of annealing is the shortest, as annealing temperature is When 650 DEG C, annealing time can be 600 μ s-900 μ s, and when annealing temperature is 900 DEG C, annealing temperature can be 200 μ s-400 μ s, the corresponding relation of concrete annealing temperature and annealing time can be according to the reality of intermediate material Depending on situation, as intermediate material is the finest and close, the protium comprised is the most, then required annealing temperature just may be used With higher, such as more than 800 DEG C, annealing time can also extend accordingly, did not did this in the present embodiment Many restrictions.
Gas in the atmosphere of rapid thermal anneal process described in the present embodiment includes: H2、D2、N2、 At least one in He, Ne, Ar and Xe.
Step S107: judge whether the ulking thickness of described atomic layer reaches the target thickness of described boundary layer, If it is not, then return step S104, repeated execution of steps S104-step S106, i.e. repeat atom The banking process of layer, if the ulking thickness of atomic layer has reached the target thickness of described boundary layer, then enters Enter step S108, as shown in Figure 4, i.e. complete the growth course of described boundary layer, obtained boundary layer 103。
It should be noted that in the formation early stage of boundary layer, the judgement in step S107 can not be carried out Journey, and directly repeat the forming process of atomic layer, when the banking process of atomic layer performs certain number of times After, in order to ensure the accuracy of interfacial layer thickness, after completing an atomic layer banking process, to currently The gross thickness that atomic layer is piled up measures, if being also not up to the target thickness of boundary layer, then proceeds The banking process of atomic layer, until it reaches the target thickness of boundary layer, below corresponding judge process with This is similar.
The number of times repeating atomic layer banking process in the present embodiment is 1-1000 time, described boundary layer Target thickness is
Forming boundary layer in the present embodiment by the way of piling up layer by layer, the consistency of this boundary layer is with uniform Degree is more preferable, and is far longer than the consistency of the oxide layer of thermal oxide and chemical oxidation process formation, thus Under identical gate dielectric layer depth information, the dielectric constant of the gate dielectric layer in the embodiment of the present invention is bigger, Meet the requirement to gate dielectric layer dielectric constant, in other words, in the same dielectric to gate dielectric layer Under the requirement of constant, it is thinner that the boundary layer in the present embodiment can do, the boundary layer of relatively prior art, Reduce further the equivalent oxide thickness (EOT) of gate dielectric layer, and by then passing through heap layer by layer The boundary layer that long-pending mode is formed, also can the thickness of more precise control boundary layer in the present embodiment so that it is Meet device performance requirements.
Step S109: anneal described boundary layer, the annealing temperature of this annealing process is higher than step S106 In annealing temperature, and the gas in the atmosphere of this annealing process includes H2、D2、N2、He、Ne、 At least one in Ar and Xe.
Rapid thermal annealing process in step S106 mainly removes the list being made up of "-Si-OH " dangling bonds Protium in the intermediate material of layer, therefore annealing temperature is not the highest, and annealing time is shorter, step Annealing process in S109 can repair the lattice defect of substrate surface further, increases boundary layer further Compactness, therefore, the annealing temperature in this step can be higher than the temperature of the rapid thermal annealing in step S 106, Annealing time also can proper extension.
Embodiment two
The embodiment of the invention discloses a kind of MOS transistor forming method, the profile of its each step such as figure Shown in 5-Figure 11, the forming process of this MOS transistor have employed the boundary layer shape in an embodiment One-tenth method, its concrete forming process is as follows:
As shown in Figure 5, it is provided that Semiconductor substrate 200, similar with a upper embodiment, described Semiconductor substrate Isolation area 216 and the active area between isolation area it is formed with in 200；Semiconductor substrate at active area Alternative gate dielectric layer 201 and alternative gate electrode layer 202, described alternative gate dielectric layer 201 is sequentially formed on 200 Constituting replacement gate structure with alternative gate electrode layer 202, concrete alternative gate electrode layer 202 technique that formed is, Alternative gate dielectric layer 201 is formed polysilicon layer, forms photoresist layer on the polysilicon layer；To photoetching Glue-line is exposed development, forms gate patterns；With patterning photoresist layer as mask, etches polycrystalline silicon Layer and alternative gate dielectric layer 201 are to exposing Semiconductor substrate 200.
Alternative gate dielectric layer described in the present embodiment 201 be one of silicon oxide, silicon oxynitride, silicon nitride or Combination in any.In the present embodiment, described polysilicon layer can use chemical vapor deposition method to be formed, its Deposit thickness determines the height of alternative gate electrode layer 202, namely the height of the metal gates being subsequently formed.
As shown in Figure 6, with alternative gate electrode layer 202 as mask, described Semiconductor substrate 200 is carried out Shallow doped region injects, and forms lightly doped drain 204.For nmos device, injection is N-shaped ion； For PMOS device, injection is p-type ion.Afterwards, described Semiconductor substrate 200 is carried out heat Process, make the ion that injects in lightly doped drain 204 occur longitudinally and horizontal uniform diffusion.This enforcement In example, the Technology for Heating Processing of this step can be carried out together with the annealing process after making source/drain and being complete.
With continued reference to Fig. 6, forming side wall 206 on semiconductor substrate 200, described side wall 206 is positioned at and replaces For grid structure both sides.Concrete formation process is as follows: with chemical vapour deposition technique in Semiconductor substrate 200 Upper and replacement gate structure periphery forms side wall layer；With being etched back to technique etching side wall layer to exposing quasiconductor Substrate 200 and replacement gate structural top.In the present embodiment, the material of described side wall 206 is silicon nitride Or silicon oxide-silicon nitride or oxide-nitride-oxide.
Referring again to Fig. 6, with the side wall 206 of replacement gate structure and replacement gate structure both sides as mask, to Described Semiconductor substrate 200 carries out heavily doped region injection, forms source electrode 208a and drain electrode 208b, described source The degree of depth of pole 208a and drain electrode 208b is deeper than lightly doped drain 204.After injecting ion, to described half Conductor substrate 200 carries out heat treatment, makes the injection ion in source electrode 208a and drain electrode 208b occur longitudinally With horizontal uniform diffusion.
In the present embodiment, forming PMOS transistor region, inject in Semiconductor substrate 200 is P-type ion, such as boron ion etc..Forming nmos transistor region, noting in Semiconductor substrate 200 Enter is N-shaped ion, such as phosphonium ion or arsenic ion etc..
As it is shown in fig. 7, use chemical vapour deposition technique interlayer dielectric layer on semiconductor substrate 200 210, described interlayer dielectric layer 210 covers replacement gate structure；Use cmp (CMP) side Method grind interlayer dielectric layer 210 to exposing replacement gate structural top, the most described interlayer dielectric layer 210 table Face flushes with replacement gate structural top.In the present embodiment, the material of described interlayer dielectric layer 210 is oxygen SiClx or silicon oxynitride etc..
As shown in Figure 8, with interlayer dielectric layer 210 as mask, go by dry etching method or wet etching method Except replacement gate structure, form groove 211.
Afterwards, described substrate carrying out pre-treatment, described pretreatment process includes: carry out described substrate Chemical cleaning, removes oxide layer and the impurity particle of substrate surface, and it is molten that described Process of Chemical Cleaning uses Liquid is the mixed solution of dilute HF Yu HCl or dilute HF and NH3Mixed solution or dilute HF solution； Substrate after Chemical cleaning is annealed, to repair lattice defect.
As it is shown in figure 9, enter atomic layer banking process, by described substrate transport a to reaction chamber, Described reaction chamber is passed through the reacting gas comprising hydroxyl, the hydroxyl in described reacting gas and substrate surface Atom by chemical bonds formed intermediate material, shown reacting gas includes H2O gas, D2O gas Body, H2O2Gas, CH3One in OH gas and HCOOH gas or combination；In the reactor chamber with The form of pulse is passed through flushing gas, removes the by-product of described reacting gas and chemical reaction；To described Substrate carries out rapid thermal annealing, removes the protium in intermediate material, forms atom at described substrate surface Layer 212.This process refers to an embodiment, repeats no more here.
As shown in Figure 10, repeat the banking process of atomic layer, until the ulking thickness of described atomic layer Reach the target thickness of described boundary layer, obtain described boundary layer 213.
With continued reference to Figure 10, annealing boundary layer 213, the annealing temperature of this annealing process is higher than former The annealing temperature of sublayer banking process, and the gas in the atmosphere of this annealing process includes H2、D2、 N2, at least one in He, Ne, Ar and Xe.
As shown in figure 11, chemical vapor deposition method is used to form high K dielectric on boundary layer 213 surface Layer 214, described " on boundary layer 213 surface " refers to by region upwards, boundary layer 213 surface, should Region is not belonging to boundary layer 213 itself.
In the present embodiment, the thickness of high-K dielectric layer 214 is The wherein material of high-K dielectric layer Including hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminum, zirconium oxide, zirconium silicon oxide, tantalum oxide, Titanium oxide, strontium barium oxide titanium, Barium monoxide titanium, strontium oxide titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum, With at least one in lead niobate zinc.
With continued reference to Figure 11, described high-K dielectric layer surface forms the metal gate filling full described groove Pole 215, detailed process is, forms metal level, and filled by described metal level on interlayer dielectric layer 210 Full groove；With chemical mechanical milling method planarization metal layer to exposing interlayer dielectric layer 210, form metal gate Pole 215, described boundary layer 213, high-K dielectric layer 214 constitute metal gate structure with metal gates 215.
Metal gates 215 in the present embodiment can be single coating or multilayer lamination structure.
When described metal gates 215 is single coating, described metal gate material be aluminum, copper, silver, Gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, tungsten silicide, titanium tungsten, titanium nitride, nitridation thallium, carbon Change thallium, nickel platinum or nitrogen silication thallium.
When institute's metal gates 215 is multilayer lamination structure, described metal gates 215 includes: be positioned at high K Work-function layer (not shown) on dielectric layer 214 surface, described work-function layer material can be titanium, Titanium nitride, thallium, titanium aluminum or nitridation thallium；Second gate metal level (the figure being positioned on described work-function layer surface Not shown in), described second gate metal layer material can be aluminum, copper, silver, gold, platinum, nickel, titanium, cobalt, Thallium, tantalum, tungsten, tungsten silicide, titanium tungsten, titanium nitride, nitridation thallium, carbonization thallium, nickel platinum or nitrogen silication thallium.
Embodiment three
Present embodiment discloses another kind of MOS transistor forming method, the profile of each step such as Figure 12- Shown in Figure 19, have employed the boundary layer forming method described in embodiment one equally, concrete forming process is as follows:
As shown in figure 12, it is provided that Semiconductor substrate 300, it is formed with isolation in described Semiconductor substrate 300 District 301 and the active area between isolation area.
Afterwards, described substrate carrying out pre-treatment, described pretreatment process includes: carry out described substrate Chemical cleaning, removes oxide layer and the impurity particle of substrate surface, and it is molten that described Process of Chemical Cleaning uses Liquid is the mixed solution of dilute HF Yu HCl or dilute HF and NH3Mixed solution or dilute HF solution； Substrate after Chemical cleaning is annealed, to repair lattice defect.
As shown in figure 13, enter atomic layer banking process, by described substrate transport a to reaction chamber, Described reaction chamber is passed through the reacting gas comprising hydroxyl, the hydroxyl in described reacting gas and substrate surface Atom by chemical bonds formed intermediate material, shown reacting gas includes H2O gas, D2O gas Body, H2O2Gas, CH3One in OH gas and HCOOH gas or combination；In the reactor chamber with The form of pulse is passed through flushing gas, removes the by-product of described reacting gas and chemical reaction；To described Substrate carries out rapid thermal annealing, removes the protium in intermediate material, forms atom at described substrate surface Layer 302.This process refers to an embodiment, repeats no more here.
As shown in figure 14, repeat the banking process of atomic layer, until the ulking thickness of described atomic layer Reach the target thickness of described boundary layer, obtain described boundary layer 303.
Annealing boundary layer 303, the annealing temperature of this annealing process is higher than atomic layer banking process Gas in annealing temperature, and the atmosphere of this annealing process includes H2、D2、N2、He、Ne、 At least one in Ar and Xe.
As shown in figure 15, chemical vapor deposition method is used to form high K dielectric on boundary layer 303 surface Layer 304, the control raceway groove that act as of described high-K dielectric layer 304 is opened.The material of high-K dielectric layer, Thickness is all similar with a upper embodiment.
With reference to shown in Figure 16, high-K dielectric layer 304 forms replacement gate 305, concrete formation process As follows: in high-K dielectric layer 304, to form polysilicon layer, form photoresist layer on the polysilicon layer；Right Photoresist layer is exposed development, forms gate patterns；With patterning photoresist layer as mask, etching is many Crystal silicon layer, high-K dielectric layer 304 and boundary layer 303 are to exposing Semiconductor substrate 300.
In other embodiments, before forming replacement gate 305, can in high-K dielectric layer 304 first Form one layer of metal mask layer with titanium nitride as material, during follow-up removal replacement gate 305 As etching stop layer, protect following high-K dielectric layer 304 from the impact of etch carrier.
With reference to Figure 17, with replacement gate 305 as mask, described Semiconductor substrate 300 is carried out shallow doping District is injected, and forms lightly doped drain 306, afterwards at replacement gate 305 both sides formation side wall 307, and with The side wall 307 of replacement gate 305 and replacement gate both sides is mask, in described Semiconductor substrate 300 Carry out heavily doped region injection, form source electrode 308a and drain electrode 308b.The present embodiment is formed the process of source and drain Similar with a upper embodiment, repeat no more here.
With reference to Figure 18, chemical vapor deposition method is used to form interlayer dielectric layer 309 on the surface of a substrate, The interlayer dielectric layer just having completed deposition covers replacement gate, uses CMP to grind inter-level dielectric afterwards Layer, until exposing replacement gate top.
With continued reference to Figure 18, with described interlayer dielectric layer 309 as mask, carve by dry etching method or wet method Etching technique removes described replacement gate structure, forms groove 310.
As shown in figure 19, in described groove, fill up metal, form metal gates 311, wherein metal gate The forming process of pole 311, concrete structure, material selection etc. are all similar with a upper embodiment.
Embodiment four
Present embodiment discloses a kind of MOS transistor, use both the above MOS transistor forming method Being made, the boundary layer that this MOS transistor has in HKMG structure, and this MOS transistor is adopted With described in embodiment one method formed, this boundary layer between Semiconductor substrate and high-K dielectric layer, The boundary layer that its consistency is formed more than common process, described common process is thermal oxidation technology and chemical oxygen Metallization processes.
Embodiment five
Present embodiment discloses a kind of oxide layer forming method, this oxide layer can be that semiconductor device is formed During any oxide layer, including: provide Semiconductor substrate；Enter atomic layer banking process, first By in described substrate transport a to reaction chamber, described reaction chamber is passed through the reacting gas comprising hydroxyl, Hydroxyl in described reacting gas forms intermediate material with the atom of substrate surface by chemical bonds；It The described reacting gas of rear removing, specifically, be passed through flushing gas in described reaction chamber, described to remove Reacting gas, described flushing gas includes He, N2, at least one in Ne, Ar and Xe；To described Substrate carries out rapid thermal annealing, removes the protium in described intermediate material, is formed at described substrate surface Atomic layer, the annealing temperature of this rapid thermal anneal process is 500 DEG C-1100 DEG C, and annealing time is 1ms-100 μs；Repeat atomic layer banking process, until the ulking thickness of described atomic layer reaches described oxide layer Target thickness, obtain described oxide layer.
The reacting gas of atomic layer banking process is H2O gas, D2O gas, H2O2Gas, CH3OH At least one in gas and HCOOH gas.
Further, before entering atomic layer banking process, also Semiconductor substrate can be carried out pre-treatment, before this Processing procedure includes: semiconductor substrate surface carries out Chemical cleaning, removes the autoxidation of substrate surface Layer and impurity particle, described Process of Chemical Cleaning use the mixed solution that solution is dilute HF Yu HCl, Or dilute HF and NH3Mixed solution or dilute HF solution；Substrate after Chemical cleaning is moved back Fire, to repair lattice defect.
After completing atomic layer banking process, also Semiconductor substrate can be carried out post processing, this post processing Cheng Wei, anneals to the oxide layer formed, makes oxide layer finer and close, revise the lattice of substrate simultaneously Defect, the annealing temperature of this annealing process is higher than the annealing temperature of atomic layer banking process, and this is annealed Gas in the atmosphere of journey includes H2、D2、N2, at least one in He, Ne, Ar and Xe.
Atomic layer banking process execution capable of circulation in the present embodiment 1-1000 time, the oxidated layer thickness of formation Can be The oxide layer formed in the present embodiment and conventional thermal oxidation technique and chemical oxidation process shape The oxide layer become is compared, and uniformity and compactness are better.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses The present invention.Multiple amendment to these embodiments will be aobvious and easy for those skilled in the art See, generic principles defined herein can without departing from the spirit or scope of the present invention, Realize in other embodiments.Therefore, the present invention is not intended to be limited to embodiment illustrated herein, and It is to fit to the widest scope consistent with principles disclosed herein and features of novelty.

Claims (22)

1. a HKMG structure median surface layer forming method, described boundary layer be positioned at Semiconductor substrate and Between high-K dielectric layer, it is characterised in that including:
A) providing Semiconductor substrate, described substrate includes unsaturation silicon atom；
B) reacting gas comprising hydroxyl and described substrate surface contact, the hydroxyl in described reacting gas are used The atom of base and substrate surface forms intermediate material by chemical bonds, described intermediate material be described instead The hydroxyl in gas is answered to be combined-Si-OH the dangling bonds formed with the unsaturation silicon atom of substrate surface；
C) described reacting gas is removed；
D) described substrate is annealed, remove the protium in described intermediate material, at described substrate table Face forms atomic layer；
E) step b)-step d) is repeated, until the ulking thickness of described atomic layer reaches described boundary layer Target thickness, obtains described boundary layer.
Boundary layer forming method the most according to claim 1, it is characterised in that described reacting gas For H2O gas, D2O gas, H2O2Gas, CH3In OH gas and HCOOH gas at least A kind of.
Boundary layer forming method the most according to claim 1, it is characterised in that in step c), The mode removing described reacting gas is: be passed through flushing gas in reaction chamber, to remove described reaction gas Body.
Boundary layer forming method the most according to claim 3, it is characterised in that described flushing gas Including: He, N2, at least one in Ne, Ar and Xe.
Boundary layer forming method the most according to claim 1, it is characterised in that in step d) Annealing process is rapid thermal anneal process.
Boundary layer forming method the most according to claim 5, it is characterised in that described Rapid Thermal is moved back The annealing temperature of ignition technique is 500 DEG C-1100 DEG C, and annealing time is 1ms-100 μ s.
Boundary layer forming method the most according to claim 6, it is characterised in that described Rapid Thermal is moved back Gas in the atmosphere of ignition technique includes: H2、D2、N2, in He, Ne, Ar and Xe at least A kind of.
Boundary layer forming method the most according to claim 1, it is characterised in that in step e), The number of times repeating step b)-step d) is 1-1000 time, and the target thickness of described boundary layer is
Boundary layer forming method the most according to claim 1, it is characterised in that in step a) and Also including between step b), described substrate carries out pre-treatment, and described pretreatment process includes:
Described substrate carries out Chemical cleaning, and the solution that described Process of Chemical Cleaning uses is HF and HCl Mixed solution or HF and NH3Mixed solution or HF solution.
Boundary layer forming method the most according to claim 9, it is characterised in that described pre-treatment Process also includes: anneal the substrate after Chemical cleaning.
11. boundary layer forming methods according to claim 10, it is characterised in that described annealed Gas in the atmosphere of journey includes: H2、D2、N2、NH3With at least one in He.
12. boundary layer forming methods according to claim 10, it is characterised in that in step e) The most also including, anneal described boundary layer, the annealing temperature of this annealing process is higher than in step d) Annealing temperature, and the gas in the atmosphere of this annealing process includes H2、D2、N2、He、Ne、 At least one in Ar and Xe.
13. boundary layer forming methods according to claim 1, it is characterised in that described quasiconductor Substrate is plane or non-planar substrate, and the material of described Semiconductor substrate is Si, SiGe or SiC.
14. boundary layer forming methods according to claim 13, it is characterised in that described on-plane surface Fin type transistor structure or nanowire crystal tubular construction is included on type substrate.
15. 1 kinds of MOS transistor forming methods, have employed the boundary described in any one of claim 1-14 Surface layer forming method, it is characterised in that this MOS transistor forming method includes:
A) provide Semiconductor substrate, form replacement gate structure at described substrate surface；
B) with replacement gate structure as mask, in substrate, source/drain is formed；
C) formation interlayer dielectric layer on described substrate surface, and described interlayer dielectric layer surface and alternative gate Electrode structure top flushes；
D) with described interlayer dielectric layer as mask, remove described replacement gate structure, form groove；
E) reacting gas comprising hydroxyl and described substrate surface contact, the hydroxyl in described reacting gas are used Base forms intermediate material with the atom of substrate surface by chemical bonds；
F) described reacting gas is removed；
G) described substrate is annealed, remove the protium in described intermediate material, at described substrate table Face forms atomic layer；
H) step e)-step g) is repeated, until the ulking thickness of described atomic layer reaches described boundary layer Target thickness, obtains described boundary layer；
I) on described interface layer surfaces, high-K dielectric layer is formed；
J) on described high-K dielectric layer surface, form the metal gates of the full described groove of filling.
16. MOS transistor forming methods according to claim 15, it is characterised in that in step Suddenly d) and also include between step e): described substrate carries out pre-treatment, and described pretreatment process includes:
Described substrate carries out Chemical cleaning, and the solution that described Process of Chemical Cleaning uses is HF and HCl Mixed solution or HF and NH3Mixed solution or HF solution；
Substrate after Chemical cleaning is annealed.
17. MOS transistor forming methods according to claim 16, it is characterised in that in step Suddenly h) and also include between step i): described boundary layer is annealed, the annealing temperature of this annealing process Degree is higher than the annealing temperature in step d), and the gas in the atmosphere of this annealing process includes H2、 D2、N2, at least one in He, Ne, Ar and Xe.
18. 1 kinds of MOS transistor forming methods, have employed the boundary described in any one of claim 1-14 Surface layer forming method, it is characterised in that this MOS transistor forming method includes:
A) Semiconductor substrate is provided；
B) reacting gas comprising hydroxyl and described substrate surface contact, the hydroxyl in described reacting gas are used Base forms intermediate material with the atom of substrate surface by chemical bonds；
C) described reacting gas is removed；
D) described substrate is annealed, remove the protium in described intermediate material, at described substrate table Face forms atomic layer；
E) step b)-step d) is repeated, until the ulking thickness of described atomic layer reaches described boundary layer Target thickness, obtains described boundary layer；
F) on described interface layer surfaces, high-K dielectric layer is formed；
G) on described high-K dielectric layer surface, replacement gate is formed；
H) with described replacement gate as mask, in substrate surface, source/drain is formed；
I) form interlayer dielectric layer on the surface of a substrate, and described interlayer dielectric layer surface is tied with replacement gate Structure top flushes；
J) with described interlayer dielectric layer as mask, remove described replacement gate structure, form groove；
K) in described groove, fill up metal, form metal gates.
19. 1 kinds of MOS transistors, have the boundary layer in HKMG structure, and this MOS transistor Using the method described in any one of claim 1-14 to be formed, this boundary layer is positioned at Semiconductor substrate and high K Between dielectric layer, the boundary layer that its consistency is formed more than thermal oxidation technology and chemical oxidation process.
20. 1 kinds of oxide layer forming methods, it is characterised in that including:
A) providing Semiconductor substrate, described substrate includes unsaturation silicon atom；
B) reacting gas comprising hydroxyl and described substrate surface contact, the hydroxyl in described reacting gas are used The atom of base and substrate surface forms intermediate material by chemical bonds, described intermediate material be described instead The hydroxyl in gas is answered to be combined-Si-OH the dangling bonds formed with the unsaturation silicon atom of substrate surface, described Reacting gas is H2O gas, D2O gas, H2O2Gas, CH3OH gas and HCOOH gas In at least one；
C) described reacting gas is removed；
D) described substrate is annealed, remove the protium in described intermediate material, at described substrate table Face forms atomic layer；
E) step b)-step d) is repeated, until the ulking thickness of described atomic layer reaches described oxide layer Target thickness, obtains described oxide layer.
21. oxide layer forming methods according to claim 20, it is characterised in that in step c), The mode removing described reacting gas is: be passed through flushing gas in reaction chamber, to remove described reaction gas Body, described flushing gas includes: He, N2, at least one in Ne, Ar and Xe.
22. oxide layer forming methods according to claim 20, it is characterised in that in step d) Annealing process be rapid thermal anneal process, the annealing temperature of this rapid thermal anneal process is 500 DEG C -1100 DEG C, annealing time is 1ms-100 μ s.
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