CN102486999A - Forming method of grid oxidation layer - Google Patents
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- CN102486999A CN102486999A CN2010105693573A CN201010569357A CN102486999A CN 102486999 A CN102486999 A CN 102486999A CN 2010105693573 A CN2010105693573 A CN 2010105693573A CN 201010569357 A CN201010569357 A CN 201010569357A CN 102486999 A CN102486999 A CN 102486999A
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Abstract
The invention provides a forming method of a grid oxidation layer. The forming method comprises the following steps of: providing a substrate, and forming a grid oxide layer on the substrate by a thermal oxidation process, wherein reactive gas in the thermal oxidation process is mixed gas at least containing deuterium. According to the forming method, a deuterium element is introduced into the thermal-oxidation growth process of the grid oxidation layer, silicon dangling bonds in a saturated interface state form silicon-deuterium bonds with stronger combination so as to reduce the silicon dangling bonds positioned in the interface state or replace hydrogen of silicon-hydrogen bonds to further form the silicon-deuterium bonds with stronger combination. Simultaneously, the silicon-deuterium bond energy is more than the silicon-hydrogen bond energy; and under the semiconductor process environment, the silicon-deuterium bonds are not easily broken due to external stress, so that the silicon dangling bonds positioned in the interface state are further reduced, the interface defects are reduced, and further the hot-electron effect is restrained.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of formation method of grid oxic horizon.
Background technology
The integrated circuit especially main devices in the very lagre scale integrated circuit (VLSIC) is metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor is called for short MOS).Integrated circuit is since invention, and its progress on performance and function is advanced by leaps and bounds, and the physical dimension of MOS device constantly dwindling always, and its characteristic size has got into nanoscale at present.
In the scaled process of MOS device, drain voltage does not reduce thereupon, and this just causes the increase of the channel region electric field between source electrode, drain electrode; Under the highfield effect; Electronics can accelerate to the speed than high times of heat movement speed between twice collision, so kinetic energy is very big, and these electronics are called as hot electron; Said hot electron can inject to gate dielectric layer, thereby causes thermoelectronic effect (hot electroneffect).This effect belongs to the small-size effect of device, and said effect can cause gate electrode electric current and Semiconductor substrate electric current, influences the reliability of device and circuit.
Above-mentioned thermoelectronic effect is a key factor that influences MOS device lifetime (TTF): thermoelectronic effect more a little less than, device lifetime is long more; Otherwise thermoelectronic effect is obvious more, and device lifetime is short more.In order to improve MOS device lifetime, need to suppress thermoelectronic effect.For nmos device, thermoelectronic effect is particularly outstanding.Because the main charge carrier of NMOS is an electronics; And the main charge carrier of PMOS is the hole, with the hole relatively, the electronics interface potential barrier between Semiconductor substrate and the gate dielectric layer of jumping over more easily; Thereby make electronics injection grid dielectric layer more easily, cause injury gate dielectric layer.
Publication number is in the one Chinese patent application of CN1393935A a kind of nmos device with pocket (pocket) doped structure to be provided, and has suppressed thermoelectronic effect to a certain extent.Said structure is as shown in Figure 1, comprising: Semiconductor substrate 001 is provided, on said Semiconductor substrate 001, injects the boron ion, form P type trap 002 and channel region (not indicating among the figure); On said Semiconductor substrate 001 surface, form grid oxic horizon 003 and gate electrode 004 successively, the Semiconductor substrate of said gate electrode 004 both sides is source region and drain region; In said source region and drain region, inject indium ion, to form pocket area 005; Continuation is injected phosphonium ion in said source region and drain region, form light doping section 006; Both sides at gate dielectric layer 003 and gate electrode 004 form sidewall 007; At last, mixed deeply in said source region and drain region, to form source electrode 008 and drain electrode 009.
The improvement of prior art mainly is the improvement that concentrates on source-and-drain junction, leaks (LDD) etc. like above-mentioned employing lightly-doped source.Above-mentioned improvement will effectively reduce channel region drain terminal electric field, reduce the charge carrier that is excited, thereby improve thermoelectronic effect.But these improvement do not relate to the minimizing charge carrier catches probability in oxide layer, promptly how effectively to improve the interfacial state in the grid oxic horizon, mainly reduces the interface trap in the said grid oxic horizon, to suppress thermoelectronic effect.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of grid oxic horizon, to improve the thermoelectronic effect of the semiconductor device that prior art forms.
For addressing the above problem, the present invention provides a kind of formation method of grid oxic horizon, comprising:
Substrate is provided, adopts thermal oxidation technology on said substrate, to form gate oxide level, wherein, said thermal oxidation technology is for include the mist of deuterium gas at least.
Optional, the range of flow of said deuterium gas is 1slm～10slm.
Optional, include deuterium gas and oxygen in the said thermal oxidation environment.
Optional, include deuterium gas and nitrous oxide in the said thermal oxidation environment.
Optional, the temperature range of said thermal oxidation environment is 650～1100 ℃, chamber pressure 0.5～780Torr, and the reaction time is about 3～90 seconds.
Optional, also comprise said gate oxide level is carried out nitrogenize.
Optional, said gate oxide level carried out nitrogenize after, also comprise said gate oxide level annealed.
Optional, include deuterium gas at least in the said annealing atmosphere.
Optional, the range of flow of said deuterium gas is 1slm～10slm.
Optional, said annealing temperature is 900～1100 ℃.
Compared with prior art, such scheme has the following advantages: the present invention is used for the saturated silicon dangling bonds that are positioned at interfacial state through in the thermal oxidation environment, introducing deuterium gas, with the silicon-deuterium key that forms, perhaps replaces the hydrogen of si-h bond, to form silicon deuterium key.In semiconductor technology, said silicon-deuterium key is difficult for causing because of the stress of outside the fracture of said silicon-deuterium key, reduces the silicon dangling bonds, further reduces the boundary defect that is positioned at grid oxic horizon, suppresses thermoelectronic effect;
Further, introduce deuterium gas in the anneal environment after thermal oxidation technology, be used for the saturated silicon dangling bonds that are positioned at interfacial state,, perhaps replace the hydrogen of si-h bond, to form silicon deuterium key with the silicon-deuterium key that forms.In semiconductor technology, said silicon-deuterium key is difficult for causing because of the stress of outside the fracture of said silicon-deuterium key, reduces the silicon dangling bonds, further reduces the boundary defect that is positioned at grid oxic horizon, suppresses thermoelectronic effect.
Description of drawings
Fig. 1 is a prior art semiconductor device structure sketch map.
Fig. 2 is that the grid oxic horizon of one embodiment of the invention forms the method flow sketch map.
Fig. 3 to Fig. 8 is the grid oxic horizon formation method structural representation of one embodiment of the invention.
Embodiment
When device dimensions shrink, the correspondingly attenuation simultaneously of the thickness of grid oxic horizon.Yet when reduced down in thickness arrived a certain degree, grid oxic horizon can't provide grid conducting material and the enough electrical insulation of Semiconductor substrate that are positioned at its below because of too thin.More important is that thin grid oxic horizon is easy to let the dopant ion that injects be diffused in the grid oxic horizon.Further,, contain the outstanding key of a large amount of silicon in said grid oxic horizon and the silicon substrate interface, in said grid oxic horizon, form boundary defect, make the silicon dangling bonds be easy to trapped electron, cause thermoelectronic effect through semiconductor process environments; Said silicon dangling bonds also maybe with like the hydrogen bonding in the thermal oxidation technology, said si-h bond a little less than, easy scission of link under extraneous ambient stress still can form the silicon dangling bonds in said grid oxic horizon.
To above-mentioned discovery; The inventor to suppress the angle of thermoelectronic effect, provides a kind of formation method of grid oxic horizon from reducing the boundary defect in the gate oxide level; Comprise: substrate is provided; Adopt thermal oxidation technology on said substrate, to form gate oxide level, wherein, the reacting gas of said thermal oxidation technology is for include the mist of deuterium gas at least.
Formation method with grid is embodiment below, and the formation method of grid oxic horizon of the present invention is described.As shown in Figure 2, the formation method for the grid of one embodiment of the invention comprises:
Step S1 provides substrate, said substrate ion is injected form N type trap or P type trap, and said substrate is carried out prerinse;
Step S2 through thermal oxidation technology, forms grid oxic horizon on said substrate, include the mist of deuterium gas and oxygen in the reacting gas of said thermal oxidation technology, or the mist of deuterium gas and nitrous oxide;
Step S3 carries out nitrogenize to the grid oxic horizon that is positioned on the said substrate;
Step S4 anneals to said grid oxic horizon, and said anneal gas includes deuterium gas at least;
Step S5 forms polysilicon layer on said grid oxic horizon;
Step S6, the patterning etching is positioned at polysilicon layer and the grid oxic horizon on the substrate, to form grid.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth detail in the following description so that make much of the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention does not receive the restriction of following disclosed practical implementation.
Fig. 3 to Fig. 8 is the formation method structural representation of the grid oxic horizon of one embodiment of the invention.
As shown in Figure 3, substrate 200 at first is provided, said substrate 200 is N type substrate or P type substrate, in the present embodiment, said substrate is a N type substrate.Said substrate 200 is carried out ion implantation technology, in said substrate 200, form N type trap or P type trap (not shown), form raceway groove (not shown) and fill spacer medium 210 and isolate active area through shallow trench isolation processing procedure (STI).
Then, adopt hydrofluoric acid (HF) solution of dilution that substrate 200 is carried out prerinse, remove the pollutant and the oxide layer on substrate 200 surfaces.
As shown in Figure 4, through thermal oxidation technology, on said substrate 200, form grid oxic horizon 220, said thermal oxidation environment 300 is for include the mist of deuterium gas at least.The flow of said deuterium gas is 1slm～10slm.
Said thermal oxidation technology can generate (situ stream-generated for the steam original position; ISSG) or rapid thermal oxidation process (RTO); The temperature range that forms said grid oxic horizon 220 is 650～1100 ℃, and the thickness of said grid oxic horizon 220 is 1～18 dust.
In the present embodiment, said thermal oxidation technology is rapid thermal oxidation process (RTO).In the RTO chamber, utilize irradiator Fast Heating and dry substrate 200 surfaces, under oxygen atmosphere, to form grid oxic horizon 220.Except that oxygen, at least also include deuterium gas in the said thermal oxidation environment.
Except that oxygen, deuterium gas, can also include nitrous oxide in the said thermal oxidation environment.In the present embodiment, for including the mist of oxygen and deuterium gas, said mist has the overall flow rate of 1～5slm.The temperature range of said thermal oxidation environment is 650～1100 ℃, chamber pressure 0.5～780Torr, and the reaction time is about 3～90 seconds.
As other embodiment; The rapid thermal oxidation of said substrate 200 also can utilize the wet method processing procedure to carry out; As: the steam original position generates (situ stream-generated; ISSG), and for example be attended by that overall flow rate is the mist that contains deuterium gas of 1～5slm, also include a kind of or combination in hydrogen or the nitrous oxide in the said mist.In the present embodiment, the temperature range of said thermal oxidation environment is 650～1100 ℃, and chamber pressure is 0.5～780Torr, and the reaction time is about 3～90 seconds.
The present invention is through introducing the deuterium element in the thermal oxide growth process of grid oxic horizon 220; Silicon dangling bonds in the boundary saturation attitude form the stronger silicon deuterium bond energy key of combination, to reduce to be positioned at the silicon dangling bonds of interfacial state; The hydrogen that perhaps replaces si-h bond is to form silicon deuterium key.Silicon-deuterium bond energy is greater than said silicon-hydrogen bond ability simultaneously, and under semiconductor process environments, said silicon-deuterium key is difficult for causing scission of link because of the stress of outside, further reduces the silicon dangling bonds that are positioned at interfacial state, reduces boundary defect, and then the inhibition thermoelectronic effect.
As shown in Figure 5, in nitrogenize environment 310, the grid oxic horizon 220 that is positioned on the substrate 200 is carried out nitrogenize, form silicon oxynitride on said grid oxic horizon 220 surfaces.
With the grid oxic horizon 220 that has same thickness but do not have a silicon oxynitride relatively, the grid oxic horizon 220 with silicon oxynitride has bigger electrical insulation ability.In addition, silicon oxynitride also has the ability that stops dopant ion to be diffused into grid oxic horizon 220.
Said nitriding process can be through uncoupling pecvd nitride (decoupled plasmanitridation; DPN) technology is accomplished; Utilize the formed silicon oxynitride of DPN technology to can be used as the resistance barrier of dopant ion; So the heat treatment step after ion injects, silicon oxynitride will stop that dopant ion diffuses in the grid oxic horizon 220.Said silicon oxynitride can keep the electrical insulation characteristic of grid oxic horizon 220 and prevent the problem that electricity usefulness reduces.Especially, after technology was advanced to the following technical threshold of 60 nanometers, DPN technology had become the indispensable technology of manufacturing semiconductor element.
As shown in Figure 6, in anneal environment 320, substrate 200 to be annealed, the purpose of annealing is to eliminate rete inside, comprises the defective and the internal stress of grid oxic horizon 220, reduces resistivity.Its principle is that the atom in the film can redistribute under heat effect and makes defective disappear.
Continuation is with reference to figure 6; At least include deuterium gas in the said annealing atmosphere 320, it is following to the reason in the anneal environment to introduce said deuterium gas: through in annealing atmosphere 320, introducing the deuterium element, the silicon dangling bonds in the boundary saturation attitude; Form and combine stronger silicon deuterium key; To reduce to be positioned at the silicon dangling bonds of interfacial state, perhaps replace the hydrogen of si-h bond, to form silicon deuterium key.Silicon-deuterium bond energy is greater than said silicon-hydrogen bond ability simultaneously, and under semiconductor process environments, said silicon-deuterium key is difficult for causing scission of link because of the stress of outside, further reduces the silicon dangling bonds that are positioned at interfacial state, reduces boundary defect, and then the inhibition thermoelectronic effect.
In the present embodiment, saidly be annealed into a step and accomplish, except that deuterium gas, can also include nitrogen or inert gas in the said annealing atmosphere 320, said annealing temperature is 900～1100 ℃, and annealing time is 60～120S.Preferably, said annealing temperature is 1000 ℃, and annealing time is 100S.
In the present embodiment; Said annealing process is that a step annealing is accomplished; As other embodiment, said annealing process can also be divided into for two steps to carry out: at first in the annealing atmosphere of gentleness, anneal, to encrypt the grid oxic horizon 220 after the nitrogenize; Said annealing atmosphere includes deuterium gas at least, and said annealing temperature is 900～1050 ℃; The annealing second time is carried out in then raise annealing temperature to 1000～1100 ℃, includes deuterium gas at least in the said annealing atmosphere.
As preferred embodiment, nitriding process and annealing process carry out in continuous two reative cells of (in situ) board in position.Can save the transmission blanking time that semiconductor device is sent to the equipment that can only carry out annealing process from the equipment that can only carry out nitriding process like this.Therefore the annealing of original position board can improve output, and satisfies behind the nitriding process and the restriction of the stand-by period between next technology (like polysilicon deposition).
As shown in Figure 7, on the grid oxic horizon after the nitrogenize 220, form polysilicon layer 240, said polysilicon 240 formation methods can be chemical vapour deposition technique.
As shown in Figure 8, to said grid oxic horizon 220 and polysilicon layer 240 patternings, and said grid oxic horizon 220 of etching and polysilicon layer 240 successively, form grid.Particularly, on said polysilicon layer 240, forming the photoresist layer (not shown) of patterning, is mask with said photoresist layer, and said grid oxic horizon 220 of etching and polysilicon layer 240 form grid successively.
The present invention is used for the saturated silicon dangling bonds that are positioned at interfacial state through in the thermal oxidation environment, introducing deuterium gas, with the silicon-deuterium key that forms, perhaps replaces the hydrogen of si-h bond, to form silicon deuterium key.In semiconductor technology, said silicon-deuterium key is difficult for causing because of the stress of outside the fracture of said silicon-deuterium key, reduces the silicon dangling bonds, further reduces the boundary defect that is positioned at grid oxic horizon, suppresses thermoelectronic effect;
Further, introduce deuterium gas in the annealing process after thermal oxidation technology, be used for the saturated silicon dangling bonds that are positioned at interfacial state,, perhaps replace the hydrogen of si-h bond, to form silicon deuterium key with the silicon-deuterium key that forms.In semiconductor technology, said silicon-deuterium key is difficult for causing because of the stress of outside the fracture of said silicon-deuterium key, reduces the silicon dangling bonds, further reduces the boundary defect that is positioned at grid oxic horizon, suppresses thermoelectronic effect.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. the formation method of a grid oxic horizon is characterized in that, comprising:
Substrate is provided, adopts thermal oxidation technology on said substrate, to form gate oxide level, wherein, the reacting gas of said thermal oxidation technology is for include the mist of deuterium gas at least.
2. according to the formation method of the said grid oxic horizon of claim 1, it is characterized in that the range of flow of said deuterium gas is 1slm～10slm.
3. according to the formation method of the said grid oxic horizon of claim 2, it is characterized in that, include oxygen and deuterium gas in the said thermal oxidation environment.
4. according to the formation method of the said grid oxic horizon of claim 2, it is characterized in that, include nitrous oxide and deuterium gas in the said thermal oxidation environment.
5. according to the formation method of the said grid oxic horizon of claim 4, it is characterized in that the temperature range of said thermal oxidation environment is 650～1100 ℃, chamber pressure 0.5～780Torr, the reaction time is about 3～90 seconds.
6. according to the formation method of the said grid oxic horizon of claim 1, it is characterized in that, also comprise said gate oxide level is carried out nitrogenize.
7. according to the formation method of the said grid oxic horizon of claim 6, it is characterized in that, said gate oxide level is carried out nitrogenize after, also comprise said gate oxide level annealed.
8. according to the formation method of the said grid oxic horizon of claim 7, it is characterized in that, include deuterium gas at least in the said annealing atmosphere.
9. the formation method of said grid oxic horizon according to Claim 8 is characterized in that the range of flow of said deuterium gas is 1slm～10slm.
10. according to the formation method of the said grid oxic horizon of claim 9, it is characterized in that said annealing temperature is 900～1100 ℃.
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| CN106571303B (en) * | 2015-10-13 | 2018-05-04 | 上海新昇半导体科技有限公司 | Semiconductor structure and forming method thereof |
| CN106884203A (en) * | 2015-12-15 | 2017-06-23 | 上海新昇半导体科技有限公司 | The forming method of monocrystal silicon and wafer |
| CN107151817A (en) * | 2016-03-03 | 2017-09-12 | 上海新昇半导体科技有限公司 | The growing method of monocrystalline silicon and its monocrystal silicon of preparation |
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| CN107604429A (en) * | 2016-07-12 | 2018-01-19 | 上海新昇半导体科技有限公司 | The method of czochralski growth monocrystalline silicon |
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| CN109585556B (en) * | 2017-09-29 | 2022-01-04 | 台湾积体电路制造股份有限公司 | Semiconductor device performance improvement |
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| CN109300782A (en) * | 2018-09-30 | 2019-02-01 | 上海华力集成电路制造有限公司 | The manufacturing method of semiconductor devices |
| CN109473439A (en) * | 2018-11-16 | 2019-03-15 | 上海华力微电子有限公司 | A kind of integrated technique of SONOS memory device preparation |
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