CN103515197A - Self-aligned multi-patterning mask layer and formation method thereof - Google Patents
Self-aligned multi-patterning mask layer and formation method thereof Download PDFInfo
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- CN103515197A CN103515197A CN201210214129.3A CN201210214129A CN103515197A CN 103515197 A CN103515197 A CN 103515197A CN 201210214129 A CN201210214129 A CN 201210214129A CN 103515197 A CN103515197 A CN 103515197A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
Abstract
The invention relates to a self-aligned multi-patterning mask layer and a formation method thereof. The formation method comprises the following steps that: a semiconductor substrate is provided and a to-be-etched material layer is formed at the surface of the semiconductor substrate; a sacrificial material layer is formed at the surface of the to-be-etched material layer; etching is carried out on the sacrificial material layer to form a sacrificial layer, wherein the dimension of the portion, approaching the to-be-etched material layer, of the sacrificial layer is smaller than that of the portion, far away from the to-be-etched material layer, of the sacrificial layer; and a side wall is formed at the surface of the side wall of the sacrificial layer, wherein the portions of the two sides of the side wall are inclined towards the middle portion of the side wall from a position at the surface of the to-be-etched material layer to a position far away from the surface of the to-be-etched material layer. Because the portions of the two sides of the side wall are inclined towards the middle portion of the side wall and the profile shapes of the portions of the two sides of the side wall are identical with each other, the shapes of side walls of the to-be-etched material layer formed by etching by using the side wall as the mask subsequently are identical, so that the electrical performance of the semiconductor device that is formed subsequently is not influenced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly mask layer of a kind of autoregistration multiple graphics and forming method thereof.
Background technology
In field of semiconductor manufacture, photoresist material for mask image being transferred to one or more layers material layer, for example, is transferred to mask image in metal level, dielectric layer or Semiconductor substrate.But along with constantly dwindling of the characteristic size of semiconductor technology, the mask pattern that utilizes photoetching process to form small-feature-size in material layer becomes more and more difficult.
In order to improve the integrated level of semiconductor device, industry has proposed multiple double-pattern technique, and wherein, autoregistration double-pattern (Self-Aligned Double Patterning, SADP) technique is wherein a kind of.Publication number is that the american documentation literature of US2009/0146322A1 discloses a kind of autoregistration double-pattern and as mask, semiconductor structure carried out the method for etching, specifically comprises:
Please refer to Fig. 1, on Semiconductor substrate 10 surfaces, form material layer 20 to be etched, on described material layer to be etched 20 surfaces, form sacrificial material layer (not shown), described sacrificial material layer is carried out to etching, form sacrifice layer 30;
Please refer to Fig. 2, at described material layer 20 to be etched and sacrifice layer 30 surfaces, form hard mask material layer 40;
Please refer to Fig. 3, described hard mask material layer 40 is carried out without mask etching, until expose the top surface of described material layer to be etched 20 surfaces and sacrifice layer 30, in described sacrifice layer 30 sidewall surfaces, form side wall 45;
Please refer to Fig. 4, remove described sacrifice layer 30, using described side wall 45 as hard mask layer, described material layer 20 to be etched is carried out to etching.
But utilize above-mentioned autoregistration double-pattern as mask, described material layer 20 to be etched to be carried out after etching, the pattern of the sidewall of the material layer to be etched 20 that described side wall 45 both sides are corresponding is different, can affect the electric property of the semiconductor device of follow-up formation.
Summary of the invention
The problem that the present invention solves is to provide a kind of mask layer of aiming at multiple graphics and forming method thereof, can make the pattern of sidewall of material layer to be etched corresponding to described mask layer both sides identical.
For addressing the above problem, technical solution of the present invention provides a kind of formation method of mask layer of autoregistration multiple graphics, comprising: Semiconductor substrate is provided, at described semiconductor substrate surface, forms material layer to be etched; In described material surface to be etched, form sacrificial material layer; Described sacrificial material layer is carried out to etching, form sacrifice layer, the size of the described sacrifice layer near material layer to be etched is less than the size away from the sacrifice layer of material layer to be etched; At described material layer to be etched and sacrificial layer surface, form hard mask material layer; Described hard mask material layer is carried out without mask etching, in described sacrifice layer sidewall surfaces, form side wall, from material surface to be etched to away from material surface to be etched, the sidewall of described side wall both sides tilts to side wall centre position; Remove described sacrifice layer, described side wall is as the mask layer of autoregistration multiple graphics.
Optionally, described sacrificial material layer is interior doped with foreign ion, and surperficial from material surface to be etched to sacrificial material layer, and the doping content of described foreign ion becomes greatly or gradually and diminishes gradually.
Optionally, the material of described sacrificial material layer is polysilicon, and the foreign ion of described doping is boron ion or phosphonium ion.
Optionally, the surface from material surface to be etched to sacrificial material layer, in described sacrificial material layer, the mole percent level of boron ion increases gradually.
Optionally, the surface from material surface to be etched to sacrificial material layer, in described sacrificial material layer, the mole percent level of phosphonium ion reduces gradually.
Optionally, the material of described sacrificial material layer is amorphous carbon, and the foreign ion of described doping is nitrogen ion, hydrogen ion or silicon atom.
Optionally, the surface from material surface to be etched to sacrificial material layer, in described sacrificial material layer, nitrogen ion or hydrionic mole percent level reduce gradually.
Optionally, the surface from material surface to be etched to sacrificial material layer, in described sacrificial material layer, the mole percent level of silicon atom increases gradually.
Optionally, the material of described sacrificial material layer is silica, and the foreign ion of described doping is boron ion or phosphonium ion.
Optionally, the surface from material surface to be etched to sacrificial material layer, in described sacrificial material layer, the mole percent level of boron ion, phosphonium ion reduces gradually.
Optionally, the material of described sacrificial material layer is SiCO or SiCOH, the surface from material surface to be etched to sacrificial material layer, and in described sacrificial material layer, the mole percent level of carbon reduces gradually.
Optionally, the method of described sacrificial material layer being carried out to etching comprises: on described sacrificial material layer surface, form patterned mask layer, the described patterned mask layer of take is mask, described sacrificial material layer is carried out to anisotropic etching, form sidewall first sacrifice layer vertical with Semiconductor substrate plane; Described the first sacrifice layer sidewall is carried out to isotropic etching, form sacrifice layer, the size of the described sacrifice layer near material layer to be etched is less than the size away from the sacrifice layer of material layer to be etched.
Optionally, when the material of described sacrificial material layer is polysilicon, when the foreign ion of described doping is boron ion or phosphonium ion, described sacrificial material layer is carried out to dry etching, form sidewall first sacrifice layer vertical with Semiconductor substrate plane; The etching solution that utilization contains hydrofluoric acid carries out wet etching to described the first sacrifice layer sidewall, forms described sacrifice layer.
Optionally, when the material of described sacrificial material layer is polysilicon, when the foreign ion of described doping is boron ion or phosphonium ion, described sacrificial material layer is carried out to dry etching, form sidewall first sacrifice layer vertical with Semiconductor substrate plane; Described the first sacrifice layer sidewall is carried out to plasma dry etching, form described sacrifice layer.
Optionally, when the material of described sacrificial material layer is silica, when the foreign ion of described doping is boron ion or phosphonium ion, utilize fluoro-gas to carry out dry etching to described sacrificial material layer, form sidewall first sacrifice layer vertical with Semiconductor substrate plane; The etching solution that utilization contains hydrofluoric acid carries out wet etching to described the first sacrifice layer sidewall, forms described sacrifice layer.
Optionally, when the material of described sacrificial material layer is SiCO or SiCOH, utilize CF
4gas carries out dry etching to described sacrificial material layer, forms sidewall first sacrifice layer vertical with Semiconductor substrate plane; The etching solution that utilization contains hydrofluoric acid carries out wet etching to described the first sacrifice layer sidewall, forms described sacrifice layer.
Optionally, the method of described sacrificial material layer being carried out to etching comprises: on described sacrificial material layer surface, form patterned mask layer, the described patterned mask layer of take is mask, described sacrificial material layer is carried out to plasma etching, form described sacrifice layer, the size of the described sacrifice layer near material layer to be etched is less than the size away from the sacrifice layer of material layer to be etched.
Optionally, when the material of described sacrificial material layer is amorphous carbon, when the foreign ion of described doping is nitrogen ion, hydrogen ion or silicon atom, utilize the plasma of oxygen-containing gas to carry out plasma etching to described sacrificial material layer, form described sacrifice layer.
Optionally, when the material of described sacrificial material layer is polysilicon, when the foreign ion of described doping is boron ion or phosphonium ion, described sacrificial material layer is carried out to plasma etching, form described sacrifice layer, the concrete technology of described plasma etching is: etching gas comprises Cl
2and HBr, radio-frequency power is 500 ~ 1000 watts, biasing radio-frequency power is 200 ~ 500 watts, Cl
2be greater than 0.25 with the molar percentage of HBr.
Optionally, described hard mask material layer is wherein a kind of of silicon oxide layer, titanium nitride layer, tantalum nitride layer, silicon nitride layer, fire sand layer, silicon oxynitride layer, silicon carbide layer, boron nitride layer or several multiple-level stack structure wherein.
Optionally, described material layer to be etched comprises single or multiple lift material layer.
Optionally, described sacrifice layer bottom be of a size of sacrifice layer top size 0.4 ~ 0.95.
Technical solution of the present invention also provides a kind of mask layer that adopts the autoregistration multiple graphics of described formation method formation, comprise: Semiconductor substrate, be positioned at the material layer to be etched of described semiconductor substrate surface, be positioned at the mask layer of described material surface to be etched, from material surface to be etched to away from material surface to be etched, the sidewall of described mask layer both sides tilts to mask layer centre position.
Compared with prior art, the present invention has the following advantages:
The forming process of the mask layer of the autoregistration multiple graphics of the embodiment of the present invention comprises: Semiconductor substrate is provided, at described semiconductor substrate surface, forms material layer to be etched; In described material surface to be etched, form sacrificial material layer; Described sacrificial material layer is carried out to etching, form sacrifice layer, the size of the described sacrifice layer near material layer to be etched is less than the size away from the sacrifice layer of material layer to be etched; At described material layer to be etched and sacrificial layer surface, form hard mask material layer; Described hard mask material layer is carried out without mask etching, in described sacrifice layer sidewall surfaces, form side wall, from material surface to be etched to away from material surface to be etched, the sidewall of described side wall both sides tilts to side wall centre position.Due to from material surface to be etched to away from material surface to be etched, the sidewall of described side wall both sides all tilts to side wall centre position, make because the section shape of the side wall of side wall both sides is identical, making side wall described in later use is that the sidewall pattern of the material layer to be etched that forms of mask etching is identical, can not affect the electric property of the semiconductor device of follow-up formation.
Further, in described sacrificial material layer doped with foreign ion, and the surface from material surface to be etched to sacrificial material layer, the doping content of described foreign ion becomes greatly or gradually and diminishes gradually, because etching technics is to having the etch rate difference of the sacrificial material layer of different levels of doping, make described sacrificial material layer carry out after etching, the size of the described sacrifice layer near material layer to be etched is less than the size away from the sacrifice layer of material layer to be etched.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is that prior art utilizes autoregistration double-pattern as the cross-sectional view of the etching process of mask;
Fig. 5 is the schematic flow sheet of formation method of mask layer of the autoregistration multiple graphics of the embodiment of the present invention;
Fig. 6 to Figure 11 is the cross-sectional view of forming process of mask layer of the autoregistration multiple graphics of the embodiment of the present invention.
Embodiment
Known in background technology, utilize the autoregistration double-pattern of prior art as mask, material layer to be etched to be carried out after etching, the pattern of the sidewall of the material layer to be etched that side wall both sides are corresponding is different, can affect the electric property of the semiconductor device of follow-up formation.Inventor finds through research, the pattern difference of the sidewall of this material layer to be etched is mainly different generation of section shape due to the sidewall of described side wall both sides, side wall sidewall near sacrifice layer one side is vertical with semiconductor substrate surface, but because described side wall carries out forming without mask etching to hard mask material layer, sidewall shape at the side wall away from sacrifice layer one side is arc, from material surface to be etched to away from material surface to be etched, the described side wall sidewall away from sacrifice layer one side tilts to side wall centre position, make the section shape of side wall both sides sidewall different, utilize described side wall as mask layer, material layer to be etched to be carried out after etching, can make the pattern difference of the sidewall of material layer to be etched corresponding to side wall both sides.
In order to address the above problem, inventor has proposed mask layer of a kind of autoregistration multiple graphics and forming method thereof, from material surface to be etched to away from material surface to be etched, the sidewall of described side wall both sides all tilts to mask layer centre position, because the section shape of the side wall of side wall both sides is identical, making side wall described in later use is that the sidewall pattern of the material layer to be etched that forms of mask etching is identical, can not affect the electric property of the semiconductor device of follow-up formation.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that.Therefore the present invention is not subject to the restriction of following public concrete enforcement.
First the embodiment of the present invention provides a kind of formation method of mask layer of autoregistration multiple graphics, please refer to Fig. 5, and the schematic flow sheet for the formation method of the mask layer of the autoregistration multiple graphics of the embodiment of the present invention, specifically comprises:
Step S101, provides Semiconductor substrate, at described semiconductor substrate surface, forms material layer to be etched;
Step S102, in described material surface to be etched, form sacrificial material layer, in-situ doped in described sacrificial material layer have foreign ion, and surperficial from material surface to be etched to sacrificial material layer, and the doping content of described foreign ion becomes greatly or gradually and diminishes gradually;
Step S103, carries out etching to described sacrificial material layer, forms sacrifice layer, and the size of the described sacrifice layer near material layer to be etched is less than the size away from the sacrifice layer of material layer to be etched;
Step S104, forms hard mask material layer at described material layer to be etched and sacrificial layer surface;
Step S105, carries out without mask etching described hard mask material layer, in described sacrifice layer sidewall surfaces, forms side wall, and from material surface to be etched to away from material surface to be etched, the sidewall of described side wall both sides tilts to side wall centre position;
Step S106, removes described sacrifice layer, and described side wall is as the mask layer of autoregistration multiple graphics.
Concrete, please refer to Fig. 6, Semiconductor substrate 100 is provided, on described Semiconductor substrate 100 surfaces, form material layer 110 to be etched.
Described Semiconductor substrate 100 is wherein a kind of such as silicon substrate, germanium substrate, gallium nitride substrate, glass substrate, silicon-on-insulator substrate, germanium substrate on insulator.In the present embodiment, described Semiconductor substrate 100 is silicon substrate.Because those skilled in the art can reasonably select various Semiconductor substrate as required, therefore, the particular type of Semiconductor substrate should not limit the scope of the invention.
Described Semiconductor substrate can also be multiple-level stack structure, can also form one or more layers interlayer dielectric layer (not shown) and interlayer metal layer (not shown) in described Semiconductor substrate.
Described material layer to be etched 110 can be the material layer of monolayer material layer or multiple-level stack.Described material layer to be etched 110 is the multiple-level stack structure of dielectric layer, metal level or wherein one or more of Semiconductor substrate.When described material layer 110 to be etched is one deck, while forming autoregistration multiple graphics, utilize follow-up formation side wall to carry out etching to described one deck material layer 110 to be etched.When described material layer 110 to be etched is multilayer, while forming autoregistration multiple graphics, utilize follow-up formation side wall to carry out etching to described multilayer material layer 110 to be etched.
Please refer to Fig. 7, on described material layer to be etched 110 surfaces, form sacrificial material layer 120.
The height of described sacrificial material layer 120 is corresponding with the height of the side wall of follow-up formation, and the material of described sacrificial material layer 120 is polysilicon, silica, amorphous carbon, SiCO or SiCOH etc.The technique that forms described polysilicon, silica, SiCO or SiCOH is chemical vapor deposition method, such as plasma enhanced chemical vapor deposition technique (PECVD), low-pressure chemical vapor deposition process (LPCVD) etc., the technique that forms described amorphous carbon is sputtering method, cathode arc ion plating method or laser ablation method, owing to forming the known technology that the technique of amorphous carbon is those skilled in the art, at this, be not described further.
When forming polysilicon, silica, amorphous carbon, SiCO or SiCOH, in described polysilicon, silica, amorphous carbon, SiCO or SiCOH also original position doped with foreign ion.
In the present embodiment, the material of described sacrificial material layer 120 is polysilicon, and described polysilicon material layer is interior doped with boron ion, and from material layer to be etched 110 surfaces to sacrificial material layer 120 surfaces, the mole percent level of described boron ion increases gradually.In the present embodiment, the mole percent level scope of the boron ion in the sacrificial material layer 120 on close material layer to be etched 110 surfaces is 0 ~ 2%, and the mole percent level scope of the boron ion on close sacrificial material layer 120 surfaces is 1 ~ 5%.
In other embodiments, when the material of described sacrificial material layer 120 is polysilicon, in described polysilicon material layer, during doped with phosphonium ion, from material layer to be etched 110 surfaces to sacrificial material layer 120 surfaces, the mole percent level of described phosphonium ion reduces gradually.One of them embodiment, the mole percent level scope of the phosphonium ion in the sacrificial material layer 120 on close material layer to be etched 110 surfaces is 1 ~ 5%, the mole percent level scope of the phosphonium ion on close sacrificial material layer 120 surfaces is 0 ~ 2%.
In other embodiments, when the material of described sacrificial material layer 120 is amorphous carbon, described amorphous carbon material layer is interior doped with nitrogen, hydrogen or silicon.In described amorphous carbon material layer, during doped with nitrogen or hydrogen, from material layer to be etched 110 surfaces to sacrificial material layer 120 surfaces, the mole percent level of described nitrogen or hydrogen reduces gradually.One of them embodiment, is 5 ~ 10% near the nitrogen in the sacrificial material layer 120 on material layer to be etched 110 surfaces or the mole percent level scope of hydrogen, near the nitrogen on sacrificial material layer 120 surfaces or the mole percent level scope of hydrogen, is 2 ~ 5%.In described amorphous carbon material layer, during doped with silicon, from material layer to be etched 110 surfaces to sacrificial material layer 120 surfaces, the mole percent level of described silicon increases gradually.One of them embodiment, the mole percent level scope of the silicon in the sacrificial material layer 120 on close material layer to be etched 110 surfaces is 0 ~ 2%, the mole percent level scope of the silicon on close sacrificial material layer 120 surfaces is 1 ~ 5%.
When the material of described sacrificial material layer 120 is silica, described silica material layer is interior doped with boron ion or phosphonium ion.In described silica material layer, during doped with boron ion or phosphonium ion, from material layer to be etched 110 surfaces to sacrificial material layer 120 surfaces, the mole percent level of described boron ion or phosphonium ion reduces gradually.One of them embodiment, near the boron ion in the sacrificial material layer 120 on material layer to be etched 110 surfaces or the mole percent level scope of phosphonium ion, being 1 ~ 5%, is 0 ~ 2% near the boron ion on sacrificial material layer 120 surfaces or the mole percent level scope of phosphonium ion.
When the material of described sacrificial material layer 120 is SiCO or SiCOH, from material layer to be etched 110 surfaces to sacrificial material layer 120 surfaces, the mole percent level of the carbon in described SiCO or SiCOH material layer reduces gradually.One of them embodiment, from material layer to be etched 110 surfaces to sacrificial material layer 120 surfaces, the mole percent level from 10% to 5% of the carbon in described SiCO or SiCOH material layer.
Please refer to Fig. 8, at described sacrificial material layer 120(, please refer to Fig. 7) patterned the first mask layer 130 of surface formation, described patterned the first mask layer 130 is corresponding to sacrifice layer 125 position, described patterned the first mask layer 130 of take is mask, described sacrificial material layer 120 is carried out to etching, form sacrifice layer 125, the size of the described sacrifice layer 125 near material layer 110 to be etched is less than the size away from the sacrifice layer 125 of material layer 110 to be etched.
Described the first mask layer 130 at least comprises photoresist layer, between described photoresist layer and sacrificial material layer 120, can also be formed with wherein a kind of of silicon oxide layer, titanium nitride layer, tantalum nitride layer, silicon nitride layer, fire sand layer, silicon oxynitride layer, silicon carbide layer, boron nitride layer or several multiple-level stack structure wherein.Utilize chemical wet etching technique to carry out etching to described the first mask layer 130, form described patterned the first mask layer 130.
The etching technics that forms described sacrifice layer 125 can only include dry etch process one time, also can comprise repeatedly dry etch process, also can comprise dry etch process and at least one times wet-etching technology at least one times.
In the present embodiment, when the material of described sacrificial material layer 120 is polysilicon, when the foreign ion of described doping is boron ion, described sacrificial material layer 120 is carried out to plasma etching, form described sacrifice layer 125, the size of the described sacrifice layer 125 near material layer 110 to be etched is less than the size away from the sacrifice layer 125 of material layer 110 to be etched.The concrete technology of described plasma etching is: etching gas comprises Cl
2and HBr, radio-frequency power is 500 ~ 1000 watts, biasing radio-frequency power is 200 ~ 500 watts, Cl
2be greater than 0.25 with the molar percentage of HBr.When from material layer to be etched 110 surfaces to sacrificial material layer 120 surfaces, when in described sacrificial material layer 120, the mole percent level of boron ion increases gradually, the mole percent level negative correlation of the plasma forming due to etching gas to the etch rate of described sacrificial material layer and boron ion, etch rate to described sacrificial material layer reduces gradually, make the size of the described sacrifice layer 125 near material layer 110 to be etched be less than the size away from the sacrifice layer 125 of material layer 110 to be etched, from sacrifice layer 125 surfaces to material layer to be etched 110 surfaces, the sidewall of described sacrifice layer 125 both sides tilts to sacrifice layer 125 centre positions.In the present embodiment, the dimension D 1 of described sacrifice layer 125 bottoms be sacrifice layer 125 tops dimension D 2 0.4 ~ 0.95.Because the bottom size of described sacrifice layer is less than the top dimension of sacrifice layer, the bottom spacing of follow-up two side walls that form in described sacrifice layer both sides also can be less than top spacing, make the size of the material layer to be etched that exposes between described two side walls be less than the size of the first mask layer that photoetching process forms, utilize described side wall can define the size less than litho pattern, be conducive to dwindle the size of semiconductor structure, improve integrated level.
In other embodiments, when the material of described sacrificial material layer is polysilicon, when the foreign ion of described doping is phosphonium ion, described sacrificial material layer is carried out to plasma etching, form described sacrifice layer, the size of the described sacrifice layer near material layer to be etched is less than the size away from the sacrifice layer of material layer to be etched.The concrete technology of described plasma etching is: etching gas comprises Cl
2and HBr, radio-frequency power is 500 ~ 1000 watts, biasing radio-frequency power is 200 ~ 500 watts, Cl
2be greater than 0.25 with the molar percentage of HBr.Because Cl ion concentration in described etching gas is larger, can improve the isotropic etching of etching gas.When the surface from material surface to be etched to sacrificial material layer, when in described sacrificial material layer, the mole percent level of phosphonium ion reduces gradually, due to the mole percent level positive correlation to the etch rate of described sacrificial material layer and phosphonium ion of the plasma of described etching gas, etch rate to described sacrificial material layer also reduces gradually, make the size of the described sacrifice layer near material layer to be etched be less than the size away from the sacrifice layer of material layer to be etched, from sacrificial layer surface to material surface to be etched, the sidewall of described sacrifice layer both sides tilts to sacrifice layer centre position.
In other embodiments, when the material of described sacrificial material layer is polysilicon, when the foreign ion of described doping is boron ion, described sacrificial material layer is carried out to anisotropic dry etching, form sidewall first sacrifice layer vertical with Semiconductor substrate plane; The etching solution that utilization contains hydrofluoric acid carries out wet etching to described the first sacrifice layer sidewall, forms described sacrifice layer.In an embodiment, the concrete technology of described dry etching comprises: etching gas comprises Cl therein
2and HBr, radio-frequency power is 500 ~ 1000 watts, biasing radio-frequency power is 200 ~ 500 watts, Cl
2be less than 0.25 with the molar percentage of HBr.The described etching solution that contains hydrofluoric acid is the mixed solution of nitric acid and hydrofluoric acid.Because described sacrificial layer surface is formed with mask layer, described wet-etching technology can only carry out etching to sacrifice layer sidewall, when the surface from material surface to be etched to sacrificial material layer, when in described sacrificial material layer, the mole percent level of boron ion increases gradually, and described in contain hydrofluoric acid the mole percent level negative correlation of etching solution to the etch rate of described sacrificial material layer and boron ion, etch rate to described sacrificial material layer reduces gradually, make the size of the described sacrifice layer near material layer to be etched be less than the size away from the sacrifice layer of material layer to be etched, from sacrificial layer surface to material surface to be etched, the sidewall of described sacrifice layer both sides tilts to sacrifice layer centre position.
When the material of described sacrificial material layer is polysilicon, when the foreign ion of described doping is phosphonium ion, described sacrificial material layer is carried out to anisotropic dry etching, form sidewall first sacrifice layer vertical with Semiconductor substrate plane; The etching solution that utilization contains hydrofluoric acid carries out wet etching to described the first sacrifice layer sidewall, forms described sacrifice layer.In an embodiment, the concrete technology of described dry etching comprises: etching gas comprises Cl therein
2and HBr, radio-frequency power is 500 ~ 1000 watts, biasing radio-frequency power is 200 ~ 500 watts, Cl
2be less than 0.25 with the molar percentage of HBr.The described etching solution that contains hydrofluoric acid is the mixed solution of nitric acid and hydrofluoric acid.Because described sacrificial layer surface is formed with mask layer, described wet-etching technology can only carry out etching to sacrifice layer sidewall, when the surface from material surface to be etched to sacrificial material layer, when in described sacrificial material layer, the mole percent level of phosphonium ion reduces gradually, and described in contain hydrofluoric acid the mole percent level positive correlation of etching solution to the etch rate of described sacrificial material layer and phosphonium ion, etch rate to described sacrificial material layer reduces gradually, make the size of the described sacrifice layer near material layer to be etched be less than the size away from the sacrifice layer of material layer to be etched, from sacrificial layer surface to material surface to be etched, the sidewall of described sacrifice layer both sides tilts to sacrifice layer centre position.
In other embodiments, after forming the first sacrifice layer that sidewall is vertical with Semiconductor substrate plane, described the first sacrifice layer sidewall is carried out to plasma etching, form described sacrifice layer.Described plasma etch process specifically comprises: etching gas comprises Cl
2or CF
4, radio-frequency power is 500 ~ 1000 watts, biasing radio-frequency power is 0 ~ 50 watt.Because described sacrificial layer surface is formed with mask layer, described plasma etch process can only be carried out etching to sacrifice layer sidewall, when the surface from material surface to be etched to sacrificial material layer, when in described sacrificial material layer, the mole percent level of boron ion increases gradually, and described Cl
2or CF
4the mole percent level negative correlation of plasma to the etch rate of described sacrificial material layer and boron ion, etch rate to described sacrificial material layer reduces gradually, make the size of the described sacrifice layer near material layer to be etched be less than the size away from the sacrifice layer of material layer to be etched, from sacrificial layer surface to material surface to be etched, the sidewall of described sacrifice layer both sides tilts to sacrifice layer centre position.When the surface from material surface to be etched to sacrificial material layer, when in described sacrificial material layer, the mole percent level of phosphonium ion reduces gradually, and described Cl
2or CF
4the mole percent level positive correlation of plasma to the etch rate of described sacrificial material layer and phosphonium ion, etch rate to described sacrificial material layer reduces gradually, make the size of the described sacrifice layer near material layer to be etched be less than the size away from the sacrifice layer of material layer to be etched, from sacrificial layer surface to material surface to be etched, the sidewall of described sacrifice layer both sides tilts to sacrifice layer centre position.
In other embodiments, the material of described sacrificial material layer is amorphous carbon, when the foreign ion of described doping is nitrogen ion, hydrogen ion or silicon atom, utilize the plasma of oxygen-containing gas to carry out plasma etching to described sacrificial material layer, form described sacrifice layer.Described oxygen-containing gas is the mist of oxygen, carbon monoxide, wherein one or more of sulfur dioxide.When the surface from material surface to be etched to sacrificial material layer, when in described sacrificial material layer, nitrogen ion or hydrionic mole percent level reduce gradually, and the plasma of described oxygen-containing gas is to the etch rate of described sacrificial material layer and nitrogen ion or hydrionic mole percent level positive correlation, etch rate to described sacrificial material layer reduces gradually, make the size of the described sacrifice layer near material layer to be etched be less than the size away from the sacrifice layer of material layer to be etched, from sacrificial layer surface to material surface to be etched, the sidewall of described sacrifice layer both sides tilts to sacrifice layer centre position.When the surface from material surface to be etched to sacrificial material layer, when in described sacrificial material layer, the mole percent level of silicon atom increases gradually, and the mole percent level negative correlation of the plasma of described oxygen-containing gas to the etch rate of described sacrificial material layer and silicon atom, etch rate to described sacrificial material layer reduces gradually, make the size of the described sacrifice layer near material layer to be etched be less than the size away from the sacrifice layer of material layer to be etched, from sacrificial layer surface to material surface to be etched, the sidewall of described sacrifice layer both sides tilts to sacrifice layer centre position.
In other embodiments, when the material of described sacrificial material layer is silica, when the foreign ion of described doping is boron ion or phosphonium ion, described sacrificial material layer is carried out to anisotropic dry etching, form sidewall first sacrifice layer vertical with Semiconductor substrate plane; The etching solution that utilization contains hydrofluoric acid carries out wet etching to described the first sacrifice layer sidewall, forms described sacrifice layer.In an embodiment, the etching gas that described sacrificial material layer is carried out to dry etching is fluoro-gas, specifically comprises: CF therein
4, CHF
3, C
4f
8deng.When the surface from material surface to be etched to sacrificial material layer, boron ion in described sacrificial material layer, when the mole percent level of phosphonium ion reduces gradually, because the etching solution that contains hydrofluoric acid is to the etch rate of described sacrificial material layer and boron ion, the mole percent level positive correlation of phosphonium ion, etch rate to described sacrificial material layer also reduces gradually, make the size of the described sacrifice layer near material layer to be etched be less than the size away from the sacrifice layer of material layer to be etched, from sacrificial layer surface to material surface to be etched, the sidewall of described sacrifice layer both sides tilts to sacrifice layer centre position.
In other embodiments, when the material of described sacrificial material layer is SiCO or SiCOH, described sacrificial material layer is carried out to anisotropic dry etching, form sidewall first sacrifice layer vertical with Semiconductor substrate plane; The etching solution that utilization contains hydrofluoric acid carries out wet etching to described the first sacrifice layer sidewall, forms described sacrifice layer.In an embodiment, the etching gas that described sacrificial material layer is carried out to dry etching is CF therein
4.When the surface from material surface to be etched to sacrificial material layer, when in described sacrificial material layer, the mole percent level of carbon reduces gradually, due to the mole percent level positive correlation of the etching solution that contains hydrofluoric acid to the etch rate of described sacrificial material layer and carbon, etch rate to described sacrificial material layer reduces gradually, make the size of the described sacrifice layer near material layer to be etched be less than the size away from the sacrifice layer of material layer to be etched, from sacrificial layer surface to material surface to be etched, the sidewall of described sacrifice layer both sides tilts to sacrifice layer centre position.
Please refer to Fig. 9, at described material layer 110 to be etched and sacrifice layer 125 surfaces, form hard mask material layer 140.
Before forming described hard mask material layer 140, remove described the first mask layer 130(and please refer to Fig. 8).
Described hard mask material layer 140 is wherein a kind of of silicon oxide layer, titanium nitride layer, tantalum nitride layer, silicon nitride layer, fire sand layer, silicon oxynitride layer, silicon carbide layer, boron nitride layer or several multiple-level stack structure wherein.In the present embodiment, described hard mask material layer 140 is silicon nitride layer.The technique that forms described hard mask material layer 140 is chemical vapor deposition method or physical gas-phase deposition.The material of described hard mask material layer 140 is different from the material of material layer 110 to be etched, sacrifice layer 125, and has higher etching selection ratio, makes can not lose in the same time side wall and material layer to be etched at subsequent technique when removing sacrifice layer 125.
Please refer to Figure 10, described hard mask material layer 140(be please refer to Fig. 9) carry out without mask etching, in described sacrifice layer 125 sidewall surfaces, form side wall 145, from material layer to be etched 110 surfaces to away from material layer to be etched 110 surfaces, the sidewall of described side wall 145 both sides all tilts to side wall 120 centre positions.
When utilizing, without mask etching technique, described hard mask material layer 140 is carried out to etching, the hard mask material layer 140 that is positioned at sacrifice layer 125 sidewall surfaces can form side wall 145, and the sidewall shape away from side wall one side of described sacrifice layer 125 1 sides is arc, from material surface to be etched to away from material surface to be etched, the described side wall sidewall away from sacrifice layer one side tilts to side wall centre position.And because the size of the described sacrifice layer 125 near material layer 110 to be etched is less than the size away from the sacrifice layer 125 of material layer 110 to be etched, from sacrifice layer 125 surfaces to material layer to be etched 110 surfaces, the sidewall of described sacrifice layer 125 both sides tilts to sacrifice layer 125 centre positions, make from material layer to be etched 110 surfaces to sacrifice layer 125 surfaces, side wall sidewall near described sacrifice layer 125 1 sides also tilts to side wall centre position, thereby the side wall sidewall of described side wall 145 both sides is all tilted to side wall centre position.When subsequent technique utilizes described side wall 145, for mask, material layer 110 to be etched is carried out to etching, because the section shape of the side wall of side wall 145 both sides is identical, make the sidewall pattern of the material layer to be etched 110 that side wall 145 described in later use forms for mask etching identical, can not affect the electric property of the semiconductor device of follow-up formation.
Please refer to Figure 11, remove described sacrifice layer 125(with reference to Figure 10), described side wall 145 is as the mask layer of autoregistration multiple graphics.
The technique of removing described sacrifice layer 125 is wet etching, and described wet etching solution has high etching selection ratio, when removing described sacrifice layer 125, can etching described in side wall 145.In the present embodiment, described wet etching is hydrofluoric acid.
In subsequent technique, the described side wall 145 of take is mask, and described material layer 110 to be etched is carried out to etching, by the graph transfer printing of described side wall 145 in material layer 110 to be etched.
The embodiment of the present invention also provides a kind of mask that utilizes the autoregistration multiple graphics of above-mentioned formation method formation, please refer to Figure 11, cross-sectional view for the mask of the autoregistration multiple graphics of the embodiment of the present invention, comprise: Semiconductor substrate 100, be positioned at the material layer to be etched 110 on described Semiconductor substrate 100 surfaces, be positioned at the side wall 145 on described material layer to be etched 110 surfaces, described side wall 145 is as the mask layer of subsequent etching material layer 110 to be etched, from material layer to be etched 110 surfaces to away from material layer to be etched 110 surfaces, the sidewall of described mask layer both sides tilts to mask layer centre position.
To sum up, the forming process of the mask layer of the autoregistration multiple graphics of the embodiment of the present invention comprises: Semiconductor substrate is provided, at described semiconductor substrate surface, forms material layer to be etched; In described material surface to be etched, form sacrificial material layer; Described sacrificial material layer is carried out to etching, form sacrifice layer, the size of the described sacrifice layer near material layer to be etched is less than the size away from the sacrifice layer of material layer to be etched; At described material layer to be etched and sacrificial layer surface, form hard mask material layer; Described hard mask material layer is carried out without mask etching, in described sacrifice layer sidewall surfaces, form side wall, from material surface to be etched to away from material surface to be etched, the sidewall of described side wall both sides tilts to side wall centre position.Due to from material surface to be etched to away from material surface to be etched, the sidewall of described side wall both sides all tilts to side wall centre position, make because the section shape of the side wall of side wall both sides is identical, making side wall described in later use is that the sidewall pattern of the material layer to be etched that forms of mask etching is identical, can not affect the electric property of the semiconductor device of follow-up formation.
Further, in described sacrificial material layer doped with foreign ion, and the surface from material surface to be etched to sacrificial material layer, the doping content of described foreign ion becomes greatly or gradually and diminishes gradually, because etching technics is to having the etch rate difference of the sacrificial material layer of different levels of doping, make described sacrificial material layer carry out after etching, the size of the described sacrifice layer near material layer to be etched is less than the size away from the sacrifice layer of material layer to be etched.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (23)
1. a formation method for the mask layer of autoregistration multiple graphics, is characterized in that, comprising:
Semiconductor substrate is provided, at described semiconductor substrate surface, forms material layer to be etched;
In described material surface to be etched, form sacrificial material layer;
Described sacrificial material layer is carried out to etching, form sacrifice layer, the size of the described sacrifice layer near material layer to be etched is less than the size away from the sacrifice layer of material layer to be etched;
At described material layer to be etched and sacrificial layer surface, form hard mask material layer;
Described hard mask material layer is carried out without mask etching, in described sacrifice layer sidewall surfaces, form side wall, from material surface to be etched to away from material surface to be etched, the sidewall of described side wall both sides tilts to side wall centre position;
Remove described sacrifice layer, described side wall is as the mask layer of autoregistration multiple graphics.
2. the formation method of the mask layer of autoregistration multiple graphics as claimed in claim 1, it is characterized in that, described sacrificial material layer is interior doped with foreign ion, and surperficial from material surface to be etched to sacrificial material layer, and the doping content of described foreign ion becomes greatly or gradually and diminishes gradually.
3. the formation method of the mask layer of autoregistration multiple graphics as claimed in claim 2, is characterized in that, the material of described sacrificial material layer is polysilicon, and the foreign ion of described doping is boron ion or phosphonium ion.
4. the formation method of the mask layer of autoregistration multiple graphics as claimed in claim 3, is characterized in that, the surface from material surface to be etched to sacrificial material layer, and in described sacrificial material layer, the mole percent level of boron ion increases gradually.
5. the formation method of the mask layer of autoregistration multiple graphics as claimed in claim 3, is characterized in that, the surface from material surface to be etched to sacrificial material layer, and in described sacrificial material layer, the mole percent level of phosphonium ion reduces gradually.
6. the formation method of the mask layer of autoregistration multiple graphics as claimed in claim 2, is characterized in that, the material of described sacrificial material layer is amorphous carbon, and the foreign ion of described doping is nitrogen, hydrogen or silicon.
7. the formation method of the mask layer of autoregistration multiple graphics as claimed in claim 6, is characterized in that, the surface from material surface to be etched to sacrificial material layer, and in described sacrificial material layer, nitrogen ion or hydrionic mole percent level reduce gradually.
8. the formation method of the mask layer of autoregistration multiple graphics as claimed in claim 6, is characterized in that, the surface from material surface to be etched to sacrificial material layer, and in described sacrificial material layer, the mole percent level of silicon atom increases gradually.
9. the formation method of the mask layer of autoregistration multiple graphics as claimed in claim 2, is characterized in that, the material of described sacrificial material layer is silica, and the foreign ion of described doping is boron ion or phosphonium ion.
10. the formation method of the mask layer of autoregistration multiple graphics as claimed in claim 9, is characterized in that, the surface from material surface to be etched to sacrificial material layer, and in described sacrificial material layer, the mole percent level of boron ion or phosphonium ion reduces gradually.
The formation method of the mask layer of 11. autoregistration multiple graphics as claimed in claim 1, it is characterized in that, the material of described sacrificial material layer is SiCO or SiCOH, the surface from material surface to be etched to sacrificial material layer, in described sacrificial material layer, the mole percent level of carbon reduces gradually.
The formation method of the mask layer of 12. autoregistration multiple graphics as claimed in claim 1, it is characterized in that, the method of described sacrificial material layer being carried out to etching comprises: on described sacrificial material layer surface, form patterned mask layer, the described patterned mask layer of take is mask, described sacrificial material layer is carried out to anisotropic etching, form sidewall first sacrifice layer vertical with Semiconductor substrate plane; Described the first sacrifice layer sidewall is carried out to isotropic etching, form sacrifice layer, the size of the described sacrifice layer near material layer to be etched is less than the size away from the sacrifice layer of material layer to be etched.
The formation method of the mask layer of 13. autoregistration multiple graphics as claimed in claim 12, it is characterized in that, when the material of described sacrificial material layer is polysilicon, when the foreign ion of described doping is boron ion or phosphonium ion, described sacrificial material layer is carried out to dry etching, form sidewall first sacrifice layer vertical with Semiconductor substrate plane; The etching solution that utilization contains hydrofluoric acid carries out wet etching to described the first sacrifice layer sidewall, forms described sacrifice layer.
The formation method of the mask layer of 14. autoregistration multiple graphics as claimed in claim 12, it is characterized in that, when the material of described sacrificial material layer is polysilicon, when the foreign ion of described doping is boron ion or phosphonium ion, described sacrificial material layer is carried out to dry etching, form sidewall first sacrifice layer vertical with Semiconductor substrate plane; Described the first sacrifice layer sidewall is carried out to plasma dry etching, form described sacrifice layer.
The formation method of the mask layer of 15. autoregistration multiple graphics as claimed in claim 12, it is characterized in that, when the material of described sacrificial material layer is silica, when the foreign ion of described doping is boron ion or phosphonium ion, utilize fluoro-gas to carry out dry etching to described sacrificial material layer, form sidewall first sacrifice layer vertical with Semiconductor substrate plane; The etching solution that utilization contains hydrofluoric acid carries out wet etching to described the first sacrifice layer sidewall, forms described sacrifice layer.
The formation method of the mask layer of 16. autoregistration multiple graphics as claimed in claim 12, is characterized in that, when the material of described sacrificial material layer is SiCO or SiCOH, utilizes CF
4gas carries out dry etching to described sacrificial material layer, forms sidewall first sacrifice layer vertical with Semiconductor substrate plane; The etching solution that utilization contains hydrofluoric acid carries out wet etching to described the first sacrifice layer sidewall, forms described sacrifice layer.
The formation method of the mask layer of 17. autoregistration multiple graphics as claimed in claim 1, it is characterized in that, the method of described sacrificial material layer being carried out to etching comprises: on described sacrificial material layer surface, form patterned mask layer, the described patterned mask layer of take is mask, described sacrificial material layer is carried out to plasma etching, form described sacrifice layer, the size of the described sacrifice layer near material layer to be etched is less than the size away from the sacrifice layer of material layer to be etched.
The formation method of the mask layer of 18. autoregistration multiple graphics as claimed in claim 17, it is characterized in that, when the material of described sacrificial material layer is amorphous carbon, when the foreign ion of described doping is nitrogen ion, hydrogen ion or silicon atom, utilize oxygen-containing gas to form plasma described sacrificial material layer is carried out to plasma etching, form described sacrifice layer.
The formation method of the mask layer of 19. autoregistration multiple graphics as claimed in claim 17, it is characterized in that, when the material of described sacrificial material layer is polysilicon, when the foreign ion of described doping is boron ion or phosphonium ion, described sacrificial material layer is carried out to plasma etching, form described sacrifice layer, the concrete technology of described plasma etching is: etching gas comprises Cl
2and HBr, radio-frequency power is 500 ~ 1000 watts, biasing radio-frequency power is 200 ~ 500 watts, Cl
2be greater than 0.25 with the molar percentage of HBr.
The formation method of the mask layer of 20. autoregistration multiple graphics as claimed in claim 1, it is characterized in that, described hard mask material layer is wherein a kind of of silicon oxide layer, titanium nitride layer, tantalum nitride layer, silicon nitride layer, fire sand layer, silicon oxynitride layer, silicon carbide layer, boron nitride layer or several multiple-level stack structure wherein.
The formation method of the mask layer of 21. autoregistration multiple graphics as claimed in claim 1, is characterized in that, described material layer to be etched comprises single or multiple lift material layer.
The formation method of the mask layer of 22. autoregistration multiple graphics as claimed in claim 1, is characterized in that, described sacrifice layer bottom be of a size of sacrifice layer top size 0.4 ~ 0.95.
23. 1 kinds of mask layers that adopt the autoregistration multiple graphics of formation method formation as claimed in claim 1, it is characterized in that, comprise: Semiconductor substrate, be positioned at the material layer to be etched of described semiconductor substrate surface, be positioned at the mask layer of described material surface to be etched, from material surface to be etched to away from material surface to be etched, the sidewall of described mask layer both sides tilts to mask layer centre position.
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| CN114068309B (en) * | 2020-07-29 | 2023-01-20 | 长鑫存储技术有限公司 | Method for forming high density pattern |
| WO2022022035A1 (en) * | 2020-07-29 | 2022-02-03 | 长鑫存储技术有限公司 | Method for forming high density pattern |
| US11929255B2 (en) | 2020-07-29 | 2024-03-12 | Changxin Memory Technologies, Inc. | Method of high-density pattern forming |
| CN113421826A (en) * | 2021-06-18 | 2021-09-21 | 南京大学 | Atomic-level precision lossless layer-by-layer etching method for two-dimensional layered material |
| CN113421826B (en) * | 2021-06-18 | 2024-02-09 | 南京大学 | Atomic-level precision lossless layer-by-layer etching method for two-dimensional layered material |
| CN114093755A (en) * | 2021-11-15 | 2022-02-25 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
| CN114093755B (en) * | 2021-11-15 | 2024-05-03 | 长鑫存储技术有限公司 | Semiconductor structure and forming method thereof |
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