CN103475353A - Double-end-to-single-end circuit - Google Patents
Double-end-to-single-end circuit Download PDFInfo
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- CN103475353A CN103475353A CN2013103958592A CN201310395859A CN103475353A CN 103475353 A CN103475353 A CN 103475353A CN 2013103958592 A CN2013103958592 A CN 2013103958592A CN 201310395859 A CN201310395859 A CN 201310395859A CN 103475353 A CN103475353 A CN 103475353A
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- nmos transistor
- nmos pipe
- grid
- grid electrode
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Abstract
The invention discloses a double-end-to-single-end circuit. The double-end-to-single-end circuit is composed of a first NMOS transistor and a second NMOS transistor, wherein a source electrode of the first NMOS transistor is connected with a threshold voltage VAA, and a drain electrode of the first NMOS transistor is connected with a source electrode of the second NMOS transistor through an output voltage Vout; a drain electrode of the second NMOS transistor is connected with an output interface, and a grid electrode of the first NMOS transistor and a grid electrode of the second NMOS transistor are connected with a differential signal VIP and a differential signal VIN respectively; the grid electrode of the first NMOS transistor and the grid electrode of the second NMOS transistor are respectively connected with a capacitor in series; a resistor is arranged between the capacitor and the grid electrode of the first NMOS transistor in a parallel connection mode, a resistor is arranged between the capacitor and the grid electrode of the second NMOS transistor in a parallel connection mode, and the resistors are connected with a reference voltage Vbias. The double-end-to-single-end circuit is not provided with a current mirror and is suitable for a high-speed circuit; the direct current bias of the first NMOS transistor and the direct current bias of the second NMOS transistor can be adjusted separately, and therefore flexible adjustment of an duty ratio, the time of a rising edge and a falling edge at the time of output and the like can be realized.
Description
Technical field
The present invention relates to a kind of circuit, relate in particular to a kind of both-end and turn single-end circuit.
Background technology
existing both-end turns the general differential signal VIP that only uses of single-end circuit, the input of differential signal VIN, not by practicality, is therefore wasted the existing power consumption of input signal, in addition on the one hand, the duty ratio of output signal is not fine, and the duty ratio of output is relevant with the threshold voltage of NMOS pipe to a certain extent.Also have in addition two kinds of both-ends to turn single-end circuit, but it is not suitable for the height circuit, and the delay of differential signal VIP and VIN and time of delay of postponing paraphase be difficult to accomplish consistent, the rising of output, trailing edge speed are affected.
Summary of the invention
Technical problem to be solved by this invention is, a kind of applicable high speed circuit is provided, and the both-end that the rising of output, trailing edge time can be adjusted flexibly turns single-end circuit.
In order to solve the problems of the technologies described above, the present invention is achieved by the following technical solutions: a kind of both-end list shifting circuit, by a NMOS pipe and the 2nd NMOS pipe, formed, the source electrode connection valve threshold voltage VAA of a described NMOS pipe, drain electrode connects the source electrode of the 2nd NMOS pipe by output voltage V out, the drain electrode of the 2nd NMOS pipe connects output interface, and a described NMOS pipe is connected respectively differential signal VIP, VIN with the grid of the 2nd NMOS pipe.
Preferably, on the grid of a described NMOS pipe and the 2nd NMOS pipe, all be in series with electric capacity, between the electric capacity of a NMOS pipe and the 2nd NMOS pipe and grid, all be parallel with resistance, resistance connects reference voltage Vbias.
Compared with prior art, usefulness of the present invention is: this both-end turns single-end circuit does not have current mirror, is applicable to high speed circuit, and the direct current biasing of a NMOS pipe and the 2nd NMOS pipe can be regulated separately, the duty ratio of realization to output, the rising of output, trailing edge time etc. can be adjusted flexibly.
the accompanying drawing explanation:
Below in conjunction with accompanying drawing, the present invention is further described.
Fig. 1 is that a kind of both-end of the present invention turns single shifting circuit embodiment mono-structural representation;
Fig. 2 is that a kind of both-end of the present invention turns single shifting circuit embodiment mono-structural representation.
In figure: 1, a NMOS pipe; 2, the 2nd NMOS pipe; 3, electric capacity; 4, resistance.
embodiment:
Below in conjunction with the drawings and the specific embodiments, describe the present invention:
Implemented one:
A kind of both-end list shifting circuit shown in Fig. 1, by NMOS pipe the 1 and the 2nd a NMOS pipe 2, formed, the source electrode connection valve threshold voltage VAA of a described NMOS pipe 1, drain electrode connects the source electrode of the 2nd NMOS pipe 2 by output voltage V out, the drain electrode of the 2nd NMOS pipe 2 connects output interface, and a described NMOS pipe 1 is connected respectively differential signal VIP, VIN with the grid of the 2nd NMOS pipe 2.
Embodiment bis-:
A kind of both-end list shifting circuit shown in Fig. 2, by NMOS pipe the 1 and the 2nd a NMOS pipe 2, formed, the source electrode connection valve threshold voltage VAA of a described NMOS pipe 1, drain electrode connects the source electrode of the 2nd NMOS pipe 2 by output voltage V out, the drain electrode of the 2nd NMOS pipe 2 connects output interface, and a described NMOS pipe 1 is connected respectively differential signal VIP, VIN with the grid of the 2nd NMOS pipe 2; All be in series with on the grid of described NMOS pipe the 1 and the 2nd a NMOS pipe 2 between the electric capacity 3 of electric capacity 3, the one NMOS pipe the 1 and the 2nd NMOS pipes 2 and grid and all be parallel with resistance 4, resistance 4 connects reference voltage Vbias.
Particularly, when differential signal VIP becomes large, differential signal VIN diminishes, and the grid voltage of the 2nd NMOS pipe 2 diminishes, and causes the electric current of the 2nd NMOS pipe 2 to diminish, and does not even have.This has reduced output leakage current on the one hand, be convenient to output voltage and raise, therefore the electric current of a NMOS pipe 1 also diminishes on the other hand, causes the grid of a NMOS pipe 1 and the pressure drop between source electrode to reduce, therefore the source class of a NMOS pipe 1 will be followed the grid rising, and more than the grid risen.The source class of the one NMOS pipe 1 is output voltage V out, and grid is differential signal VIP, so output voltage V out will follow differential signal VIP rising.If the load of output is larger electric capacity, output is risen needs large charging current, in this case, the leakage current cut-off of the 2nd NMOS pipe 2, the output charging current is provided by a NMOS pipe 1.Similarly when differential signal VIP diminishes, when differential signal VIN becomes large, NMOS pipe 1 cut-off, the 2nd NMOS manages 2 conductings, and the capacitor discharge to output, cause output voltage V out to diminish.
This both-end turns single-end circuit does not have current mirror, is applicable to high speed circuit, and the direct current biasing of NMOS pipe the 1 and the 2nd a NMOS pipe 2 can be regulated separately, realizes that the rising of output, trailing edge time etc. can be adjusted flexibly to the duty ratio of output.
It is emphasized that: above is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, any simple modification, equivalent variations and modification that every foundation technical spirit of the present invention is done above embodiment, all still belong in the scope of technical solution of the present invention.
Claims (2)
1. a both-end list shifting circuit, by a NMOS pipe (1) and the 2nd NMOS pipe (2), formed, it is characterized in that: the source electrode connection valve threshold voltage (VAA) of a described NMOS pipe (1), drain electrode connects the source electrode of the 2nd NMOS pipe (2) by output voltage (Vout), the drain electrode of the 2nd NMOS pipe (2) connects output interface, and a described NMOS pipe (1) is connected respectively differential signal (VIP, VIN) with the grid that the 2nd NMOS manages (2).
2. both-end list shifting circuit according to claim 1, it is characterized in that: on the grid of a described NMOS pipe (1) and the 2nd NMOS pipe (2), all be in series with electric capacity (3), all be parallel with resistance (4) between the electric capacity (3) of the one NMOS pipe (1) and the 2nd NMOS pipe (2) and grid, resistance (4) connects reference voltage (Vbias).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013103958592A CN103475353A (en) | 2013-09-04 | 2013-09-04 | Double-end-to-single-end circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013103958592A CN103475353A (en) | 2013-09-04 | 2013-09-04 | Double-end-to-single-end circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103475353A true CN103475353A (en) | 2013-12-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013103958592A Pending CN103475353A (en) | 2013-09-04 | 2013-09-04 | Double-end-to-single-end circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113098485A (en) * | 2021-04-02 | 2021-07-09 | 南方科技大学 | Double-rotation single-drive circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101471631A (en) * | 2007-12-29 | 2009-07-01 | 上海贝岭股份有限公司 | CMOS audio operational amplifier |
| CN101674072A (en) * | 2008-09-10 | 2010-03-17 | 中国科学院半导体研究所 | Interface circuit used for receiving low-voltage differential signals |
| CN102638231A (en) * | 2012-03-19 | 2012-08-15 | 中国科学院上海技术物理研究所 | Method for designing fully-customized chip for detection of high-speed weak photoelectric signals |
| CN102638317A (en) * | 2011-02-14 | 2012-08-15 | 中兴通讯股份有限公司 | Signal loss detection circuit and method and amplifier |
| CN203406847U (en) * | 2013-09-04 | 2014-01-22 | 苏州苏尔达信息科技有限公司 | Circuit switching double ends to single end |
-
2013
- 2013-09-04 CN CN2013103958592A patent/CN103475353A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101471631A (en) * | 2007-12-29 | 2009-07-01 | 上海贝岭股份有限公司 | CMOS audio operational amplifier |
| CN101674072A (en) * | 2008-09-10 | 2010-03-17 | 中国科学院半导体研究所 | Interface circuit used for receiving low-voltage differential signals |
| CN102638317A (en) * | 2011-02-14 | 2012-08-15 | 中兴通讯股份有限公司 | Signal loss detection circuit and method and amplifier |
| CN102638231A (en) * | 2012-03-19 | 2012-08-15 | 中国科学院上海技术物理研究所 | Method for designing fully-customized chip for detection of high-speed weak photoelectric signals |
| CN203406847U (en) * | 2013-09-04 | 2014-01-22 | 苏州苏尔达信息科技有限公司 | Circuit switching double ends to single end |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113098485A (en) * | 2021-04-02 | 2021-07-09 | 南方科技大学 | Double-rotation single-drive circuit |
| CN113098485B (en) * | 2021-04-02 | 2022-12-02 | 南方科技大学 | Double-rotation single-drive circuit |
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Application publication date: 20131225 |