CN202940784U - Reset circuit with adjustable reset time - Google Patents
Reset circuit with adjustable reset time Download PDFInfo
- Publication number
- CN202940784U CN202940784U CN 201220620738 CN201220620738U CN202940784U CN 202940784 U CN202940784 U CN 202940784U CN 201220620738 CN201220620738 CN 201220620738 CN 201220620738 U CN201220620738 U CN 201220620738U CN 202940784 U CN202940784 U CN 202940784U
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- circuit
- resistance
- reset
- adjustable
- power supply
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Abstract
The utility model discloses a reset circuit with adjustable reset time. The circuit comprises a source electrode and a PMOS tube connected with a power supply. A drain electrode of the PMOS tube is connected with a capacitor whose an end is connected with ground, and an amplifying circuit formed by inverters. An output end of the amplifying circuit is connected with an external circuit. A grid electrode of the PMOS tube is connected with an output end of a bleeder circuit. One of input ends of the bleeder circuit is connected with the power supply, and the other input end is connected with a switch tube. The switch tube is connected with an output end of the amplifying circuit. Through adjusting resistance value ratios of two resistors of the bleeder circuit, voltage of the grid electrode of the PMOS tube is adjusted, so that reset time is adjustable and the circuit adapts to circuits with different reset time requirements. A method of current to current is used, dimensions of the PMOS tube are reduced, and chip cost is reduced.
Description
Technical field
The utility model relates to the integrated circuit (IC) design field, is specifically related to a kind of reset circuit.
Background technology
In the design of integrated circuit, in order to guarantee the certainty of whole all states of circuit, need to reset to internal circuit, reset circuit is the requisite part of integrated circuit; In the design of reset circuit, need to have and guarantee that internal circuit can reset sufficiently long resetting time.General reset circuit charges to capacitor with the PMOS pipe by one, the principle of utilizing the both end voltage of capacitor not suddenly change, when powering on, the voltage of capacitor is zero, power supply is exactly resetting time by the PMOS pipe to the time that capacitor charges, guarantee long enough resetting time, need to increase capacitor or increase the resistance that the PMOS pipe forms, can cause chip cost to improve, while is due to the uncertainty of manufacturing process, capacitor and PMOS pipe are larger with technique change, can cause the resetting time of chip unstable, affect the operating efficiency of chip.
Summary of the invention
Problem to be solved in the utility model is to provide a kind of resetting time of adjustable reset circuit, can solve resetting time that prior art extends reset circuit can cause chip cost to improve and resetting time unsettled problem.
The utility model is achieved through the following technical solutions:
The reset circuit that a kind of resetting time is adjustable, comprise the PMOS pipe that source electrode is connected with power supply, the drain electrode of described PMOS pipe is connected with the amplifying circuit that capacitor and the inverter series connection of an end ground connection consist of respectively, the output of described amplifying circuit is connected with external circuit, the grid of described PMOS pipe is connected with the output of bleeder circuit, described bleeder circuit input one end is connected with power supply, and the input other end is connected with switching tube, and described switching tube is connected with the output of amplifying circuit.
Further scheme of the present utility model is, bleeder circuit is made of A resistance and the series connection of B resistance, and an end of described A resistance is connected with power supply, and an end of described B resistance is connected with switching tube, and being connected of described A resistance and B resistance a little is connected with the grid of PMOS pipe.
Further scheme of the present utility model is, described switching tube is enhancement mode NMOS pipe, and the drain electrode of described enhancement mode NMOS pipe is connected with an end of B resistance, source ground, and grid is connected with the output of amplifying circuit.
The utility model advantage compared with prior art is:
One, by adjusting the resistance ratio of bleeder circuit two resistance, gate pmos utmost point institute making alive is adjusted, thereby realized the adjustable of resetting time, to adapt to the circuit that require different resetting times;
Two, adopt electric current to the charging modes of electric current, can reduce the size of PMOS pipe, reduce chip cost.
Description of drawings
Fig. 1 is the circuit structure diagram of the reset circuit of prior art.
Fig. 2 is the circuit structure diagram of adjustable reset circuit resetting time described in the utility model.
Embodiment
The reset circuit of prior art as shown in Figure 1, comprise the PMOS pipe 1 that source electrode is connected with power supply 6, the drain electrode of described PMOS pipe 1 is connected with the amplifying circuits that the capacitor 2 of an end ground connection and inverter 3,4,5 series connection consist of respectively, the output 7 of described amplifying circuit is connected with external circuit, the grounded-grid of described PMOS pipe 1.
Reset circuit as shown in Figure 1 only has by adding the resistance value of large capacitor or increase PMOS pipe, can cause the raising of chip cost, also can cause resetting time unstable because of the uncertainty of manufacturing process.
The circuit structure diagram of the reset circuit that resetting time as shown in Figure 2 is adjustable, compared to Figure 1 difference is: the grid of PMOS pipe 1 is connected with the output of the bleeder circuit that is made of A resistance 8 and 9 series connection of B resistance, one end of described A resistance 8 is connected with power supply 6, one end of described B resistance 9 is connected with switching tube 10, and described switching tube 10 is connected with the output 7 of amplifying circuit.
Switching tube as shown in Figure 2 is connected and 10 is connected to enhancement mode NMOS pipe, and the drain electrode of described enhancement mode NMOS pipe 9 ends that are connected that are connected with B resistance are connected, and source ground, the grid 5 connected outputs that are connected with the inverter of amplifying circuit are connected.
The bleeder circuit that A resistance 8 and B resistance 9 form provides bias voltage to PMOS pipe 1, produces a bias current, and bias voltage is higher, and bias current is less, and longer to the time of capacitor charging, the resetting time of formation is longer; Change the resistance ratio of A resistance 8 and B resistance 9, can adjust the bias voltage of PMOS pipe 1, thereby realize different resetting times; After NMOS pipe 10 can guarantee to reset and finish, the current path of A resistance 8 and B resistance 9 disconnected, and reduced the power consumption of chip, extended the useful life of chip.
Claims (3)
- one kind resetting time adjustable reset circuit, comprise the PMOS pipe (1) that source electrode is connected with power supply (6), the drain electrode of described PMOS pipe (1) respectively with capacitor (2) and the inverter (3 of an end ground connection, 4, the amplifying circuit of 5) series connection formation is connected, the output of described amplifying circuit (7) is connected with external circuit, it is characterized in that: the grid of described PMOS pipe (1) is connected with the output of bleeder circuit, described bleeder circuit input one end is connected with power supply (6), the input other end is connected with switching tube (10), described switching tube (10) is connected with the output (7) of amplifying circuit.
- Resetting time as claimed in claim 1 adjustable reset circuit, it is characterized in that: described bleeder circuit is made of A resistance (8) and B resistance (9) series connection, one end of described A resistance (8) is connected with power supply (6), one end of described B resistance (9) is connected with switching tube (10), and the point that is connected of described A resistance (8) and B resistance (9) is connected with the grid of PMOS pipe (1).
- Resetting time as claimed in claim 1 or 2 adjustable reset circuit, it is characterized in that: described switching tube (10) is enhancement mode NMOS pipe, the drain electrode of described enhancement mode NMOS pipe is connected with an end of B resistance (9), source ground, grid is connected with inverter (5) output of amplifying circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220620738 CN202940784U (en) | 2012-11-22 | 2012-11-22 | Reset circuit with adjustable reset time |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220620738 CN202940784U (en) | 2012-11-22 | 2012-11-22 | Reset circuit with adjustable reset time |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202940784U true CN202940784U (en) | 2013-05-15 |
Family
ID=48325006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220620738 Expired - Lifetime CN202940784U (en) | 2012-11-22 | 2012-11-22 | Reset circuit with adjustable reset time |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202940784U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102957407A (en) * | 2012-11-22 | 2013-03-06 | 江苏格立特电子有限公司 | Reset circuit with adjustable reset time |
-
2012
- 2012-11-22 CN CN 201220620738 patent/CN202940784U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102957407A (en) * | 2012-11-22 | 2013-03-06 | 江苏格立特电子有限公司 | Reset circuit with adjustable reset time |
| CN102957407B (en) * | 2012-11-22 | 2015-09-30 | 江苏格立特电子有限公司 | The reset circuit that a kind of resetting time is adjustable |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: XIE WEIGUO Free format text: FORMER OWNER: JIANGSU GELITE ELECTRONICS CO., LTD. Effective date: 20130723 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20130723 Address after: 223900, Jiangsu, Suqian province Sihong County Construction North Road and Jinsha River Road Electronic Industrial Park, No. 10 factory building Patentee after: Xie Weiguo Address before: 223900, Jiangsu, Suqian province Sihong County Construction North Road and Jinsha River Road Electronic Industrial Park, No. 10 factory building Patentee before: JIANGSU GELITE ELECTRONICS Co.,Ltd. |
|
| ASS | Succession or assignment of patent right |
Owner name: JIANGSU GELITE ELECTRONICS CO., LTD. Free format text: FORMER OWNER: XIE WEIGUO Effective date: 20140122 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20140122 Address after: 223900, Jiangsu, Suqian province Sihong County Construction North Road and Jinsha River Road Electronic Industrial Park, No. 10 factory building Patentee after: JIANGSU GELITE ELECTRONICS Co.,Ltd. Address before: 223900, Jiangsu, Suqian province Sihong County Construction North Road and Jinsha River Road Electronic Industrial Park, No. 10 factory building Patentee before: Xie Weiguo |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130515 |