CN103456746A - Array substrate, manufacturing method thereof and display device - Google Patents
Array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN103456746A CN103456746A CN2013104095928A CN201310409592A CN103456746A CN 103456746 A CN103456746 A CN 103456746A CN 2013104095928 A CN2013104095928 A CN 2013104095928A CN 201310409592 A CN201310409592 A CN 201310409592A CN 103456746 A CN103456746 A CN 103456746A
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Abstract
The embodiment of the invention provides an array substrate, a manufacturing method of the array substrate and a display device and relates to the field of display technologies. The array substrate, the manufacturing method and the display device can reduce the number of composition process times and lower cost. The array substrate comprises a pixel area and an array substrate row drive GOA area. The pixel area comprises a grid electrode, patterns of an active layer, a source electrode, a drain electrode, a pixel electrode electrically connected with the drain electrode, and a second transparent electrode which is located above the source electrode, electrically connected with the source electrode and located in the same layer as the pixel electrode. Patterns of a grid insulating layer are arranged in the pixel area and the GOA area. The GOA area comprises a first electrode in the same layer as the grid electrode, active layer retained patterns in the same layer as the patterns of the active layer, a second electrode in the same layer as the source electrode and the drain electrode, and a first transparent electrode in the same layer as the pixel electrode. The active layer retained patterns and the second electrode respectively comprise a via hole through which the first electrode can be exposed. The first transparent electrode is arranged above the second electrode and is electrically connected with both the second electrode and the first electrode. The array substrate is used for manufacturing the display device.
Description
Technical field
The present invention relates to the Display Technique field, relate in particular to a kind of array base palte and preparation method thereof, display unit.
Background technology
Along with thin-film transistor (Thin Film Transistor, abbreviation TFT) development of lcd technology, increasing new technology constantly is suggested and applies, for example high-resolution, high aperture, the capable driving of array base palte (Gate on Array is called for short GOA) technology etc.Wherein, in order to reduce costs the TFT display floater that obtains narrow frame, it is particularly important that the GOA structure becomes.Yet the introducing of GOA structure has also brought the complexity of array base-plate structure design simultaneously, has increased composition number of processes and the difficulty of making array base palte.
At present, the tft array substrate that formation has a GOA structure needs grid metal mask layer, gate insulation layer mask, active layer mask, source to leak the repeatedly composition technique such as metal mask layer, the first electrode layer mask, passivation layer mask and the second electrode lay mask, and comprises respectively again film forming, exposure, development, etching in composition technique each time, the technique such as peels off.The number of times of composition technique too much will directly cause the increase of technology difficulty, the rising of product cost and the reduction of product production capacity.
Therefore, when formation has the tft array substrate of GOA structure, how to reduce the number of times of composition technique, become the problem of people's growing interest.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and preparation method thereof, display unit, can reduce the number of times of composition technique, thereby promote the production capacity of volume production product, reduce costs.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, provide a kind of array base palte, this array base palte comprises pixel region and GOA district; Described pixel region comprises the grid be arranged on substrate, pattern, source electrode and the drain electrode of active layer, the pixel electrode be electrically connected to described drain electrode, and the pattern setting of gate insulation layer is in described pixel region and described GOA district; Also comprise be arranged on described GOA district and described grid with the first electrode of floor, with the pattern of described active layer with the active layer of floor retain pattern, with described source electrode and drain electrode the second electrode with floor, with the first transparency electrode of same layer of described pixel electrode; Wherein, described active layer reservation pattern and described the second electrode include the via hole that exposes described the first electrode; Described the first transparency electrode is arranged on described the second electrode top and all is electrically connected to described the second electrode and described the first electrode; Described pixel region also comprise be arranged on described source electrode top and with second transparency electrode of described pixel electrode with layer, described the second transparency electrode is electrically connected to described source electrode.
On the other hand, provide a kind of display unit, comprise above-mentioned array base palte.
Again on the one hand, provide a kind of preparation method of above-mentioned array base palte, described array base palte comprises pixel region and GOA district; This preparation method comprises: by a composition technique, on the underlay substrate of described pixel region, form grid, form the first electrode on the underlay substrate in described GOA district; By a composition technique, form the pattern of gate insulation layer on the substrate in described pixel region and described GOA district, form the first pattern and be positioned at the second pattern above described the first pattern on the substrate of described pixel region, on the substrate in described GOA district, form with described the first pattern with the active layer of floor retain pattern, with second electrode of described the second pattern with floor, and described active layer reservation pattern and described the second electrode include the via hole that exposes described the first electrode and divide; Wherein, the pattern of the corresponding active layer of described the first pattern, the corresponding source electrode of described the second pattern and drain electrode; By a composition technique, at least form described source electrode and drain electrode, the pixel electrode be electrically connected to described drain electrode on the substrate of described pixel region, be positioned at above described source electrode and the second transparency electrode be electrically connected to described source electrode, on the substrate in described GOA district, form and be positioned at above described the second electrode and the first transparency electrode all be electrically connected to described the second electrode and described the first electrode.
The embodiment of the present invention provides a kind of array base palte and preparation method thereof, display unit, and this array base palte comprises pixel region and GOA district; Described pixel region comprises the grid be arranged on substrate, pattern, source electrode and the drain electrode of active layer, the pixel electrode be electrically connected to described drain electrode; The pattern setting of gate insulation layer is in described pixel region and described GOA district; Also comprise be arranged on described GOA district and described grid with the first electrode of floor, with the pattern of described active layer with the active layer of floor retain pattern, with described source electrode and drain electrode the second electrode with floor, with the first transparency electrode of same layer of described pixel electrode; Wherein, described active layer reservation pattern and described the second electrode include the via hole that exposes described the first electrode; Described the first transparency electrode is arranged on described the second electrode top and all is electrically connected to described the second electrode and described the first electrode; Described pixel region also comprise be arranged on described source electrode top and with second transparency electrode of described pixel electrode with layer, described the second transparency electrode is electrically connected to described source electrode.Like this, can only by 3 composition techniques, just form TFT structure and the GOA structure on array base palte, and pixel electrode, effectively reduce the number of times of composition technique, thereby can promote the production capacity of volume production product, reduce costs.
The accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Preparation method's flow chart of the tft array substrate of a kind of GOA of comprising structure that Fig. 1 provides for the embodiment of the present invention;
A kind of structural representation that forms grid and the first electrode that Fig. 2 provides for the embodiment of the present invention;
A kind of pattern, the first pattern, the second pattern, active layer that forms gate insulation layer that Fig. 3 provides for the embodiment of the present invention retains the structural representation of pattern, the second electrode and GOA district via hole;
A kind of array base-plate structure schematic diagram one that Fig. 4 (a) provides for the embodiment of the present invention;
A kind of array base-plate structure schematic diagram two that Fig. 4 (b) provides for the embodiment of the present invention;
A kind of pattern, the first pattern, the second pattern, active layer that forms gate insulation layer that Fig. 5 (a)～Fig. 5 (e) provides for the embodiment of the present invention retains the process schematic diagram of pattern, the second electrode and GOA district via hole;
A kind of process schematic diagram that forms pattern, source electrode and drain electrode, pixel electrode, the second transparency electrode and first transparency electrode of active layer that Fig. 6 (a)～Fig. 6 (d) provides for the embodiment of the present invention;
A kind of formation that Fig. 7 provides for the embodiment of the present invention comprises the structural representation of the pattern of passivation layer;
A kind of array base-plate structure schematic diagram three that Fig. 8 provides for the embodiment of the present invention.
Reference numeral:
Pixel region-10a; GOA district-10b; Underlay substrate-100; Gate insulation layer film-11; Amorphous silicon membrane-12a; N+ amorphous silicon membrane-12b; Metallic film-13; Grid-101a; The first electrode-101b; The pattern of gate insulation layer-102; The pattern of active layer-103; The first pattern-103a; Active layer retains pattern-103b; Source electrode-1041; Drain electrode-1042; The second pattern-104a; The second electrode-104b; Via hole-105b; Pixel electrode-106; The second transparency electrode-106a; The first transparency electrode-106b; The pattern of passivation layer-107; Public electrode-108; Intermediate tone mask plate-20; The opaque section of intermediate tone mask plate-201; The translucent portion of intermediate tone mask plate-202; The transparent part of intermediate tone mask plate-203; Photoresist-30; Photoresist complete reserve part-301; Photoresist half reserve part-302; Photoresist is removed part-303 fully.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making under the creative work prerequisite the every other embodiment obtained, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of preparation method of array base palte, and described array base palte comprises pixel region 10aHe GOA district 10b; As shown in Figure 1, the method comprises the steps:
S101, as shown in Figure 2 by a composition technique, forms grid 101a on the underlay substrate 100 of described pixel region 10a, forms the first electrode 101b on the underlay substrate 100 of described GOA district 10b.
S102, as shown in Figure 3 by a composition technique, forms the pattern 102 of gate insulation layer on the substrate of described pixel region 10a and described GOA district 10b; Form the first pattern 103a and be positioned at the second pattern 104a above described the first pattern on the substrate of described pixel region 10a, on the substrate of described GOA district 10b, form with described the first pattern 103a with the active layer of floor retain pattern 103b, with the second electrode 104b of described the second pattern 104a with floor, and described active layer reservation pattern 103b and described the second electrode 104b include the via hole 105b that exposes described the first electrode 101b.
Wherein, the pattern 103 of the corresponding active layer of described the first pattern 103a, the corresponding source electrode 1041 of described the second pattern 104a and drain electrode 1042.
S103, as Fig. 4 (a) with 4(b), by a composition technique, at least form source electrode 1041 and drain electrode 1042, the pixel electrode 106 be electrically connected to described drain electrode 1042 on the substrate of described pixel region 10a, be positioned at above described source electrode 1041 and the second transparency electrode 106a be electrically connected to described source electrode 1041, on the substrate of described GOA district 10b, form and be positioned at above described the second electrode 104b and the first transparency electrode 106b all be electrically connected to described the second electrode 104b and described the first electrode 101b.
Here, when described the first pattern 103a comprises metal-oxide film, in step S102, described the first pattern 103a is the pattern 103 of described active layer; When described the first pattern 103a comprises amorphous silicon membrane and n+ amorphous silicon membrane, in step S103, after the n+ amorphous silicon membrane of described source electrode 1041 and described the first pattern 103a corresponding to the gap that drains between 1042 is carried out to etching, just can form the pattern 103 of described active layer; Now, the pattern 103 of described active layer comprises amorphous silicon pattern and n+ amorphous silicon pattern.
In the embodiment of the present invention, by a composition technique, form the grid 101a that is positioned at described pixel region 10a, the first electrode that is positioned at described GOA district 10b, form the pattern 102 of the gate insulation layer that is positioned at described pixel region 10a and described GOA district 10b by other twice composition technique, be positioned at the pattern 103 of the active layer of described pixel region 10a, source electrode 1041 and drain electrode 1042, the the second transparency electrode 106a that is positioned at described source electrode top and is electrically connected to described source electrode 1041, the pixel electrode 106 be electrically connected to described drain electrode 1042, and the described active layer reservation pattern 103b of the pattern 103 of GOA district 10b and described active layer with floor that be positioned at, the second electrode 104b with described source electrode 1041 and drain electrode 1042 same layers, the the first transparency electrode 106b that is positioned at described the second electrode 104b top and all is electrically connected to described the second electrode 104b and described the first electrode 101b, wherein, described the first transparency electrode 106b is electrically connected to described the first electrode 101b by via hole 105b, described active layer retains pattern 103b and described the second electrode 104b includes the described via hole 105b that exposes described the first electrode 101b.The embodiment of the present invention only just can form TFT structure and the GOA structure on array base palte by 3 composition techniques, and pixel electrode, has effectively reduced the number of times of composition technique, thereby can promote the production capacity of volume production product, reduces costs.
Optionally, if in above-mentioned S102, described the first pattern 103a comprises amorphous silicon membrane 12a and n+ amorphous silicon membrane 12b, and on this basis, described S102 specifically comprises:
Form successively gate insulation layer film 11, amorphous silicon membrane 12a and n+ amorphous silicon membrane 12b and metallic film 13 on described substrate, and form photoresist 30 on described metallic film 13.
After adopting intermediate tone mask plate 20 or gray tone mask plate to be exposed, develop the substrate that is formed with described photoresist 30, form the complete reserve part 301 of photoresist, photoresist half reserve part 302 and photoresist and remove part 303 fully; Wherein, described photoresist is removed the to be formed via hole 105b that exposes described the first electrode 101b that part 303 correspondences are positioned at described GOA district 10b fully; Complete reserve part 301 correspondences of described photoresist be positioned at described the first pattern 103a to be formed of described pixel region 10a and to be formed and described the first pattern 103a of being positioned at the described second pattern 104a of described the first pattern 103a top and being positioned at described GOA district 10b with the described active layer of floor retain pattern 103b and with the described second electrode 104b of the same floor of described the second pattern 104a; Described photoresist half corresponding other zones of reserve part 302.
Adopt etching technics to remove described photoresist and remove the described metallic film 13 of part 303, described n+ amorphous silicon membrane 12b, described amorphous silicon membrane 12a and described gate insulation layer film 11 fully, form the via hole 105b that exposes described the first electrode 101b.
Adopt cineration technics to remove the photoresist 30 of described photoresist half reserve part 302.
Adopt etching technics to remove described metallic film 13, described n+ amorphous silicon membrane 12b and the described amorphous silicon membrane 12a exposed, form described the first pattern 103a and described the second pattern 104a, and with described the first pattern 103a with the described active layer of layer retain pattern 103b and with the described second electrode 104b of described the second pattern 104a with layer, and described active layer retains pattern 103b and described the second electrode 104b includes the via hole 105b that exposes described the first electrode 101b; Wherein, the pattern 103 of the corresponding described active layer of described the first pattern 103a, the corresponding described source electrode 1041 of described the second pattern 104a and drain electrode 1042.
Adopt stripping technology to remove the photoresist 30 of the complete reserve part 301 of described photoresist.
It should be noted that, above-mentioned film forming method can be the methods such as deposition, coating, sputter.
In addition, because described the first electrode 101b and described grid 101a form by a composition technique, generally can select identical metal material, and the above-mentioned metallic film 13 that is positioned at described photoresist 30 belows is also metal material; In the process prepared in reality, these two kinds of metal materials can be identical, also can be not identical.Like this, because at first described the first electrode 101b forms by etching, and carry out etching with before forming described the second pattern 104a at the metallic film 13 by described photoresist half reserve part 302 correspondences, outside described the first electrode 101b has been exposed to by described via hole 105b, therefore, when forming described the second pattern 104a, etching just needs to consider following two kinds of situations:
First, in the situation that described the first electrode 101b is not identical with the metal material of above-mentioned metallic film 13, remove the photoresist 30 of described photoresist half reserve part 302 by cineration technics after, for etching, the etching liquid of the metallic film that expose 13 corresponding with described photoresist half reserve part 302 should have selectivity to metal material; That is, only the metal material at the described metallic film exposed 13 places had to corrasion, the metal material of described the first electrode 101b is not had to a corrasion.
Second, in the situation that described the first electrode 101b is identical with the metal material of above-mentioned metallic film 13, for example ITO transparent conductive film of one deck can be set above described the first electrode 101b, the described first electrode 101b of same material is also etched away when the described metallic film 13 exposed of etching preventing.
On this basis, further alternative, described S103 specifically comprises:
Form transparent conductive film on substrate, and form photoresist 30 on described transparent conductive film.
By mask plate to the substrate that is formed with described photoresist 30 exposed, development, etching, peel off after, form pattern 103, the described source electrode 1041 of described active layer and drain 1042, the pixel electrode 106 that is electrically connected to described drain electrode 1042, be positioned at above described source electrode 1041 and the second transparency electrode 106a be electrically connected to described source electrode 1041 on the substrate of described pixel region 10a; Form and be positioned at above described the second electrode 104b and the first transparency electrode 106b all be electrically connected to described the second electrode 104b and described the first electrode 101b on the substrate of described GOA district 101b; Wherein, the pattern 103 of described active layer comprises amorphous silicon pattern and n+ amorphous silicon pattern.
Here, when form described source electrode 1041 and drain electrode 1042 by etching after, also need to described source electrode 1041 and described drain electrode 1042 between the n+ amorphous silicon membrane 12b of described the first pattern 103a corresponding to gap carry out etching, thereby form the pattern 103 of described active layer.
Below provide the preparation method of the array base palte of a pair of described GOA of the comprising structure of a specific embodiment to describe:
S201, with reference to shown in figure 2, form the layer of metal film on described underlay substrate 100, by a composition PROCESS FOR TREATMENT, form grid 101a on the underlay substrate 100 of described pixel region 10a, form the first electrode 101b on the underlay substrate 100 of described GOA district 10b.
Concrete, can use magnetically controlled sputter method, on glass substrate, preparation a layer thickness exists
extremely
copper metal film.Then undertaken by exposure, development, etching, the composition PROCESS FOR TREATMENT such as peel off by mask plate, form described grid 101a on the underlay substrate 100 of described pixel region 10a, form described the first electrode 101b on the underlay substrate 100 of described GOA district 10b, certainly, also form grid line, grid line lead-in wire etc. simultaneously.
S202, as shown in Fig. 5 (a), form successively gate insulation layer film 11, amorphous silicon membrane 12a and n+ amorphous silicon membrane 12b and molybdenum film 13 on the substrate of completing steps S201, and form photoresist 30 on described molybdenum film 13.
Concrete, can utilize chemical vapour deposition technique first on the substrate that is formed with grid 101a and the first electrode 101b patterned layer, to deposit a layer thickness and be about
extremely
gate insulation layer film 11, the material of described gate insulation layer film 11 is silicon nitride normally, also can use silica and silicon oxynitride etc.; By chemical vapour deposition technique deposit thickness on aforesaid substrate, be about again
extremely
amorphous silicon membrane 12a and n+ amorphous silicon membrane 12b; And then deposition a layer thickness is about on aforesaid substrate
arrive
molybdenum film 13, and apply one deck photoresist 30 on described molybdenum film 13.
S203, as shown in Fig. 5 (b), after the substrate that adopts 20 pairs of intermediate tone mask plates to be formed with described photoresist 30 is exposed, develops, the complete reserve part 301 of formation photoresist, photoresist half reserve part 302 and photoresist are removed part 303 fully.
Wherein, complete reserve part 301 correspondences of described photoresist be positioned at described the first pattern 103a to be formed of described pixel region 10a and to be formed and described the first pattern 103a of being positioned at the described second pattern 104a of described the first pattern 103a top and being positioned at described GOA district 10b with the described active layer of floor retain pattern 103b and with the described second electrode 104b of the same floor of described the second pattern 104a; Described photoresist is removed the to be formed via hole 105b that exposes described the first electrode 101b that part 303 correspondences are positioned at described GOA district 10b fully; Described photoresist half corresponding other zones of reserve part 302.
Herein, with reference to figure 5(b) for the cardinal principle of described intermediate tone mask plate 20, be described as follows:
Described intermediate tone mask plate 20 is by grating effect, make exposure zones of different to see through light intensity different, thereby make described photoresist 30 carry out selectivity exposure, development.Described intermediate tone mask plate 20 comprises opaque section 201, translucent portion 202 and transparent part 203.Described photoresist 30 is after overexposure, the opaque section 201 of the corresponding described intermediate tone mask plate of the complete reserve part 301 of described photoresist, the translucent portion 202 of the corresponding described intermediate tone mask plate of described photoresist half reserve part 302, described photoresist is removed the transparent part 203 of the corresponding described intermediate tone mask plate of part 303 fully.
The principle of described gray tone mask plate 20 and described intermediate tone mask plate 20 are similar, do not repeat them here.
Wherein, in all embodiment of the present invention, the described photoresist 30 of indication is positive photoresist, be in described intermediate tone mask plate 20, the zone that described photoresist is removed part 303 correspondences fully is complete exposure area, and the material of corresponding described intermediate tone mask plate 20 is light transmissive material; The zone of described photoresist half reserve part 302 correspondences is half exposure area, the material of corresponding described intermediate tone mask plate 20 is semi transparent material, the zone of complete reserve part 301 correspondences of described photoresist is exposure area not, and the material of corresponding described intermediate tone mask plate 20 is light-proof material.
S204, as shown in Fig. 5 (c), adopt etching technics to remove described photoresist and remove the described molybdenum film 13 of part 303, described n+ amorphous silicon membrane 12b and described amorphous silicon membrane 12a and described gate insulation layer film 11 fully, form the pattern 102 of gate insulation layer and the via hole 105b that exposes described the first electrode 101b.
Here, the etching technics adopted can comprise dry the quarter and wet etching.Wherein, when the described molybdenum of etching film 13, adopt dry quarter or wet etching all can; Adopt dry the quarter when etching described n+ amorphous silicon membrane 12b and described amorphous silicon membrane 12a and described gate insulation layer film 11, and can realize this dry carving technology by same gas.
S205, as shown in Fig. 5 (d), adopt cineration technics to remove the photoresist 30 of described photoresist half reserve part 302.
Because the photoresist 30 of the complete reserve part 301 of described photoresist is thicker than the thickness of the photoresist 30 of described photoresist half reserve part 302, therefore, after the photoresist of described photoresist half reserve part 302 is removed, the complete reserve part 301 of described photoresist also has the part photoresist to stay on described substrate.Now, outside the molybdenum film 13 of described photoresist half reserve part 302 correspondences is exposed to.
S206, as shown in Figure 5 (e) shows, adopt etching technics to remove the described molybdenum film 13 exposed, and the described n+ amorphous silicon membrane 12b of described molybdenum film 13 belows and described amorphous silicon membrane 12a, form described the first pattern 103a and be positioned at described the second pattern 104a above described the first pattern 103a at described pixel region 10a, described GOA district 10b form with described the first pattern 103a with the active layer of floor retain pattern 103b and with the described second electrode 104b of the same floor of described the second pattern 104a, described active layer retains pattern 103b and described the second electrode 104b includes the described via hole 105b that exposes described the first electrode 101b.
Wherein, the pattern 103 of the corresponding described active layer of described the first pattern 103a, comprise that amorphous silicon membrane 12a and n+ amorphous silicon membrane 12b are two-layer; The corresponding described source electrode 1041 of described the second pattern 104a and drain electrode 1042.
Here, can adopt wet-etching technique to carry out etching to described molybdenum film 13, adopt dry the quarter to carry out etching to described n+ amorphous silicon membrane 12b and described amorphous silicon membrane 12a.
S207, employing stripping technology are removed the photoresist 30 of the complete reserve part 301 of described photoresist, obtain with reference to the structure shown in figure 3.
Above step S202～S207 is by a composition PROCESS FOR TREATMENT, form the pattern 102 of gate insulation layer on the substrate of described pixel region 10a and described GOA district 10b, form described the first pattern 103a and be positioned at described the second pattern 104a above described the first pattern 103a on the substrate of described pixel region 10a, form the described active layer reservation pattern 103b with floor with described the first pattern 103a on the substrate of described GOA district 10b, with the described second electrode 104b of described the second pattern 104a with layer, and described active layer retains pattern 103b and the second electrode 104b includes the described via hole 105b that exposes described the first electrode 101b.
S208, as shown in Figure 6 (a) forms ito thin film on the substrate of completing steps S207, and forms photoresist 30 on described ito thin film.
Concrete, can first utilize chemical vapour deposition technique to deposit a layer thickness on whole substrate and be about
extremely
ito thin film, then on described ito thin film, apply one deck photoresist 30.
Here, can also substitute described ito thin film with other transparent conductive films; Wherein transparent conductive film commonly used also comprises indium zinc oxide (Indium Zinc Oxide is called for short IZO) conductive film.
S209, as shown in Figure 6 (b), adopt mask plate to be exposed, develops the substrate that is formed with described photoresist 30, and the formation complete reserve part 301 of photoresist and photoresist are removed part 303 fully.
Wherein, pixel electrode 106 corresponding to the complete reserve part of described photoresist 301, the first transparency electrode 106b that is positioned at the second transparency electrode 106a of source electrode to be formed 1041 tops and is positioned at described the second electrode 104b top and is electrically connected to described the first electrode 101b by the via hole 105b that exposes described the first electrode 101b; Described photoresist is removed corresponding other zones of part 303 fully.
S210, as shown in Figure 6 (c), adopt etching technics to remove described photoresist and remove the described ito thin film of part 303 and the molybdenum film 13 of described the second pattern 104a fully, the first transparency electrode 106b that forms described source electrode 1041 and drain electrode 1042, the pixel electrode 106 be electrically connected to described drain electrode 1042, is positioned at described source electrode 1041 tops the second transparency electrode 106a be electrically connected to described source electrode 1041 and is positioned at described the second electrode 104b top and all is electrically connected to described the second electrode 104b and described the first electrode 101b.
S211, as shown in Fig. 6 (d), adopt etching technics to remove the n+ amorphous silicon membrane 12b of described the first pattern 103a corresponding to gap between described source electrode 1041 and described drain electrode 1042, thereby form the pattern 103 of active layer.Wherein, the pattern 103 of described active layer comprises amorphous silicon pattern and n+ amorphous silicon pattern.
S212, adopt stripping technology to remove the photoresist 30 of the complete reserve part 301 of described photoresist, obtain the 4(a with reference to figure) shown in structure.
Above step S208～S212 is by a composition PROCESS FOR TREATMENT, form described source electrode 1041 and drain electrode 1042 on the substrate of described pixel region 10a, be positioned at the pattern 103 of the active layer of described source electrode 1041 and drain electrode 1042 belows, the pixel electrode 106 be electrically connected to described drain electrode 1042, the the second transparency electrode 106a that is positioned at described source electrode 1041 tops and is electrically connected to described source electrode 1041, form and be positioned at above described the second electrode 104b and the first transparency electrode 106b all be electrically connected to described the second electrode 104b and described the first electrode 101b on the substrate of described GOA district 10b.
In embodiments of the present invention, by 3 composition techniques, just form TFT structure and the GOA structure on array base palte, and pixel electrode, effectively reduce the number of times of composition technique, thereby can promote the production capacity of volume production product, reduce costs.
The array base palte that the embodiment of the present invention provides goes for the production of the liquid crystal indicator of the types such as a senior super dimension conversion hysteria, twisted-nematic (Twist Nematic is called for short TN) type.Wherein, a senior super dimension switch technology, its core technology characteristic description is: the electric field produced by electric field that in same plane, the gap electrode edge produces and gap electrode layer and plate electrode interlayer forms multi-dimensional electric field, make in liquid crystal cell between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thereby improved the liquid crystal operating efficiency and increased light transmission efficiency.A senior super dimension switch technology can improve the picture quality of TFT display panels, has high-resolution, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples.
Therefore, on the basis of step S212, described preparation method also comprises:
S213, as shown in Figure 7 forms the pattern 107 of passivation layer on the substrate of described pixel region 10a and described GOA district 10b.
S214, as shown in Figure 8 forms public electrode 108 on the substrate of described pixel region 10a.
It should be noted that, described public electrode 108 and the described pixel electrode 106 of a described senior super dimension conversion hysteria array base palte all are arranged on described array base palte.In the case, the described pixel electrode 106 that is positioned at below can be tabular, and the described public electrode 108 that is positioned at top can be strip; Can be also that the pixel electrode 106 that is positioned at below also is strip.
Optionally, if in above-mentioned S102, described the first pattern 103a is metal-oxide film, and on this basis, described S102 specifically comprises:
Form successively gate insulation layer film 11, metal-oxide film and metallic film 13 on described substrate, and form photoresist 30 on described metallic film 13.
After adopting intermediate tone mask plate 20 or gray tone mask plate to be exposed, develop the substrate that is formed with described photoresist 30, form the complete reserve part 301 of photoresist, photoresist half reserve part 302 and photoresist and remove part 303 fully; Wherein, described photoresist is removed the to be formed via hole 105b that exposes described the first electrode 101b that part 303 correspondences are positioned at described GOA district 10b fully; Complete reserve part 301 correspondences of described photoresist be positioned at described the first pattern 103a to be formed of described pixel region 10a and to be formed and described the first pattern 103a of being positioned at the described second pattern 104a of described the first pattern 103a top and being positioned at described GOA district 10b with the described active layer of floor retain pattern 103b and with the described second electrode 104b of the same floor of described the second pattern 104a; Described photoresist half corresponding other zones of reserve part 302.
Adopt etching technics to remove described photoresist and remove the described metallic film 13 of part 303, described metal-oxide film and described gate insulation layer film 11 fully, form the via hole 105b that exposes described the first electrode 101b.
Adopt cineration technics to remove the photoresist 30 of described photoresist half reserve part 302.
Adopt etching technics to remove described metallic film 13, the described metal-oxide film exposed, form described the first pattern 103a and described the second pattern 104a, and with described the first pattern 103a with the described active layer of layer retain pattern 103b and with the described second electrode 104b of described the second pattern 104a with layer; Wherein, described active layer reservation pattern 103b and described the second electrode 104b include the via hole 105b that exposes described the first electrode 101b; Wherein, described the first pattern 103a is the pattern 103 of described active layer, the corresponding described source electrode 1041 of described the second pattern 103b and drain electrode 1042.
Adopt stripping technology to remove the photoresist 30 of the complete reserve part 301 of described photoresist.
On this basis, further alternative, described S103 specifically comprises:
Form transparent conductive film on substrate, and form photoresist 30 on described transparent conductive film.
By mask plate to the substrate that is formed with described photoresist 30 exposed, development, etching, peel off after, form described source electrode 1041 and drain electrode 1042, the pixel electrode 106 be electrically connected to described drain electrode 1042 on the substrate of described pixel region 10a, be positioned at above described source electrode 1041 and the second transparency electrode 106a be electrically connected to described source electrode 1041; Form and be positioned at above described the second electrode 104b and the first transparency electrode 106b all be electrically connected to described the second electrode 104b and described the first electrode 101b on the substrate of described GOA district 101b.
Below provide the preparation method of the array base palte of the two pairs of described GOA of comprising structures of a specific embodiment to describe:
S301, on described underlay substrate 100, form copper metal film, by a composition PROCESS FOR TREATMENT, form grid 101a on the underlay substrate 100 of described pixel region 10a, form the first electrode 101b on the underlay substrate 100 of described GOA district 10b.
S302, form successively gate insulation layer film 11, metal-oxide film and molybdenum film 13 on the substrate of completing steps S201, and form photoresist 30 on described molybdenum film 13.
After S303, the substrate that adopts 20 pairs of intermediate tone mask plates to be formed with described photoresist 30 are exposed, develop, form the complete reserve part 301 of photoresist, photoresist half reserve part 302 and photoresist and remove part 303 fully.
Wherein, described photoresist is removed the to be formed via hole 105b that exposes described the first electrode 101b that part 303 correspondences are positioned at described GOA district 10b fully; Complete reserve part 301 correspondences of described photoresist be positioned at described the first pattern 103a to be formed of described pixel region 10a and to be formed and described the first pattern 103a of being positioned at the described second pattern 104a of described the first pattern 103a top and being positioned at described GOA district 10b with the described active layer of floor retain pattern 103b and with described the second electrode 104b of the same floor 104a of described the second pattern; Described photoresist half corresponding other zones of reserve part 302.
S304, employing etching technics are removed described photoresist and are removed the described molybdenum film 13 of part 303, described metal-oxide film and described gate insulation layer film 11 fully, form the pattern 102 of gate insulation layer and the via hole 105b that exposes described the first electrode 101b.
S305, employing cineration technics are removed the photoresist 30 of described photoresist half reserve part 302.
S306, the described molybdenum film 13 that the removal of employing etching technics is exposed and the described metal-oxide film of described molybdenum film 13 belows, form described the first pattern 103a and be positioned at described the second pattern 104a above described the first pattern 103a at described pixel region 10a, described GOA district 10b form with described the first pattern 103a with the active layer of floor retain pattern 103b and with the described second electrode 104b of the same floor of described the second pattern 104a, described active layer retains pattern 103b and described the second electrode 104b includes the via hole 105b that exposes described the first electrode 101b.
Wherein, described the first pattern 103a is the pattern 103 of described active layer, and the pattern 103 of its described active layer comprises the burning article pattern; The corresponding described source electrode 1041 of described the second pattern 104a and drain electrode 1042.
S307, employing stripping technology are removed the photoresist 30 of the complete reserve part 301 of described photoresist, obtain with reference to the structure shown in figure 3.
S308, on the substrate of completing steps S307, form ito thin film, and form photoresist 30 on described ito thin film.
S309, adopt mask plate to the substrate that is formed with described photoresist 30 exposed, after development, etching, formation is positioned at source electrode 1041 and drain electrode 1042, the pixel electrode 106 be electrically connected to described drain electrode 1042 of pattern 103 tops of described active layer, the first transparency electrode 106b that is positioned at described source electrode 1041 tops the second transparency electrode 106a be electrically connected to described source electrode 1041 and is positioned at described the second electrode 104b top and all is electrically connected to described the second electrode 104b and described the first electrode 101b, obtains the structure as shown in figure Fig. 4 (b).
Further, on the basis of step S309, described preparation method also comprises:
S310, form the pattern 107 of passivation layer on the substrate of described pixel region 10a and described GOA district 10b.
S311, form public electrode 108 on the substrate of described pixel region 10a.
The embodiment of the present invention also provides a kind of array base palte that utilizes said method to prepare, with reference to figure 4(a) and Fig. 4 (b) shown in, this array base palte comprises pixel region 10aHe GOA district 10b; The pixel electrode 106 that described pixel region 10a comprises pattern 103, the source electrode 1041 of the grid 101a that is arranged on substrate, active layer and drains 1042, is electrically connected to described drain electrode 1042, the pattern 102 of gate insulation layer is arranged on described pixel region 10a and described GOA district 10b; Described array base palte further comprises: be arranged on described GOA district 10b and described grid 101a with the first electrode 101b of floor, with the pattern 103 of described active layer with the active layer of floor retain pattern 103b, with described source electrode 1041 and 1042 the second electrode 104b with floor that drain, and the first transparency electrode 106b of described pixel electrode 106 same floor.
Wherein, described active layer reservation pattern 103b and described the second electrode 104b include the via hole 105b that exposes described the first electrode 101b; Described the first transparency electrode 106b is arranged on described the second electrode 104b top and all is electrically connected to described the second electrode 104b and described the first electrode 101b; Described pixel region 10a also comprise be arranged on described source electrode 1041 tops and with the second transparency electrode 106a of described pixel electrode 106 with layer, described the second transparency electrode 106a is electrically connected to described source electrode 1041.
Optionally, with reference to figure 4(a), the pattern 103 of described active layer comprises amorphous silicon pattern and n+ amorphous silicon pattern; Perhaps with reference to figure 4(b) shown in, the pattern 103 of described active layer comprises the burning article pattern.
In the situation that the pattern 103 of described active layer comprises amorphous silicon pattern and n+ amorphous silicon pattern, described active layer retains pattern 103b and comprises that amorphous silicon retains pattern and the n+ amorphous silicon retains pattern; In the situation that the pattern 103 of described active layer comprises the burning article pattern, described active layer retains pattern 103b and comprises that metal oxide retains pattern.
Further, shown in figure 8, described array base palte also comprises the pattern 107 of the passivation layer that is arranged on described pixel region 10a and described GOA district 10b and the public electrode 108 that is arranged on described pixel region 10a.
For a senior super dimension conversion hysteria array base palte, described public electrode 108 all is arranged on described array base palte with described pixel electrode 106, and by the multi-dimensional electric field formed in same plane, can make the liquid crystal molecule of all orientations in liquid crystal cell all produce rotation, thereby improve the operating efficiency of liquid crystal and increase light transmittance.A senior super dimension switch technology can improve the picture quality of display floater, has high-resolution, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples.
The embodiment of the present invention also provides a kind of display unit, comprises above-mentioned array base palte.
Although in above-described embodiment, 1042 with pixel electrode 106, be connected to example and be illustrated to drain, yet those skilled in the art is understood that, the interchangeability on structure and composition due to transistorized source electrode 1041 and drain electrode 1042, also source electrode 1041 can be connected with pixel electrode 106, this belongs to the equivalents of the above embodiment of the present invention.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (10)
1. an array base palte, comprise pixel region and GOA district; Described pixel region comprises the grid be arranged on substrate, pattern, source electrode and the drain electrode of active layer, the pixel electrode be electrically connected to described drain electrode, and the pattern setting of gate insulation layer is in described pixel region and described GOA district; It is characterized in that, also comprise be arranged on described GOA district and described grid with the first electrode of floor, with the pattern of described active layer with the active layer of floor retain pattern, with described source electrode and drain electrode the second electrode with floor, with the first transparency electrode of same layer of described pixel electrode;
Wherein, described active layer reservation pattern and described the second electrode include the via hole that exposes described the first electrode; Described the first transparency electrode is arranged on described the second electrode top and all is electrically connected to described the second electrode and described the first electrode;
Described pixel region also comprise be arranged on described source electrode top and with second transparency electrode of described pixel electrode with layer, described the second transparency electrode is electrically connected to described source electrode.
2. array base palte according to claim 1, is characterized in that, the pattern of described active layer comprises amorphous silicon pattern and n+ amorphous silicon pattern; Perhaps
The pattern of described active layer comprises the burning article pattern.
3. array base palte according to claim 1 and 2, is characterized in that, described array base palte also comprises the pattern of the passivation layer that is arranged on described pixel region and described GOA district and the public electrode that is arranged on described pixel region.
4. a display unit, is characterized in that, comprises the described array base palte of claims 1 to 3 any one.
5. the preparation method of an array base palte, described array base palte comprises pixel region and GOA district; It is characterized in that, comprising:
By a composition technique, form grid on the underlay substrate of described pixel region, form the first electrode on the underlay substrate in described GOA district;
By a composition technique, form the pattern of gate insulation layer on the substrate in described pixel region and described GOA district, form the first pattern and be positioned at the second pattern above described the first pattern on the substrate of described pixel region, on the substrate in described GOA district, form with described the first pattern with the active layer of floor retain pattern, with second electrode of described the second pattern with floor, and described active layer reservation pattern and described the second electrode include the via hole that exposes described the first electrode; Wherein, the pattern of the corresponding active layer of described the first pattern, the corresponding source electrode of described the second pattern and drain electrode;
By a composition technique, at least form described source electrode and drain electrode, the pixel electrode be electrically connected to described drain electrode on the substrate of described pixel region, be positioned at above described source electrode and the second transparency electrode be electrically connected to described source electrode, on the substrate in described GOA district, form and be positioned at above described the second electrode and the first transparency electrode all be electrically connected to described the second electrode and described the first electrode.
6. method according to claim 5, it is characterized in that, the described composition technique of passing through one time, form the pattern of gate insulation layer on the substrate in described pixel region and described GOA district, form the first pattern and be positioned at the second pattern above described the first pattern on the substrate of described pixel region, on the substrate in described GOA district, form with described the first pattern with the active layer of floor retain pattern, with second electrode of described the second pattern with floor, and described active layer reservation pattern and described the second electrode include the via hole that exposes described the first electrode; Wherein, the pattern of the corresponding active layer of described the first pattern, the corresponding source electrode of described the second pattern and drain electrode comprise:
Form successively gate insulation layer film, amorphous silicon membrane and n+ amorphous silicon membrane and metallic film on described substrate, and form photoresist on described metallic film;
After adopting intermediate tone mask plate or gray tone mask plate to be exposed, develop the substrate that is formed with described photoresist, form the complete reserve part of photoresist, photoresist half reserve part and photoresist and remove part fully; Wherein, described photoresist is removed the to be formed via hole that exposes described the first electrode that the part correspondence is positioned at described GOA district fully; The complete reserve part correspondence of described photoresist be positioned at described first pattern to be formed of described pixel region and to be formed and described the first pattern of being positioned at described second pattern of described the first pattern top and being positioned at described GOA district with the described active layer of floor retain pattern and with described second electrode of the same floor of described the second pattern; Corresponding other zones of described photoresist half reserve part;
Adopt etching technics to remove described metallic film, described n+ amorphous silicon membrane, described amorphous silicon membrane and described gate insulation layer film that described photoresist is removed part fully, form the via hole that exposes described the first electrode;
Adopt cineration technics to remove the photoresist of described photoresist half reserve part;
Adopt etching technics to remove described metallic film, described n+ amorphous silicon membrane and the described amorphous silicon membrane exposed, form described the first pattern and described the second pattern, and with described the first pattern with the described active layer of layer retain pattern and with described second electrode of described the second pattern with layer; Wherein, described active layer reservation pattern and described the second electrode include the described via hole that exposes described the first electrode; The pattern of the corresponding described active layer of described the first pattern, the corresponding described source electrode of described the second pattern and drain electrode;
Adopt stripping technology to remove the photoresist of the complete reserve part of described photoresist.
7. method according to claim 6, it is characterized in that, the described composition technique of passing through one time, at least form described source electrode and drain electrode, the pixel electrode be electrically connected to described drain electrode on the substrate of described pixel region, be positioned at above described source electrode and the second transparency electrode be electrically connected to described source electrode, form on the substrate in described GOA district and be positioned at above described the second electrode and the first transparency electrode all be electrically connected to described the second electrode and described the first electrode comprises:
Form transparent conductive film on substrate, and form photoresist on described transparent conductive film;
By mask plate to the substrate that is formed with described photoresist exposed, development, etching, peel off after, on the substrate of described pixel region, form described active layer pattern, described source electrode and drain electrode, the pixel electrode be electrically connected to described drain electrode, be positioned at above described source electrode and the second transparency electrode be electrically connected to described source electrode, on the substrate in described GOA district, formation is positioned at above described the second electrode and the first transparency electrode all be electrically connected to described the second electrode and described the first electrode; Wherein, the pattern of described active layer comprises amorphous silicon pattern and n+ amorphous silicon pattern.
8. method according to claim 5, it is characterized in that, the described composition technique of passing through one time, form the pattern of gate insulation layer on the substrate in described pixel region and described GOA district, form the first pattern and be positioned at the second pattern above described the first pattern on the substrate of described pixel region, on the substrate in described GOA district, form with described the first pattern with the active layer of floor retain pattern, with second electrode of described the second pattern with floor, and described active layer reservation pattern and described the second electrode include the via hole that exposes described the first electrode; Wherein, the pattern of the corresponding active layer of described the first pattern, the corresponding source electrode of described the second pattern and drain electrode comprise:
Form successively gate insulation layer film, metal-oxide film and metallic film on described substrate, and form photoresist on described metallic film;
After adopting intermediate tone mask plate or gray tone mask plate to be exposed, develop the substrate that is formed with described photoresist, form the complete reserve part of photoresist, photoresist half reserve part and photoresist and remove part fully; Wherein, described photoresist is removed the to be formed via hole that exposes described the first electrode that the part correspondence is positioned at described GOA district fully; The complete reserve part correspondence of described photoresist be positioned at described first pattern to be formed of described pixel region and to be formed and described the first pattern of being positioned at described second pattern of described the first pattern top and being positioned at described GOA district with the described active layer of floor retain pattern and with described second electrode of the same floor of described the second pattern; Corresponding other zones of described photoresist half reserve part;
Adopt etching technics to remove described metallic film, described metal-oxide film and described gate insulation layer film that described photoresist is removed part fully, form the via hole that exposes described the first electrode;
Adopt cineration technics to remove the photoresist of described photoresist half reserve part;
Adopt etching technics to remove described metallic film, the described metal-oxide film exposed, form described the first pattern and described the second pattern, and with described the first pattern with the described active layer of layer retain pattern and with described second electrode of described the second pattern with layer; Wherein, described active layer reservation pattern and described the second electrode include the described via hole that exposes described the first electrode; The pattern that described the first pattern is described active layer, the corresponding described source electrode of described the second pattern and drain electrode;
Adopt stripping technology to remove the photoresist of the complete reserve part of described photoresist.
9. method according to claim 8, it is characterized in that, the described composition technique of passing through one time, at least form described source electrode and drain electrode, the pixel electrode be electrically connected to described drain electrode on the substrate of described pixel region, be positioned at above described source electrode and the second transparency electrode be electrically connected to described source electrode, form on the substrate in described GOA district and be positioned at above described the second electrode and the first transparency electrode all be electrically connected to described the second electrode and described the first electrode comprises:
Form transparent conductive film on substrate, and form photoresist on described transparent conductive film;
By mask plate to the substrate that is formed with described photoresist exposed, development, etching, peel off after, form described source electrode and drain electrode, the pixel electrode be electrically connected to described drain electrode on the substrate of described pixel region, be positioned at above described source electrode and the second transparency electrode be electrically connected to described source electrode, on the substrate in described GOA district, form and be positioned at above described the second electrode and the first transparency electrode all be electrically connected to described the second electrode and described the first electrode.
10. according to the described method of claim 5 to 9 any one, it is characterized in that, described method also comprises: the pattern that forms passivation layer on the substrate in described pixel region and described GOA district; Also form public electrode on the substrate of described pixel region.
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