CN103455132A - Embedded system power consumption estimation method based on hardware performance counter - Google Patents

Abstract

The invention discloses an embedded system power consumption estimation method based on a hardware performance counter. The method comprises the steps of classifying performance events, selecting the performance events with representativeness, calculating a Spearman's rank correlation coefficient between the number of occurrences of the performance events and the power consumption, judging the degree of correlation, selecting representative performance events, then, establishing a power consumption model by using a linear regression method, and estimating the power consumption of an embedded system. According to the embedded system power consumption estimation method based on the hardware performance counter, through analyzing the power consumption model, the change of the power consumption of a processor in a time sequence can be observed, and the working conditions of the software and hardware of the system can be subjected to adjustment according to real-time monitoring data by adopting certain strategies, so that the aims of guaranteeing system stability, prolonging battery working time or adjusting cooling equipment to guarantee performance and the like are reached, thus, performance optimization is carried out, and then, the operating efficiency of the whole system is increased.

Description

Power consumption of embedded system evaluation method based on hardware performance counter

Technical field

The present invention relates to power consumption of embedded system and calculate field, relate in particular to a kind of power consumption of embedded system evaluation method based on hardware performance counter.

Background technology

The development trend of current embedded system may be summarized to be hardware performance and constantly raises, and software size increases day by day, is faced with the too high performance issue of hardware power consumption, addresses this problem and must be studied the generation of hardware power consumption in embedded system.

Early stage flush bonding processor due to the risc instruction sets that adopt simple in structure more, and performance requirement is not high, and dominant frequency is lower, does not produce serious power problems, and power problems only is present in the PC system higher to performance requirement usually.In recent years along with the continuous increase of embedded system for hardware performance requirements, in order to obtain higher performance, its framework is constantly complicated, some technology of in the past using on high-performance processor also start to appear in flush bonding processor simultaneously, these technology, when having brought the processor performance develop rapidly, also make the complexity of processor and power consumption become and are difficult to control.

The most processor has all used dynamic power management techniques in order to reduce power consumption, can be according to clock and operating voltage and the electric current of computation requirement dynamic adjustments processor, this respect technology mainly comprises dynamic resource dormancy (being called for short DRS) and dynamic rate adjusting (being called for short DSS).The dynamic resource dormancy, for energy-conservation and dormancy or close idle resource, wakes resource dynamic up while needing again.Current main flow processor is all supported the dynamic dormancy technology; It is the operating rate of dynamic adjustments equipment that dynamic rate is regulated, when there is a large amount of communication in calculating and synchronizes, equipment must be waited for slow devices after completing its load of bearing fast, now the two-forty of equipment there is no need fast, reduce the speed of quick equipment, can reduce system power dissipation and loss system performance not, thereby realize the energy optimization of system.

But this type of technology is from the angle of software development, the developer can't know that its definite duty also can't effectively intervene.In addition, flush bonding processor has its unique application scenario, for the mobile device battery capacity, is also limited.Therefore when design, the power consumption of embedded system and performance must be joined together to be considered, be found the equilibrium point an of the best.For this reason, must be able to find a kind of method of describing power consumption in embedded system.Therefore in embedded system, the power consumption of processor has occupied a big chunk of overall power, and usually can bring the problem of heat radiation, and it is very necessary finding a kind of method that can describe the flush bonding processor power consumption that running software brings.

Summary of the invention

The object of the present invention is to provide a kind of power consumption of embedded system evaluation method based on hardware performance counter, by the classification to performance event, select representative performance event, utilize the frequency of power consumption information and performance event, adopt the method based on the Spearman rank correlation coefficient judgement degree of correlation to carry out the selection of the corresponding event of hardware performance counter; Then utilize the method based on multiple linear regression model to carry out the foundation of system power dissipation model.

A kind of power consumption of embedded system evaluation method based on hardware performance counter comprises the following steps:

1) processor of embedded system is carried out to Module Division by function, and the performance event that processor is occurred is classified by function;

Generally, often according to function, processor is divided to module, description according to predefine performance event in processor, can be manually by all performance events corresponding to different functional modules, classified, for example: for the read-write operation of data, can be divided in a class event relevant with internal memory.

2) collect power consumption and the frequency of all properties event in the operation for embedded system time;

The present invention adopts performance counter, collects the frequency of corresponding performance event, and described performance counter can be collected the number of times that one or more performance events occur simultaneously.In test procedure, the performance events of all needs statistics that allow as much as possible occur, for example, this class performance event of floating-point operation is carried out to the power consumption statistics, in test procedure, not only need adding, subtract, four kinds of computings of multiplication and division are repeatedly calculated, also need multi-group data is tested simultaneously.According to the test procedure of writing, the power consumption data of all properties event while collecting operation, and by reading the frequency of corresponding performance event counter records all properties event;

3) frequency of calculated performance event and the Spearman rank correlation coefficient between power consumption, the judgement degree of correlation is also chosen representative performance event;

Spearman's correlation coefficient or be called the ρ of Spearman, generally use Greek alphabet ρ _sor r (rho) _smean.Spearman's correlation coefficient is the index of the statistic correlation between two variablees of a non-parametric tolerance, is used for assessment when describe the power of two relations between variable with monotonic quantity.

In actual computation, the method for more simply calculating Spearman's correlation coefficient is arranged.If original data x _iand y _iarranged note x ' by the order according to from big to small _iand y ' _ifor former x _iand y _ithe position at data place after arrangement, can be by x ' _iand y ' _ibe called variable x _iand y _irank, d _i=x ' _i-y ' _ifor x _iand y _iorder take second place poor.

If during without identical rank, related coefficient can be calculated by following formula:

$\mathrm{\ρ}=1-\frac{6\mathrm{\Σ}{d}_i^2}{n(n^2-1)}$

In formula, ρ means Spearman's correlation coefficient, and n means sample size.

If there is identical rank to exist, so just need to calculate the Pearson's linearly dependent coefficient between rank, by following formula, calculated:

${\mathrm{\ρ}}_s=\frac{{\mathrm{\Σ}}_i(x_i-\stackrel{\‾}{x})(y_i-\stackrel{\‾}{y})}{\sqrt{{\mathrm{\Σ}}_i{(x_i-\stackrel{\‾}{x})}^2{\mathrm{\Σ}}_i{(y_i-\stackrel{\‾}{y})}^2}}$

In formula, ρ _smean Pearson's linearly dependent coefficient, i means the number of data,

mean data x _imean value,

mean data y _imean value.

An identical value must have identical rank in a column data, and the rank adopted in calculating so is exactly numerical value at the mean value of position when arranging from big to small.

What the sign symbol of Spearman rank correlation coefficient meaned is the direction contacted between variable x and y.If y increases along with the increase of x, the symbol of Spearman rank correlation coefficient is positive so, otherwise the symbol of Spearman rank correlation coefficient is born.The increase that Spearman rank order correlation coefficient 0 means along with x, the trend that y does not increase or reduces.Along with x and y more and more approach the funtcional relationship of strictly monotone, the Spearman rank correlation coefficient is numerically increasing.When x, y have concerning of strictly singly increasing, the Spearman rank order correlation coefficient 1 between them, otherwise, when x, y have concerning of strictly singly subtracting, Spearman rank order correlation coefficient-1.

According to the Spearman rank correlation coefficient, select in the performance event class highly with the power consumption of processing unit degree of correlation, and itself there is certain representational performance event.

If the Spearman rank correlation coefficient between the frequency of performance event and power consumption is larger, the corresponding degree of correlation is higher, and this performance event is representative performance event.When if the degree of correlation that two or more performance events are corresponding approaches, can choose one of them performance event as representative performance event.

4) collect number of times and the power consumption information that performance event representative in step 3) occurs;

Number according to used processor performance counter, be configured performance counter, comprising: the selection of counter, configure the operations such as performance event that each performance counter correspondence is added up.The operation test procedure, record power consumption information, generally can calculate power consumption by operating voltage and working current, by reading the performance counter that each performance event is corresponding, adds up the number of times that each performance event occurs simultaneously.

5) according to the number of times occurred in step 4) and power consumption Information generation linear regression model (LRM), and calculate the power consumption of processing unit of embedded system.

For controllable variable x ₁, x ₂..., x _pwith stochastic variable y independently observe x n time _i1, x _i2..., x _ip; Y, i=1 wherein, 2 ..., n, y is about x ₁, x ₂..., x _pthe heavy generalized linear regression model of p as follows:

In formula, y means the observation vector of dependent variable, y ₁y ₂y _nmean independently observed result n time, x means controllable variable, x _npmean n observation of controllable variable, f ₁, f ₂..., f _pfor p function, β means the coefficient variation that need to try to achieve, β ₁β ₂β _nexpression is corresponding to the coefficient of n observation, and ε means stochastic error vector, ε ₁ε ₂ε _nexpression is corresponding to the error of n observation.

The linear regression model (LRM) adopted in this method is linear, while needing constant term is arranged in model, row 1 element should be arranged in x, therefore uses the described linear regression model (LRM) of following formula:

In formula, y means the observation vector of dependent variable, y ₁y ₂y _nmean independently observed result n time, x means controllable variable, x _npmean n observation of controllable variable, β means the coefficient variation that need to try to achieve, β ₁β ₂β _nexpression is corresponding to the coefficient of n observation, and ε means stochastic error vector, ε ₁ε ₂ε _nexpression is corresponding to the error of n observation.

Y is the observed reading of power consumption of processing unit in the method, and first of x classifies 1 as, the x of back _npthe value of each performance counter when every a line correspondence of part is once sampled.In linear regression analysis, dependent variable is an independent variable x _ilinear combination, therefore, equation of linear regression is as shown in the formula described:

y=β ₀+β ₁x ₁+β ₂x ₂+…+β _nx _n+ε

Wherein: ε is the random disturbance item, also is random entry or error term or residual error.Because the unlikely just formation straight line very luckily of the value of each point, therefore will introduce the random disturbance item.Linear regression is exactly to calculate suitable weight beta _imake final ε reach minimum.

Beneficial effect of the present invention is:

1, the invention provides quick, the effective way of obtaining flush bonding processor power consumption information to one of embedded software developing personnel;

2, the present invention's monitoring is the power consumption of processor integral body, does not therefore need to consider each process power consumption separately, thereby also just need not consider the problem of process scheduling time sheet;

3, the analysis result of power consumption information, can observe the variation of the power consumption of processor according to the time sequencing generation, also can to the software and hardware working condition of system, adopt certain strategy to be adjusted according to Real-time Monitoring Data, guarantee system stability to reach, extend battery working time or regulate the purposes such as heat dissipation equipment guaranteed performance;

4, this model is expanded, can be set up corresponding power consumption model to each core in multiple nucleus system, the estimation power consumption situation, carry out performance optimization.

The accompanying drawing explanation

The generation step that Fig. 1 is power consumption model in the present invention;

Fig. 2 is the software system structure used in the present invention;

The workflow diagram that Fig. 3 is the upper Matlab program of PC in the present invention;

The use flow process that Fig. 4 is performance counter of the present invention;

Fig. 5 is power consumption that in the present invention, model calculates and the comparison diagram of actual power loss;

The power consumption comparison diagram that Fig. 6 is the lmbench test procedure;

The error map that Fig. 7 is the lmbench test procedure;

The power consumption comparison diagram that Fig. 8 is the nbench test procedure;

The error map that Fig. 9 is the nbench test procedure;

The power consumption comparison diagram that Figure 10 is the unixbench test procedure;

The error map that Figure 11 is the unixbench test procedure.

Embodiment

As shown in Figure 1, Fig. 1 is the process flow diagram that in the present invention, the system power dissipation model is set up.The present embodiment is used single core processor ARM Cortex-A8 comparatively commonly used in current embedded system as analytic target, and the power consumption of the ARM core of ARM Cortex-A8 processor is analyzed; The test platform adopted is the EVM8168 evaluation board of TI, on this plate, has the voltage and current situation of INA220 power consumption monitoring chip Ke Duimei road power supply to be monitored.Simultaneously, 430 single-chip microcomputers are arranged on this evaluation board, can the data of INA220 chip be gathered, and export by serial ports.In addition, the present invention selects Matlab and Linux as test environment, and purpose is to take full advantage of Matlab to drive under the Linux of the advantage aspect data analysis and ARM Cortex-A8 performance counter.

Figure 2 shows that the structure of system software model, make EVM8168 and PC carry out synchronous communication, the driver of runnability counter on EVM8168, and realize the transmission of counter data; Move the Matlab program on PC, read the power consumption monitoring information of serial ports, comprising operating voltage and working current, in addition, create the TCP network and connect, collect the counter data sent on development board.Figure 3 shows that the workflow diagram of the upper Matlab program of PC.

The present invention specifically realizes according to following step:

Step 1, the method for employing based on the Spearman rank correlation coefficient judgement degree of correlation are carried out the selection of the corresponding event of hardware performance counter;

Step 1.1: processor is carried out to Module Division according to difference in functionality, all performance events, corresponding to different functional modules, are classified;

In the experiment porch ARM Cortex-A8 processor of choosing in the present invention, always having 49 performance events can be counted by configuration, performance counter only has 5, wherein 4 performance counters are universal performance counters, can to 48 performance events, be counted by configuration, another performance counter is the cpu cycle counter, can only be counted for the CPU_CYCLES event.And 48 can be selected by the performance counter of configure generic, there are 4 performance events nonsensical for this paper, they are respectively the PMNC_SW_INCR events, PMU0_EVENTS event, PMU1_EVENTS event and PMU_EVENTS event.So the performance event number that the usability counter is counted is 44.

The floating-point operation of ARM Cortex-A8 has comprised two kinds of instruction set, VFP instruction and SIMD instruction, although use two kinds of different hardware mechanisms, these instructions are all carried out in the NEON coprocessor, therefore NEON coprocessor dependent event can be divided into to an independent class.

The high-speed cache of ARM Cortex-A8 comprises L1, L2 two-level cache, and the access that all L1, L2 are relevant and miss event can classify as the internal memory dependent event.

Under the Cortex-A8 framework, two ALU streamlines are arranged, can process two logical operations simultaneously.Because the relevant pipeline stall brought of branch prediction failure and data is unavoidable, therefore can be using the pipeline stall event as the 3rd class performance event.

The dependent event of other programmable counter PC, and command operating dependent event, can be divided into separately a class and be analyzed.

Step 1.2: the configuration performance counter, write test procedure, collect the power consumption data of all properties event while moving, and record the frequency of all properties event;

Performance counter is configured, by open, close, the functions such as ioctl carry out to performance counter the configuration operation that equipment is opened sum counter.Figure 4 shows that the use flow process of performance counter.

According to step 1.1,44 performance events are divided into to four classes: Cache, NEON, Stall and PC, 4 performance events are carried out to statistical study at every turn, carry out altogether 11 times, the frequency of all 44 performance events is added up; In addition, by serially printing, go out the voltage and current information under working condition, by calculating, can obtain current power consumption.

Step 1.3: the frequency of calculated performance event and the Spearman rank correlation coefficient between power consumption, the judgement degree of correlation is selected the performance event that represents of every class event.

Calculate the Spearman rank correlation coefficient between each performance event and power consumption according to the corr function in Matlab, select the higher performance event of related coefficient, if there are a plurality of performance events to meet this requirement, then the degree of correlation between event is analyzed.If the degree of correlation of two performance events is very high, can think so and there is certain contact between these two performance events, the generation of one of them event must have another event and occur, can only retain one of them performance event for such situation, by such analysis, therefrom just can exclude some performance events, and then select representative performance event.

Step 2, the method for utilization based on multiple linear regression model are carried out the foundation of system power dissipation model.

Step 2.1: the configuration performance counter, according to test procedure, the performance event of selecting in step 1 is counted, collect the frequency of power consumption information and performance event;

According to step 1.3, select four representational events and be respectively from 44 performance events: DCACHE_ACCESS event, NEON_CYCLES event, CYCLES_INST_STALL event and PC_BRANCH_EXECUTED event.The operation test procedure, collect the power consumption information of these four events and the statistics of performance counter.

Step 2.2: according to the frequency of power consumption data and performance event, generate linear regression model (LRM);

Regress function according in Matlab, obtain the design parameter in linear regression model (LRM), obtains linear regression model (LRM) as follows:

p _estimate=4.8380×10 ⁶+3.7384×10 ^-4×N _CACHE+9.8095×N _PC

-2.0740×10 ^-4×N _STALL+1.6455×10 ^-5×N _NEON

Wherein, p _estimatethe power consumption of processing unit that representative model calculates, unit is microwatt; N _cACHErepresent the frequency of DCACHE_ACCESS event in the unit interval; N _pCthe frequency of PC_BRANCH_EXECUTED event in the representation unit time; N _sTALLrepresent the frequency of CYCLES_INST_STALL event in the unit interval; N _nEONthe frequency that means the NEON_CYCLES event.

As shown in Figure 5, what wherein dotted line meaned is the actual power loss of processor, and what solid line meaned is the power consumption that model calculates; From the power consumption comparison diagram shown in Fig. 5, can find out, model can carry out good expression for the situation of change of power consumption of processing unit, particularly for the description of power consumption of processing unit variation tendency, the related coefficient that actual power loss and model calculate the gained power consumption has reached 0.9152, illustrates that its degree of correlation is very high.

Step 3: write multiple test procedure, the linear regression model (LRM) generated in step 2.2 is verified.

Having chosen three kinds in the present invention and have difference test procedure targetedly in test, is respectively lmbench, nbench and unixbench.

Lmbench is a test program set of increasing income, meet the POSIX standard, there is good portability, lmbench is tested mainly for various bandwidth and the delay of operating system integral body, and content measurement comprises: the performance index such as the bandwidth of memory read-write, the bandwidth of memory copying and operating system pipeline bandwidth.The power consumption comparison diagram that Fig. 6 is the lmbench test procedure, the error map that Fig. 7 is the lmbench test procedure, as can be seen from the figure its variation tendency is identical with actual measured results, can show that by calculating its related coefficient the variation tendency of model result and the rank correlation coefficient of actual measured results reach 0.8648, thus can think model still can be on very magnanimous the variation tendency of reflection power consumption.

Nbench is a test procedure of increasing income, and by the calculated performance of a series of calculating test processor, nbench is for testing the calculated performance of each processor and being contrasted.Comprise multiple calculating in nbench, as sequence, floating-point operation, Fourier transform, Huffman compression and neural network etc.The power consumption comparison diagram that Fig. 8 is the nbench test procedure, the error map that Fig. 9 is the nbench test procedure, as can be seen from the figure, the accuracy of model can't be satisfactory, but model still can reflect size and the variation tendency of power consumption to a certain extent.

Unixbench is a test procedure set that is directed to the design of UNIX type operating system, comprise multiple test event, comprise: integer calculations, Floating-point Computation, process creation, file copy and context switching etc. are tested, the unixbench test duration is the longest, test event is maximum, and the software operation of containing is also perfect.The power consumption comparison diagram that Figure 10 is the unixbench test procedure, the error map that Figure 11 is the unixbench test procedure can find out that for unixbench model has effect preferably.

Claims (7)

1. the power consumption of embedded system evaluation method based on hardware performance counter, is characterized in that, comprises following step:

1) processor of embedded system is carried out to Module Division by function, and the performance event that processor is occurred is classified by function;

2) collect power consumption and the frequency of all properties event in the operation for embedded system time;

3) frequency of calculated performance event and the Spearman rank correlation coefficient between power consumption, the judgement degree of correlation is also chosen representative performance event;

4) collect number of times and the power consumption information that performance event representative in step 3) occurs;

5) according to the number of times occurred in step 4) and power consumption Information generation linear regression model (LRM), and calculate the power consumption of processing unit of embedded system.

2. the power consumption of embedded system evaluation method based on hardware performance counter as claimed in claim 1, is characterized in that, the pass between described power consumption and frequency is:

$\mathrm{Power}=\underset{i}{\mathrm{\Σ}}(a_i\×\mathrm{event}\_{\mathrm{times}}_i)+\mathrm{\θ}$

In formula, Power means power consumption, and i means the type of performance event event, event_times _imean performance event event _ithe number of times occurred, a _imean performance event event _ifrequency event_times _ifor the influence coefficient of power consumption, θ means the random disturbance item.

3. the power consumption of embedded system evaluation method based on hardware performance counter as claimed in claim 2, it is characterized in that, the frequency of performance event and the Spearman rank correlation coefficient between power consumption are larger, and the corresponding degree of correlation is higher, and this performance event is representative performance event.

4. the power consumption of embedded system evaluation method based on hardware performance counter as claimed in claim 1, it is characterized in that, when if the degree of correlation that two or more performance events are corresponding approaches, can choose one of them performance event as representative performance event.

5. the power consumption of embedded system evaluation method based on hardware performance counter as claimed in claim 4, is characterized in that, in step 2) and step 4) in, adopt performance counter, collect the frequency of corresponding performance event.

6. the power consumption of embedded system evaluation method based on hardware performance counter as claimed in claim 5, is characterized in that, described performance counter can be collected the number of times that one or more performance events occur simultaneously.

7. the power consumption of embedded system evaluation method based on hardware performance counter as claimed in claim 1, is characterized in that, the linear regression model (LRM) in described step 5) is:

In formula, y means the observation vector of dependent variable, y ₁y ₂y _nmean independently observed result n time, x means controllable variable, x _npmean n observation of controllable variable, β means the coefficient variation that need to try to achieve, β ₁β ₂β _nexpression is corresponding to the coefficient of n observation, and ε means stochastic error vector, ε ₁ε ₂ε _nexpression is corresponding to the error of n observation.

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