CN103441109A - Semiconductor element, semiconductor packaging structure and manufacturing method thereof - Google Patents
Semiconductor element, semiconductor packaging structure and manufacturing method thereof Download PDFInfo
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- CN103441109A CN103441109A CN2013104003131A CN201310400313A CN103441109A CN 103441109 A CN103441109 A CN 103441109A CN 2013104003131 A CN2013104003131 A CN 2013104003131A CN 201310400313 A CN201310400313 A CN 201310400313A CN 103441109 A CN103441109 A CN 103441109A
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- thermal interface
- interface material
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000004806 packaging method and process Methods 0.000 title abstract description 4
- 239000000463 material Substances 0.000 claims abstract description 105
- 229910052738 indium Inorganic materials 0.000 claims abstract description 82
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 77
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims abstract description 54
- 239000011701 zinc Substances 0.000 claims abstract description 54
- 229910052725 zinc Inorganic materials 0.000 claims abstract description 54
- 229910000765 intermetallic Inorganic materials 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims description 70
- 239000002184 metal Substances 0.000 claims description 70
- 238000007747 plating Methods 0.000 claims description 51
- 239000010949 copper Substances 0.000 claims description 47
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 37
- 229910052802 copper Inorganic materials 0.000 claims description 37
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 18
- 229910052759 nickel Inorganic materials 0.000 claims description 14
- 239000013078 crystal Substances 0.000 claims description 8
- 229910000906 Bronze Inorganic materials 0.000 claims description 6
- 239000010974 bronze Substances 0.000 claims description 6
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000843 powder Substances 0.000 claims description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910000756 V alloy Inorganic materials 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- 239000011651 chromium Substances 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims description 5
- 150000002815 nickel Chemical class 0.000 claims description 5
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 12
- 238000001465 metallisation Methods 0.000 abstract description 8
- 229910001297 Zn alloy Inorganic materials 0.000 abstract description 4
- 230000017525 heat dissipation Effects 0.000 abstract 1
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 35
- 239000000203 mixture Substances 0.000 description 13
- 239000007788 liquid Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 230000036962 time dependent Effects 0.000 description 8
- 239000007789 gas Substances 0.000 description 5
- 150000002471 indium Chemical class 0.000 description 5
- 239000011800 void material Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910016334 Bi—In Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- MPZNMEBSWMRGFG-UHFFFAOYSA-N bismuth indium Chemical compound [In].[Bi] MPZNMEBSWMRGFG-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000009916 joint effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
The invention relates to a semiconductor element, a semiconductor packaging structure and a manufacturing method thereof. The semiconductor device includes a semiconductor die, a backside metallization, a thermal interface material, and a first intermetallic compound. The back side metallization is located on a surface of the semiconductor die. The thermal interface material is located on the back side metallization and comprises an indium zinc alloy. The first intermetallic compound is located between the backside metallization and the thermal interface material and comprises indium and not zinc. Therefore, after the reflow process, the bonding effect and the heat dissipation effect can be improved.
Description
Technical field
The invention relates to a kind of semiconductor element, semiconductor package and manufacture method thereof.In detail, the invention relates to a kind of semiconductor element, semiconductor package and manufacture method thereof with dorsal part plating (Back Side Metallization, BSM) and thermal interface material (Thermal Interface Material, TIM).
Background technology
In the known semiconductor encapsulating structure, usually can cover a fin, go out with the back side of the chip on contact substrate and the hot type that chip is produced.Because the material of this fin is copper, and the material of this chip is silicon, and therefore, the joint effect of the two and radiating effect are neither good.In order to improve above-mentioned shortcoming, a solution is to set up dorsal part plating (Back Side Metallization at this chip back, BSM) and thermal interface material (Thermal Interface Material, TIM), and this fin first contacts this thermal interface material, then make this fin be engaged to this thermal interface material through reflow process.
This dorsal part plating comprises several layers of metal level, and this thermal interface material comprises at least one metal level.At present known have several this dorsal part plating and the material combination of this thermal interface material to be suggested, yet at present in known technology, all inevitably, in reflow process, can in thermal interface material, produce emptying aperture (Void), thereby impact engages effect and radiating effect.In addition, at present the required temperature of the reflow process of known technology is quite high.
Summary of the invention
The one side of this exposure is about a kind of semiconductor element.In one embodiment, this semiconductor element comprises semiconductor crystal grain, a dorsal part plating (Back Side Metallization, BSM), a thermal interface material (Thermal Interface Material, TIM) and one first Jie's metallic compound (Intermetallic Compound, IMC).This semiconductor grain has a first surface and a second surface.This dorsal part plating is positioned at the second surface of this semiconductor grain.This thermal interface material is positioned on this dorsal part plating, and comprises indium kirsite (In-Zn alloy).This first Jie metallic compound, between this dorsal part plating and this thermal interface material, and comprises indium and does not comprise zinc.
This exposure be about a kind of semiconductor package on the other hand.In one embodiment, this semiconductor package comprises a substrate, semiconductor crystal grain, a dorsal part plating, a thermal interface material, a fin, one first Jie's metallic compound and second Jie's metallic compound.This semiconductor grain has a first surface and a second surface, and the first surface of this semiconductor grain is to be electrically connected to this substrate.This dorsal part plating is positioned at the second surface of this semiconductor grain.This thermal interface material is positioned on this dorsal part plating, and comprises the indium kirsite.This fin covers this semiconductor grain to contact this thermal interface material, and at least comprises a bronze medal layer.This first Jie metallic compound, between this dorsal part plating and this thermal interface material, and comprises indium and does not comprise zinc.This second Jie metallic compound, between this thermal interface material and this fin, and comprises indium and does not comprise zinc.
This exposure be the manufacture method about a kind of semiconductor package on the other hand.In one embodiment, this manufacture method comprises the following steps: (a) form on the gold-plated second surface that belongs to semiconductor crystal grain of a dorsal part; (b) first surface of this semiconductor grain is electrically connected to a substrate; (c) provide the material of a removal oxide to this dorsal part plating; (d) form a thermal interface material on this dorsal part plating, wherein this thermal interface material comprises the indium kirsite; (e) fin is covered to this semiconductor grain to contact this thermal interface material, wherein this fin at least comprises a bronze medal layer; And (f) carry out reflow (Reflow), to generate one first Jie's metallic compound and one second Jie's metallic compound, wherein this first Jie metallic compound, between this dorsal part plating and this thermal interface material, and comprises indium and does not comprise zinc; This second Jie metallic compound, between this thermal interface material and this fin, and comprises indium and does not comprise zinc.
In the present embodiment, have the state of solid-liquid due to this indium kirsite.Therefore, in reflow process, if produce emptying aperture (Void) in this thermal interface material, this liquid indium kirsite can fill up this emptying aperture at once, make after reflow process, can there be any emptying aperture in this thermal interface material, and can increase, between this thermal interface material and this fin, engages effect and radiating effect.
The accompanying drawing explanation
Fig. 1 shows the cross-sectional schematic of an embodiment of semiconductor package of the present invention.。
Fig. 2 shows the local enlarged diagram of the regional A of Fig. 1.
Fig. 3 and Fig. 4 show the schematic diagram of an embodiment of the manufacture method of semiconductor package of the present invention.
Fig. 5 shows the schematic diagram of another embodiment of the manufacture method of semiconductor package of the present invention.
Fig. 6 shows the liquid-solid equilibria phasor of indium kirsite.
Fig. 7 shows zinc shared ratio, liquidus temperature and graph of a relation of reflow time in the indium kirsite, and wherein reflow temperature is 200 ℃.
Fig. 8 shows zinc shared ratio, liquidus temperature and graph of a relation of reflow time in the indium kirsite, and wherein reflow temperature is 250 ℃.
Fig. 9 shows the cross-sectional schematic of another embodiment of semiconductor package of the present invention.
Figure 10 shows the local enlarged diagram of the regional B of Fig. 9.
Embodiment
With reference to figure 1, show the cross-sectional schematic of an embodiment of semiconductor package of the present invention.This semiconductor package 1 comprises a substrate 12, semiconductor element 10 and a fin 20.This substrate 12 is a base plate for packaging, and it comprises a first surface 121, the electrical Connection Element (not shown) of a second surface 122 and several inside.These inner electrically Connection Elements are to be electrically connected this first surface 121 and this second surface 122.
This semiconductor element 10 comprises semiconductor crystal grain 14, several projection 15, a dorsal part plating (Back Side Metallization, BSM) 16 and one thermal interface material 18.
This semiconductor grain 14 comprises a first surface 141 and a second surface 142.
These projections 15 are the first surfaces 141 that are positioned at this semiconductor grain 14, and are electrically connected the second surface 122 of the first surface 141 of this semiconductor grain 14 to this substrate 12.That is this semiconductor grain 14 is that chip bonding is to this substrate 12.
This dorsal part plating 16 is to be positioned on the second surface 142 of this semiconductor grain 14.
This thermal interface material 18 is to be positioned on this dorsal part plating 16.
This fin 20 covers this semiconductor grain 14 to contact this thermal interface material 18.In the present embodiment, it more is engaged to the second surface 122 of this substrate 12 this fin 20, in order to the hot type that this semiconductor grain 14 is produced, goes out.This fin 20 at least comprises a bronze medal layer, and in the present embodiment, the material of this fin 20 is copper.
With reference to figure 2, show the local enlarged diagram of the regional A of Fig. 1.As shown in the figure, this dorsal part plating 16 comprises several layers of metal level, that is this dorsal part plating 16 can be layer of metal layer, two layers of metal level or metal level more than three layers.In the present embodiment, this dorsal part plating 16 sequentially comprises a first metal layer 161, one second metal level 162 and one the 3rd metal level 163.This first metal layer 161 is to be positioned on the second surface 142 of this semiconductor grain 14, and is aluminium lamination, titanium layer or chromium layer.This second metal level 162 is to be positioned on this first metal layer 161, and is nickel dam or nickel-vanadium alloy layer.The 3rd metal level 163 is to be positioned on this second metal level 162, and is the copper layer.In other words, these dorsal part plating 16 the top metal levels are the copper layer.Preferably, this first metal layer 161 and this second metal level 162 are to be formed by sputter, and the copper layer of the 3rd metal level 163 is comprised of a sputter copper and an electro-coppering, and wherein this electro-coppering is to be positioned on sputter copper, and its thickness is about 5 μ m.
This thermal interface material 18 is to be positioned on the 3rd metal level 163, and comprises at least one metal level.In the present embodiment, this thermal interface material 18 is the single-layer metal layer, and its material is indium kirsite (In-Zn alloy), and in this indium kirsite, the percentage by weight of zinc is 5wt% to 30wt%.Yet in other embodiments, the material of this thermal interface material 18 is bismuth indium kirsite (Bi-In alloy).The copper layer of this fin 20 directly contacts this thermal interface material 18.
After reflow process, these fin 20 meetings and this thermal interface material 18 fluid-tight engagement can become one first Jie's metallic compound (Intermetallic Compound, IMC), 181 and 1 second Jie's metallic compound 182 simultaneously in this thermal interface material 18.This first Jie metallic compound 181 is between the 3rd metal level 163 and this thermal interface material 18 of this dorsal part plating 16, and it is that indium in this thermal interface material 18 reacts with the copper of the 3rd metal level 163 and the Cu that forms
11in
9.Therefore, this first Jie metallic compound 181 comprises indium and does not comprise zinc.This second Jie metallic compound 182 is between this thermal interface material 18 and this fin 20, and it is that indium in this thermal interface material 18 reacts with the copper of this fin 20 and the Cu that forms
11in
9.Therefore, this second Jie metallic compound 182 comprises indium and does not comprise zinc.
Because this indium kirsite has the state of solid-liquid.Therefore, in reflow process, if the interior generation emptying aperture of this thermal interface material 18 (Void), this liquid indium kirsite can fill up this emptying aperture at once, make after reflow process, can not have any emptying aperture in this thermal interface material 18, and can increase this thermal interface material 18 and 20 of this fin engage effect and radiating effect.
With reference to figure 3 and Fig. 4, the schematic diagram of an embodiment of the manufacture method of demonstration semiconductor package of the present invention.With reference to figure 3, form a dorsal part plating 16 in the second surface 142 of semiconductor crystal grain 14.This dorsal part plating 16 comprises several layers of metal level.In the present embodiment, this dorsal part plating 16 sequentially comprises a first metal layer 161, one second metal level 162 and one the 3rd metal level 163(Fig. 2).This first metal layer 161(is for example: aluminium lamination, titanium layer or chromium layer) first be formed on the second surface 142 of this semiconductor grain 14.Then, this second metal level 162(is for example: nickel dam or nickel-vanadium alloy layer) be formed on this first metal layer 161.Then, the 3rd metal level 163(for example: the copper layer) be formed on this second metal level 162.Preferably, this the first metal layer 161 and this second metal level 162 are to be formed by sputter, the copper layer of the 3rd metal level 163 is first to form a sputter copper on this second metal level 162, then forms an electro-coppering on this sputter copper, and the thickness of this electro-coppering is about 5 μ m.
Then, this semiconductor grain 14 is electrically connected to a substrate 12.In the present embodiment, this substrate 12 is a base plate for packaging, and it comprises a first surface 121, the electrical Connection Element (not shown) of a second surface 122 and several inside.These inner electrically Connection Elements are to be electrically connected this first surface 121 and this second surface 122.This semiconductor grain 14 more comprises a second surface 142 and several projection 15.These projections 15 are the first surfaces 141 that are positioned at this semiconductor grain 14.This semiconductor grain 14 utilizes these projection 15 chip bondings to this substrate 12, makes the first surface 141 of this semiconductor grain 14 be electrically connected to the second surface 122 of this substrate 12.
With reference to figure 4, provide the material of a removal oxide to this dorsal part plating 16, to prevent this dorsal part plating 16, because of oxidation, can't engage.In the present embodiment, the material of this removal oxide is scaling powder (Flux) 164, and it is the back side that is formed at this dorsal part plating 16.Then, provide a thermal interface material 18.In the present embodiment, this thermal interface material 18 is the single-layer metal paper tinsel, and its material is indium kirsite (In-Zn alloy), and in this indium kirsite, the percentage by weight of zinc is 5wt% to 30wt%.Yet in other embodiments, the material of this thermal interface material 18 is bismuth indium kirsite (Bi-In alloy).In order to remove the oxide of this thermal interface material 18, these thermal interface material 18 upper and lower surfaces all form a scaling powder 183.Be understandable that, this scaling powder 164 can be different compositions from the material of this scaling powder 183.
Then, this thermal interface material 18 is disposed on this dorsal part plating 16.Then, by a fin (Lid) 20(Fig. 1) cover this semiconductor grain 14 to contact this thermal interface material 18.In the present embodiment, this fin 20 is a fin, and it more is engaged to the second surface 122 of this substrate 12.This fin 20 at least comprises a bronze medal layer, and in the present embodiment, the material of this fin 20 is copper, and the copper layer of this fin 20 directly contacts this thermal interface material 18.
Then, carry out reflow (Reflow), to form semiconductor encapsulating structure 1, as shown in Figure 1.After reflow process, these fin 20 meetings and this thermal interface material 18 fluid-tight engagement, can become one first Jie's metallic compound (Intermetallic Compound, IMC), 181 and 1 second Jie's metallic compound 182(Fig. 2 in this thermal interface material 18) simultaneously.This first Jie metallic compound 181 is between the 3rd metal level 163 and this thermal interface material 18 of this dorsal part plating 16, and it is that indium in this thermal interface material 18 reacts with the copper of the 3rd metal level 163 and the Cu that forms
11in
9.Therefore, this first Jie metallic compound 181 comprises indium and does not comprise zinc.This second Jie metallic compound 182 is between this thermal interface material 18 and this fin 20, and it is that indium in this thermal interface material 18 reacts with the copper of this fin 20 and the Cu that forms
11in
9.Therefore, this second Jie metallic compound 182 comprises indium and does not comprise zinc.
With reference to figure 5, the schematic diagram of another embodiment of the manufacture method of demonstration semiconductor package of the present invention.The manufacture method of the present embodiment and the manufacture method of Fig. 3 to Fig. 4 are roughly the same, it does not exist together and only is, in the present embodiment, the material of this removal oxide be reducing gas (Forming Gas) 17(for example: hydrogen, nitrogen, fluorine gas or chlorine), and do not need to use scaling powder.In detail, this dorsal part plating 16 first is placed in the tunnel (Channel) that is full of this reducing gas 17 together with this semiconductor grain 14 and this substrate 12.Then, this thermal interface material 18 is disposed on this dorsal part plating 16.Then, by this fin 20(Fig. 1) cover this semiconductor grain 14 to contact this thermal interface material 18.Then, carry out reflow (Reflow).Be noted that above-mentioned all technique all carries out in the tunnel that is full of this reducing gas 17.
With reference to figure 6, show the liquid-solid equilibria phasor of indium kirsite.In figure, abscissa is that zinc shared mole in the indium kirsite is counted ratio, and ordinate is temperature.As shown in the figure, curve 31(corresponding temperature is 413K) be solidus, when curve 31 is following, the indium kirsite is solid-state; Curve 32 is liquidus curve, and when curve 32 is above, the indium kirsite is liquid; Between curve 31 and curve 32, the indium kirsite is solid-liquid.And to count ratio higher along with zinc shared mole in the indium kirsite, the zone of this solid-liquid is larger, that is the situation of solid-liquid more easily occurs.In the present embodiment, in reflow process, because the indium in this thermal interface material 18 can react with the copper of the 3rd metal level 163 and the copper of this fin 20, form Jie's metallic compound (Cu
11in
9), and zinc can not react with copper.Therefore, the shared mole number in the indium kirsite of the zinc in this thermal interface material 18 is more and more higher than regular meeting, and now, temperature is as long as surpass 413K, and this indium kirsite presents the state of solid-liquid.In the case, if the interior generation emptying aperture of this thermal interface material 18, this liquid indium kirsite can fill up this emptying aperture at once, make after reflow process, can not have any emptying aperture in this thermal interface material 18, and can increase this thermal interface material 18 and 20 of this fin engage effect and radiating effect.
With reference to figure 7, when it is 200 ℃ for setting reflow temperature, show zinc shared ratio, liquidus temperature and graph of a relation of reflow time in the indium kirsite.In figure, abscissa is the reflow time, and left side ordinate is zinc shared atomic percent (at.%) in the indium kirsite, the temperature of the liquidus curve that the right ordinate is the indium kirsite.Show the indium kirsite of two kinds of initial component ratios in figure, the first: zinc is the 10wt%(percentage by weight) the indium kirsite of indium kirsite (being equal to zinc is the 16.3at.%(atomic percent)), and the second: zinc is the 20wt%(percentage by weight) the indium kirsite of indium kirsite (being equal to zinc is the 30.5at.%(atomic percent)).In figure, four curve representatives are as follows: the first: ■ represents the time dependent liquidus temperature of indium kirsite that in initial composition, zinc is 16.3 atomic percents (at.%); ◆ represent the time dependent zinc composition of indium kirsite that in initial composition, zinc is 16.3 atomic percents (at.%); The second: ╳ represents the time dependent liquidus temperature of indium kirsite that in initial composition, zinc is 30.5 atomic percents (at.%); ▲ represent the time dependent zinc composition of indium kirsite that in initial composition, zinc is 30.5 atomic percents (at.%).In figure, can find out, be in 200 ℃ of situations in reflow temperature, along with the time increases, zinc in the indium kirsite shared ratio with increase, simultaneously the liquidus temperature of indium kirsite also with increase.For example, when after 300 seconds, the liquidus temperature of indium kirsite has increased approximately 15 ℃.
With reference to figure 8, it is 250 ℃ for setting reflow temperature, shows zinc shared ratio, liquidus temperature and graph of a relation of reflow time in the indium kirsite.In figure, abscissa is the reflow time, and left side ordinate is zinc shared atomic percent (at.%) in the indium kirsite, the temperature of the liquidus curve that the right ordinate is the indium kirsite.Show the indium kirsite of two kinds of initial component ratios in figure, the first: zinc is the 10wt%(percentage by weight) the indium kirsite of indium kirsite (being equal to zinc is the 16.3at.%(atomic percent)), and the second: zinc is the 20wt%(percentage by weight) the indium kirsite of indium kirsite (being equal to zinc is the 30.5at.%(atomic percent)).In figure, four curve representatives are as follows: the first: ■ represents the time dependent liquidus temperature of indium kirsite that in initial composition, zinc is 16.3 atomic percents (at.%); ◆ represent the time dependent zinc composition of indium kirsite that in initial composition, zinc is 16.3 atomic percents (at.%); The second: ╳ represents the time dependent liquidus temperature of indium kirsite that in initial composition, zinc is 30.5 atomic percents (at.%); ▲ represent the time dependent zinc composition of indium kirsite that in initial composition, zinc is 30.5 atomic percents (at.%).In figure, can find out, be in 250 ℃ of situations in reflow temperature, and along with the time increases, zinc shared ratio in the indium kirsite increases thereupon, and the liquidus temperature of indium kirsite also increases thereupon simultaneously.For example, when after 300 seconds, the liquidus temperature of indium kirsite has increased approximately 20 ℃.
With reference to figure 9, show the cross-sectional schematic of another embodiment of semiconductor package of the present invention.Semiconductor package 1a and the semiconductor package 1 shown in Fig. 1 of the present embodiment are roughly the same, and it does not exist together as described below.In this semiconductor package 1a of the present embodiment, this fin 20 more comprises a nickel dam 21, is positioned on the copper layer of this fin 20.This nickel dam 21 directly contacts this thermal interface material 18.
With reference to Figure 10, show the local enlarged diagram of the regional B of Fig. 9.As shown in the figure, the indium in this thermal interface material 18 reacts and forms second Jie's metallic compound 182a with this nickel dam 21 of this fin 20, and this second Jie metallic compound 182a is In
27ni
10.Therefore, this second Jie metallic compound 182a comprises indium and does not comprise zinc.Manufacture method and the manufacture method shown in Fig. 3 and Fig. 4 of the semiconductor package 1a of the present embodiment are roughly the same, become in advance a nickel dam 21 on its copper layer that only is this fin 20 that do not exist together, then this this fin 20 is covered to this semiconductor grain 14 to contact this thermal interface material 18.Then, carry out reflow, to form semiconductor encapsulating structure 1a.In reflow process, the indium in this thermal interface material 18 reacts with this nickel dam 21 of this fin 20, and therefore, the zinc proportion in this thermal interface material 18 can increase in time.
Only above-described embodiment is only explanation principle of the present invention and effect thereof, but not in order to limit the present invention.Therefore, practise in the personage of this technology and above-described embodiment is modified and change still not de-spirit of the present invention.Interest field of the present invention should be as listed as claims.
Claims (20)
1. a semiconductor element comprises:
Semiconductor crystal grain, have a first surface and a second surface;
One dorsal part plating, be positioned at the second surface of this semiconductor grain;
One thermal interface material, be positioned on this dorsal part plating, and comprise the indium kirsite; And
One first Jie's metallic compound, between this dorsal part plating and this thermal interface material, and comprise indium and do not comprise zinc.
2. semiconductor element as claimed in claim 1, is characterized in that, this dorsal part plating comprises several layers of metal level, and wherein the top metal level is the copper layer, and this first Jie metallic compound is Cu
11in
9.
3. semiconductor element as claimed in claim 2, is characterized in that, the copper layer of this dorsal part plating is comprised of a sputter copper and an electro-coppering, and the thickness of this electro-coppering is about 5 μ m.
4. semiconductor element as claimed in claim 2, it is characterized in that, this dorsal part plating sequentially comprises a first metal layer, one second metal level and one the 3rd metal level, and this first metal layer is positioned on the second surface of this semiconductor grain, and is aluminium lamination, titanium layer or chromium layer; This second metal level is positioned on this first metal layer, and is nickel dam or nickel-vanadium alloy layer; The 3rd metal level is positioned on this second metal level, and is the copper layer.
5. semiconductor element as claimed in claim 1, is characterized in that, in the indium kirsite of this thermal interface material, the content of zinc is 5wt% to 30wt%.
6. a semiconductor package comprises:
One substrate;
Semiconductor crystal grain, have a first surface and a second surface, and the first surface of this semiconductor grain is to be electrically connected to this substrate;
One dorsal part plating, be positioned at the second surface of this semiconductor grain;
One thermal interface material, be positioned on this dorsal part plating, and comprise the indium kirsite;
One fin, cover this semiconductor grain to contact this thermal interface material, and at least comprise a bronze medal layer;
One first Jie's metallic compound, between this dorsal part plating and this thermal interface material, and comprise indium and do not comprise zinc; And
One second Jie's metallic compound, between this thermal interface material and this fin, and comprise indium and do not comprise zinc.
7. semiconductor package as claimed in claim 6, is characterized in that, this dorsal part plating comprises several layers of metal level, and wherein the top metal level is the copper layer, and this first Jie metallic compound is Cu
11in
9.
8. semiconductor package as claimed in claim 7, is characterized in that, the copper layer of this dorsal part plating is comprised of a sputter copper and an electro-coppering, and the thickness of this electro-coppering is about 5 μ m.
9. semiconductor package as claimed in claim 7, it is characterized in that, this dorsal part plating sequentially comprises a first metal layer, one second metal level and one the 3rd metal level, and this first metal layer is to be positioned on the second surface of this semiconductor grain, and is aluminium lamination, titanium layer or chromium layer; This second metal level is to be positioned on this first metal layer, and is nickel dam or nickel-vanadium alloy layer; The 3rd metal level is to be positioned on this second metal level, and is the copper layer.
10. semiconductor package as claimed in claim 6, is characterized in that, in the indium kirsite of this thermal interface material, the content of zinc is 5wt% to 30wt%.
11. semiconductor package as claimed in claim 6, is characterized in that, the copper layer of this fin is directly to contact this thermal interface material, and this second Jie metallic compound is Cu
11in
9.
12. semiconductor package as claimed in claim 6, is characterized in that, this fin more comprises a nickel dam, and this nickel dam directly contacts this thermal interface material, and this second Jie metallic compound is In
27ni
10.
13. the manufacture method of a semiconductor package comprises the following steps:
(a) form on the gold-plated second surface that belongs to semiconductor crystal grain of a dorsal part;
(b) first surface of this semiconductor grain is electrically connected to a substrate;
(c) provide the material of a removal oxide to this dorsal part plating;
(d) form a thermal interface material on this dorsal part plating, wherein this thermal interface material comprises the indium kirsite;
(e) fin is covered to this semiconductor grain to contact this thermal interface material, wherein this fin at least comprises a bronze medal layer; And
(f) carry out reflow, to generate one first Jie's metallic compound and one second Jie's metallic compound, wherein this first Jie metallic compound, between this dorsal part plating and this thermal interface material, and comprises indium and does not comprise zinc; This second Jie metallic compound, between this thermal interface material and this fin, and comprises indium and does not comprise zinc.
14. the manufacture method as claim 13, is characterized in that, in step (a), this dorsal part plating comprises several layers of metal level, and wherein the top metal level is the copper layer, and, in step (f), this first Jie metallic compound is Cu
11in
9.
15. the manufacture method as claim 14, is characterized in that, in step (a), the copper layer of this dorsal part plating is comprised of a sputter copper and an electro-coppering, and the thickness of this electro-coppering is about 5 μ m.
16. the manufacture method as claim 14, it is characterized in that, in step (a), this dorsal part plating sequentially comprises a first metal layer, one second metal level and one the 3rd metal level, this the first metal layer is to be positioned on the second surface of this semiconductor grain, and is aluminium lamination, titanium layer or chromium layer; This second metal level is to be positioned on this first metal layer, and is nickel dam or nickel-vanadium alloy layer; The 3rd metal level is to be positioned on this second metal level, and is the copper layer.
17. the manufacture method as claim 13, is characterized in that, in step (c), the material of this removal oxide is reducing gas or scaling powder.
18. the manufacture method as claim 13, is characterized in that, in step (d), in the indium kirsite of this thermal interface material, the content of zinc is 5wt% to 30wt%.
19. the manufacture method as claim 13, is characterized in that, in step (e), the copper layer of this fin directly contacts this thermal interface material; And, in step (f), this second Jie metallic compound is Cu
11in
9.
20. the manufacture method as claim 13, is characterized in that, in step (e), this fin more comprises a nickel dam, and this nickel dam directly contacts this thermal interface material; And, in step (f), this second Jie metallic compound is In
27ni
10.
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| CN110648987A (en) * | 2019-10-11 | 2020-01-03 | 宁波施捷电子有限公司 | Interface heat conduction material layer and application thereof |
| CN111602233A (en) * | 2018-02-26 | 2020-08-28 | 新电元工业株式会社 | Method for manufacturing semiconductor device |
| CN112708400A (en) * | 2020-12-17 | 2021-04-27 | 上海先方半导体有限公司 | Thermal interface material and manufacturing method thereof |
| WO2021142766A1 (en) * | 2020-01-17 | 2021-07-22 | Tianjin Laird Technologies Limited | Systems for applying materials to components |
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| CN106356341A (en) * | 2016-08-31 | 2017-01-25 | 华为技术有限公司 | Semiconductor device and manufacture method |
| TWI829986B (en) * | 2020-12-28 | 2024-01-21 | 財團法人工業技術研究院 | Laminate and method for manufacturing laminate |
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| WO2021142766A1 (en) * | 2020-01-17 | 2021-07-22 | Tianjin Laird Technologies Limited | Systems for applying materials to components |
| CN112708400A (en) * | 2020-12-17 | 2021-04-27 | 上海先方半导体有限公司 | Thermal interface material and manufacturing method thereof |
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| CN105932004A (en) | 2016-09-07 |
| TW201501257A (en) | 2015-01-01 |
| TWI529880B (en) | 2016-04-11 |
| CN105932004B (en) | 2019-03-15 |
| CN103441109B (en) | 2016-06-08 |
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