CN103420322B - 晶片封装体及其形成方法 - Google Patents

晶片封装体及其形成方法 Download PDF

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CN103420322B
CN103420322B CN201310192924.1A CN201310192924A CN103420322B CN 103420322 B CN103420322 B CN 103420322B CN 201310192924 A CN201310192924 A CN 201310192924A CN 103420322 B CN103420322 B CN 103420322B
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semiconductor base
semiconductor
layer
wafer encapsulation
semiconductor layer
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CN103420322A (zh
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黄郁庭
张恕铭
何彦仕
刘沧宇
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XinTec Inc
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Abstract

一种晶片封装体及其形成方法，该晶片封装体包括：一第一半导体基底；一第二半导体基底，设置于该第一半导体基底之上，其中该第二半导体基底包括一下半导体层、一上半导体层、及位于该下半导体层与该上半导体层之间的一绝缘层，且部分的该下半导体层电性接触该第一半导体基底上的至少一接垫；一信号导电结构，设置于该第一半导体基底的一下表面之上，该信号导电结构电性连接该第一半导体基底上的一信号接垫；以及一导电层，设置于该第二半导体基底的该上半导体层之上，且电性连接该下半导体层的与该第一半导体基底上的该至少一接垫电性接触的该部分。本发明的晶片封装体的下表面上的导电凸块的分布密度可得到舒缓。

Description

晶片封装体及其形成方法
技术领域
本发明有关于晶片封装体，且特别是有关于微机电***晶片封装体(MEMSchippackages)。
背景技术
随着电子产品朝向轻、薄、短、小发展的趋势，半导体晶片的封装结构也朝向多晶片封装(multi-chippackage,MCP)结构发展，以达到多功能和高性能要求。多晶片封装结构将不同类型的半导体晶片，例如逻辑晶片、模拟晶片、控制晶片、存储器晶片、微机电***晶片，整合在单一封装基底之上。
随着元件密度的提升，晶片封装体底部上的导电凸块的密度亦随之提升。如何在有限空间中设置所需的导电凸块已成为重要课题。
发明内容
本发明一实施例提供一种晶片封装体，包括：一第一半导体基底；一第二半导体基底，设置于该第一半导体基底之上，其中该第二半导体基底包括一下半导体层、一上半导体层、及位于该下半导体层与该上半导体层之间的一绝缘层，且部分的该下半导体层电性接触该第一半导体基底上的至少一接垫；一信号导电结构，设置于该第一半导体基底的一下表面之上，该信号导电结构电性连接该第一半导体基底上的一信号接垫；以及一导电层，设置于该第二半导体基底的该上半导体层之上，且电性连接该下半导体层的与该第一半导体基底上的该至少一接垫电性接触的该部分。
本发明一实施例提供一种晶片封装体的形成方法，包括：提供一第一半导体基底；提供一第二半导体基底，该第二半导体基底包括一下半导体层、一上半导体层、及位于该下半导体层与该上半导体层之间的一绝缘层；将该第二半导体基底接合于该第一半导体基底之上而使部分的该下半导体层电性接触该第一半导体基底上的至少一接垫；于该第二半导体基底的该上半导体层之上形成一导电层，其中该导电层电性连接该下半导体层的与该第一半导体基底上的该至少一接垫电性接触的该部分；以及于该第一半导体基底的一下表面之上形成一信号导电结构，其中该信号导电结构电性连接该第一半导体基底上的一信号接垫。
本发明的晶片封装体的下表面上的导电凸块的分布密度可得到舒缓。
附图说明
图1A-1J显示根据本发明一实施例的晶片封装体的制程剖面图。
图2显示根据本发明一实施例的晶片封装体的剖面图。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。本领域技术人员自本发明的申请专利范围中所能推及的所有实施方式皆属本发明所欲揭露的内容。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装各种晶片及/或多晶片的堆叠。例如，其可用于封装各种包含有源元件或无源元件(activeorpassiveelements)、数字电路或模拟电路(digitaloranalogcircuits)等集成电路的电子元件(electroniccomponents)，例如是有关于光电元件(optoelectronicdevices)、微机电***(MicroElectroMechanicalSystem;MEMS)、微流体***(microfluidicsystems)、或利用热、光线及压力等物理量变化来测量的物理感测器(PhysicalSensor)。特别是可选择使用晶圆级封装(waferscalepackage;WSP)制程对影像感测元件、发光二极管(light-emittingdiodes;LEDs)、太阳能电池(solarcells)、射频元件(RFcircuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(microactuators)、表面声波元件(surfaceacousticwavedevices)、压力感测器(processsensors)喷墨头(inkprinterheads)、或功率晶片(powerIC)等半导体晶片进行封装。
上述晶圆级封装制程主要指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于借堆叠(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layerintegratedcircuitdevices)的晶片封装体。在一实施中，上述切割后的封装体为一晶片尺寸封装体(CSP;chipscalepackage)。晶片尺寸封装体(CSP)的尺寸可仅略大于所封装的晶片。例如，晶片尺寸封装体的尺寸不大于所封装晶片的尺寸的120%。
图1A-1J显示根据本发明一实施例的晶片封装体的制程剖面图。如图1A所示，提供半导体基底10及20。在一实施例中，半导体基底10及20可皆为半导体晶圆，其例如分别为(但不限于)包含微机电***的晶圆及包含互补式金属氧化物半导体场效应晶体管(CMOS)的晶圆。
在一实施例中，半导体基底10包括下半导体层104、上半导体层100、及位于下半导体层104与上半导体层100之间的绝缘层102。上半导体层100可具有表面100a及表面100b，且可以表面100b下的绝缘层102而与下半导体层104电性绝缘。在一实施例中，下半导体层104中可定义有多个间隙，其可将下半导体层104划分为多个彼此分离的部分。
在一实施例中，半导体基底20(例如为半导体晶圆)包括半导体基底200、设置于半导体基底200的表面200a上的接垫204及介电层202。接垫204可包含信号接垫或接地接垫。
在一实施例中，可将半导体基底10接合于半导体基底20之上，使得部分的下半导体层104接合并电性接触至少一接垫204。在一实施例中，部分的下半导体层104所接触的接垫204可为(但不限于)接地接垫。
接着，如图1B所示，可选择性薄化上半导体层100。适合的薄化制程例如包括机械研磨制程、化学机械研磨制程、蚀刻制程、或前述的组合。
接着，可于上半导体层100的表面100a上形成与部分的下半导体层104及接垫204(例如是接地接垫)电性连接的导电层。导电层可通过穿孔及/或经由基底的侧边而与接垫204(例如是接地接垫)电性连接。然而，为简化说明，以下仅以通过穿孔而与接垫204(例如是接地接垫)电性连接的实施方式为例。
如图1C所示，可自上半导体层100的表面100a移除部分的上半导体层100以形成朝下半导体层104延伸的孔洞106。在一实施例中，孔洞106可对齐于接垫204(例如是接地接垫)及与接垫204连接的部分的下半导体层104。在另一实施例中，孔洞106可对齐于接垫204，但所对齐的接垫204不与下半导体层104接触。在又一实施例中，孔洞106不与接垫204对齐。
接着，如图1D所示，可于上半导体层100的表面100a上形成导电层108。在一实施例中，导电层108可延伸进入孔洞106而电性接触所露出的下半导体层104。下半导体层104的由孔洞106所露出的部分可电性连接半导体基底200上的接垫204(其例如为接地接垫)。因此，导电层108可与接垫204电性连接而可作为接地用途。在一实施例中，导电层108可大抵及/或完全覆盖上半导体层100的表面100a及孔洞106的侧壁及底部。在一实施例中，导电层108可直接接触上半导体层100。在一实施例中，孔洞106可位于预定切割道(未显示)之中。
此外，导电层108除了可用作接地外，在其他实施例中，导电层108可作为电磁干扰防护(EMIshielding)层、导热层、或反射层。
如图1E所示，可选择性于上半导体层100上设置承载基底110。例如，可采用粘着层112而将承载基底110接合于上半导体层100之上。
接着，如图1F所示，可选择性薄化半导体基底200。例如，可以承载基底110为支撑，自半导体基底200的表面200b薄化半导体基底200。
如图1G所示，可接着自表面200b移除部分的半导体基底200以形成朝接垫204(其例如是信号接垫)延伸的孔洞206。
接着，如图1H所示，可于半导体基底200的表面200b上形成绝缘层208。绝缘层208可延伸于孔洞206的侧壁与底部上。在一实施例中，可进一步通过图案化制程移除孔洞206底部上的部分的绝缘层208而使接垫204(例如，信号接垫)露出。
如图1I所示，可接着于绝缘层208上形成电信连接接垫204(例如，信号接垫)的导电层。例如，可先形成晶种层210a，并接着通过电镀制程形成导电层210b。
接着，如图1J所示，可于导电层210b及绝缘层208上形成保护层212，其具有露出部分的导电层210b的至少一开口。接着，可于开口中形成信号导电结构214，其例如为导电凸块或焊球。在所接合的两半导体基底为半导体晶圆的实施例中，可接着沿着预定切割道(未显示)进行切割制程以将两半导体基底切割为多个彼此分离的晶片封装体。
图2显示根据本发明一实施例的晶片封装体的剖面图，其中相同或相似的标号用以标示相同或相似的元件。图2的实施例大抵相同于图1A-1J所示的实施例。主要区别在于所使用的粘着层112可为易于移除的粘着胶。因此，可例如通过照光、加热、及/或使用溶剂的方式移除粘着层112及承载基底110而进一步缩减晶片封装体的尺寸。
在本发明实施例中，晶片封装体的信号导电结构214可设于晶片封装体的下表面，而(接地)接垫204可通过下半导体层104而与设置在晶片封装体的上侧的导电层108电性连接。因此，晶片封装体的下表面上的导电凸块的分布密度可获舒缓。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
附图中的符号简单说明如下：
10、20：半导体基底
100：上半导体层
100a、100b：表面
102：绝缘层
104：下半导体层
106：孔洞
108：导电层
110：承载基底
112：粘着层
200：半导体基底
200a、200b：表面
202：介电层
204：接垫
206：孔洞
208：绝缘层
210a：晶种层
210b：导电层
212：保护层
214：导电结构。

Claims (20)

1.一种晶片封装体，其特征在于，包括：
一第一半导体基底；
一第二半导体基底，设置于该第一半导体基底之上，其中该第二半导体基底包括一下半导体层、一上半导体层、及位于该下半导体层与该上半导体层之间的一绝缘层，且部分的该下半导体层电性接触该第一半导体基底上的至少一接垫；
一信号导电结构，设置于该第一半导体基底的一下表面之上，该信号导电结构电性连接该第一半导体基底上的一信号接垫；以及
一导电层，设置于该第二半导体基底的该上半导体层之上，且电性连接该下半导体层的与该第一半导体基底上的该至少一接垫电性接触的该部分。
2.根据权利要求1所述的晶片封装体，其特征在于，该导电层大抵完全覆盖该第二半导体基底的该上半导体层的一上表面。
3.根据权利要求1所述的晶片封装体，其特征在于，还包括一孔洞，自该第二半导体基底的该上半导体层的一上表面朝该第二半导体基底的该下半导体层延伸，其中该导电层延伸进入该孔洞而电性接触部分的该下半导体层。
4.根据权利要求3所述的晶片封装体，其特征在于，该孔洞对齐于其中一该至少一接垫。
5.根据权利要求1所述的晶片封装体，其特征在于，还包括一第二导电层，电性连接该信号导电结构及该信号接垫。
6.根据权利要求5所述的晶片封装体，其特征在于，还包括一第二孔洞，自该第一半导体基底的一下表面朝该信号接垫延伸，其中该第二导电层延伸进入该第二孔洞而电性接触该信号接垫，且该第二导电层与该第一半导体基底之间隔有一第二绝缘层。
7.根据权利要求1所述的晶片封装体，其特征在于，该导电层直接接触该第二半导体基底。
8.根据权利要求1所述的晶片封装体，其特征在于，还包括一承载基底，设置于该第二半导体基底之上。
9.根据权利要求8所述的晶片封装体，其特征在于，还包括一粘着层，设置于该承载基底与该第二半导体基底之上。
10.根据权利要求1所述的晶片封装体，其特征在于，该第一半导体基底包括一互补式金属氧化物半导体场效应晶体管晶片，而该第二半导体基底包括一微机电***晶片。
11.一种晶片封装体的形成方法，其特征在于，包括：
提供一第一半导体基底；
提供一第二半导体基底，该第二半导体基底包括一下半导体层、一上半导体层、及位于该下半导体层与该上半导体层之间的一绝缘层；
将该第二半导体基底接合于该第一半导体基底之上而使部分的该下半导体层电性接触该第一半导体基底上的至少一接垫；
于该第二半导体基底的该上半导体层之上形成一导电层，其中该导电层电性连接该下半导体层的与该第一半导体基底上的该至少一接垫电性接触的该部分；以及
于该第一半导体基底的一下表面之上形成一信号导电结构，其中该信号导电结构电性连接该第一半导体基底上的一信号接垫。
12.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括于形成该导电层之前，薄化该上半导体层。
13.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括于形成该导电层之前，移除部分的该上半导体层以形成朝该下半导体层延伸的一孔洞，接着形成该导电层而使该导电层延伸进入该孔洞而电性接触部分的该下半导体层。
14.根据权利要求13所述的晶片封装体的形成方法，其特征在于，该导电层大抵完全覆盖该上半导体层的一上表面及该孔洞的一侧壁及一底部。
15.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括在形成该信号导电结构之前，薄化该第一半导体基底。
16.根据权利要求15所述的晶片封装体的形成方法，其特征在于，还包括：
于该第二半导体基底之上接合一承载基底；以及
以该承载基底为支撑，自该第一半导体基底的该下表面薄化该第一半导体基底。
17.根据权利要求16所述的晶片封装体的形成方法，其特征在于，还包括：
自该第一半导体基底的该下表面移除部分的该第一半导体基底以形成露出该信号接垫的一第二孔洞；
于该第一半导体基底的该下表面上及该第二孔洞的一侧壁上形成一第二绝缘层；
于该第一半导体基底的该下表面上形成一第二导电层，该第二导电层延伸进入该第二孔洞而电性连接该信号接垫；以及
于该第一半导体基底的该下表面上的该第二导电层上形成该信号导电结构。
18.根据权利要求17所述的晶片封装体的形成方法，其特征在于，还包括于该第一半导体基底的该下表面上形成一保护层，其中该保护层具有露出该信号导电结构的至少一开口。
19.根据权利要求18所述的晶片封装体的形成方法，其特征在于，还包括移除该承载基底。
20.根据权利要求11所述的晶片封装体的形成方法，其特征在于，还包括对该第一半导体基底及该第二半导体基底进行一切割制程以形成彼此分离的多个晶片封装体。
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