CN103413811B - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

Info

Publication number
CN103413811B
CN103413811B CN201310310000.7A CN201310310000A CN103413811B CN 103413811 B CN103413811 B CN 103413811B CN 201310310000 A CN201310310000 A CN 201310310000A CN 103413811 B CN103413811 B CN 103413811B
Authority
CN
China
Prior art keywords
active layer
transition zone
drain electrode
region
array base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310310000.7A
Other languages
English (en)
Other versions
CN103413811A (zh
Inventor
李田生
郭建
谢振宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing BOE Optoelectronics Technology Co Ltd filed Critical Beijing BOE Optoelectronics Technology Co Ltd
Priority to CN201310310000.7A priority Critical patent/CN103413811B/zh
Priority to US14/405,008 priority patent/US10204936B2/en
Priority to PCT/CN2013/087524 priority patent/WO2015010397A1/zh
Publication of CN103413811A publication Critical patent/CN103413811A/zh
Application granted granted Critical
Publication of CN103413811B publication Critical patent/CN103413811B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明实施例公开了一种阵列基板及其制造方法,以及设有该阵列基板的显示装置,属于显示技术领域。解决了现有技术中GOA区域的边缘会形成向下开口的倒角,影响GOA区域中源漏极金属与栅极金属之间电连接的稳定性的技术问题。该阵列基板,包括显示区域和GOA区域,在所述GOA区域,从下至上依次形成有栅极金属、栅绝缘层、有源层、过渡层、源漏极金属,且开设有贯穿所述过渡层、所述有源层和所述栅绝缘层的过孔,所述源漏极金属通过所述过孔与所述栅极金属电连接;其中,所述过渡层的刻蚀速率大于所述有源层的刻蚀速率。本发明应用于OLED面板、液晶电视、液晶显示器、手机、平板电脑等显示装置。

Description

阵列基板及其制造方法、显示装置
技术领域
本发明属于显示技术领域,具体涉及一种阵列基板及其制造方法,以及设有该阵列基板的显示装置。
背景技术
随着显示技术的不断发展,薄膜晶体管液晶显示器(ThinFilmTransistorLiquidCrystalDisplay,简称TFT-LCD)已在平板显示领域中占据了主导地位。现在的TFT-LCD中越来越多的采用阵列基板行驱动(GatedriverOnArray,GOA)技术,即在阵列基板的板边划分GOA区域,在GOA区域中将栅极金属与源漏极金属通过贯穿栅绝缘层和有源层的过孔电连接,作为栅极驱动电路的一部分,以实现更高的像素密集度(PixelPerInch,PPI)。同时,为了节省阵列基板制造过程中掩膜版的使用次数,通常利用一次掩膜版工艺在GOA区域形成贯穿栅绝缘层和有源层的过孔。例如,在高级超维场转换(AdvancedsuperDimensionSwitch,ADS)型阵列基板的制造过程中,利用一次掩膜版工艺在GOA区域刻蚀有源层和栅绝缘层,形成过孔,就可以只通过六次掩膜版工艺形成阵列基板。
本发明人在实现本发明的过程中发现,现有技术至少存在以下问题:如图1所示,图中衬底基板1的左半部分为GOA区域,在GOA区域的衬底基板1上形成有栅极金属21、栅绝缘层3和有源层4,其中有源层4实际是由两层组成,即上层的金属重掺杂层和下层的非晶硅层。在过孔刻30蚀过程中,金属重掺杂层的刻蚀速率比非晶硅层的刻蚀速率慢很多,所以当栅绝缘层3和有源层4完全刻蚀掉,形成过孔时,有源层4的边缘会形成向下开口的倒角,这将导致后续沉积的源漏极金属下方存在空隙,影响GOA区域中源漏极金属与栅极金属之间电连接的稳定性。
发明内容
本发明实施例提供了一种阵列基板及其制造方法,以及设有该阵列基板的显示装置,解决了现有技术中GOA区域的边缘会形成向下开口的倒角,影响GOA区域中源漏极金属与栅极金属之间电连接的稳定性的技术问题。
为达到上述目的,本发明的实施例采用如下技术方案:
本发明提供一种阵列基板,包括显示区域和GOA区域,在所述GOA区域,从下至上依次形成有栅极金属、栅绝缘层、有源层、过渡层、源漏极金属,且开设有贯穿所述过渡层、所述有源层和所述栅绝缘层的过孔,所述源漏极金属通过所述过孔与所述栅极金属电连接;
其中,所述过渡层的刻蚀速率大于所述有源层的刻蚀速率。
优选的,所述过渡层的材料为氮化硅。
进一步,所述显示区域中的薄膜晶体管(TFT)区域,从下至上依次包括栅极、栅绝缘层、有源层、源极和漏极;
所述源极和所述漏极分别位于所述有源层的两侧,并与所述有源层连接。
本发明还提供一种阵列基板的制造方法,包括:
在衬底基板上形成GOA区域的栅极金属和显示区域的栅线和栅极;
在所述衬底基板上依次沉积栅绝缘层、有源层、过渡层,所述过渡层的刻蚀速率大于所述有源层的刻蚀速率;
刻蚀掉所述GOA区域的过渡层、有源层、栅绝缘层,以及所述显示区域中的TFT区域的过渡层和部分有源层,使所述GOA区域形成过孔;
在所述GOA区域形成源漏极金属,同时在所述显示区域形成数据线、源极和漏极,其中,所述源漏极金属通过所述过孔与所述栅极金属电连接。
优选的,所述刻蚀掉所述GOA区域的过渡层、有源层、栅绝缘层,以及所述显示区域中的TFT区域的过渡层和部分有源层,在所述GOA区域形成过孔,具体为:
在所述衬底基板上涂覆一层光刻胶,并通过灰色调掩膜工艺和灰化工艺,使所述光刻胶形成完全去除区域、部分保留区域和完全保留区域,其中,所述完全去除区域对应所述栅极金属所在的区域,所述部分保留区域对应所述显示区域中的TFT区域,所述完全保留区域对应其余的区域;
刻蚀掉所述完全去除区域的过渡层、有源层、栅绝缘层,在所述GOA区域形成过孔;
通过灰化工艺,去除所述部分保留区域的光刻胶;
刻蚀掉所述部分保留区域的过渡层和部分有源层;
通过灰化工艺,去除所述完全保留区域的光刻胶。
进一步,在所述GOA区域形成源漏极金属,同时在所述显示区域形成数据线、源极和漏极之后,还包括:
在衬底基板上形成像素电极;
在所述衬底基板上形成保护层。
进一步,在所述衬底基板上形成保护层之后还包括:
在所述衬底基板上形成公共电极。
本发明还提供一种显示装置,包括上述的阵列基板。
与现有技术相比,本发明所提供的上述技术方案具有如下优点:在有源层上增设过渡层,在GOA区域刻蚀过孔时,需要刻蚀过渡层、有源层和栅绝缘层,因为过渡层的刻蚀速率大于有源层的刻蚀速率,所以过孔刻蚀完毕之后,相比于有源层,会有较多的过渡层被刻蚀掉,从而在过渡层和有源层的边缘形成向上开口的正角,提高了GOA区域中源漏极金属与栅极金属之间电连接的稳定性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。
图1为现有的阵列基板的示意图;
图2为本发明的实施例所提供的阵列基板的示意图;
图3a至图3j为本发明的实施例所提供的阵列基板的制造方法的制造过程示意图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整的描述。
如图2所示,本发明实施例所提供的阵列基板,包括显示区域和GOA区域。在GOA区域,从下至上依次包括形成于衬底基板1上的栅极金属21、栅绝缘层3、有源层4、过渡层5、源漏极金属61,且开设有贯穿过渡层、有源层和栅绝缘层的过孔30,源漏极金属61通过过孔30与栅极金属21电连接。其中,过渡层5的刻蚀速率大于有源层4的刻蚀速率,过渡层5的材料优选为氮化硅(SiNx)。
在有源层4上增设过渡层5,在GOA区域刻蚀过孔30时,需要刻蚀过渡层5、有源层4和栅绝缘层3,因为过渡层5的刻蚀速率大于有源层4的刻蚀速率,所以过孔30刻蚀完毕之后,相比于有源层4,会有较多的过渡层5被刻蚀掉,从而在过渡层5和有源层4的边缘形成向上开口的正角,提高了GOA区域中源漏极金属61与栅极金属21之间电连接的稳定性。
在该阵列基板的显示区域中的TFT区域,从下至上依次包括形成于衬底基板1上的栅极22、栅绝缘层3、有源层4、源极62和漏极63,源极62和漏极63分别位于有源层4的两侧,并与有源层4连接。此外,在显示区域中还包括像素电极7,在GOA区域和显示区域上方还包括保护层8。
本发明实施例提供的阵列基板为ADS型阵列基板,因此在显示区域还包括公共电极9。当然,在其他实施方式中,该阵列基板也可以是ADS以外的其他类型的阵列基板。
本发明还提供了上述阵列基板的制造方法,包括:
S1:如图3a所示,在衬底基板1上形成GOA区域的栅极金属21和显示区域的栅线(图中未示出)和栅极22。
利用常规方法,在衬底基板上沉积栅极金属层,再利用掩膜版工艺,经显影、刻蚀即可形成GOA区域的栅极金属21和显示区域的栅线和栅极22。
S2:如图3b所示,在衬底基板1上依次沉积栅绝缘层3、有源层4、过渡层5。其中,过渡层5的刻蚀速率大于有源层4的刻蚀速率,过渡层5的材料优选为SiNx
S3:刻蚀掉GOA区域的过渡层、有源层、栅绝缘层,以及显示区域中的TFT区域的过渡层和部分有源层,使GOA区域形成过孔。
具体可包括:
S31:如图3c所示,在衬底基板1上涂覆一层光刻胶10,并通过灰色调掩膜工艺和灰化工艺,使光刻胶10形成完全去除区域、部分保留区域和完全保留区域,其中,完全去除区域对应栅极金属21所在的区域,部分保留区域对应显示区域中的TFT区域,完全保留区域对应其余的区域。
S32:如图3d所示,刻蚀掉完全去除区域的过渡层5、有源层4、栅绝缘层3,在GOA区域形成过孔30。
因为过渡层5的刻蚀速率大于有源层4的刻蚀速率,所以过孔30刻蚀完毕之后,相比于有源层4,会有较多的过渡层5被刻蚀掉,从而在过渡层5和有源层4的边缘形成向上开口的正角。
S33:如图3e所示,通过灰化工艺,去除部分保留区域的光刻胶10。
S34:如图3f所示,刻蚀掉部分保留区域的过渡层5和部分有源层4,形成TFT中的有源层。
S35:如图3g所示,通过灰化工艺,去除完全保留区域的光刻胶10。
S4:如图3h所示,在GOA区域形成源漏极金属61,同时在显示区域形成数据线(图中未示出)、源极62和漏极63,其中,源漏极金属61通过过孔30与栅极金属21电连接。
利用常规方法,在衬底基板1上沉积源漏极金属层,再利用掩膜版工艺,经显影、刻蚀即可形成GOA区域的源漏极金属61和显示区域的数据线、源极62和漏极63。此外,在形成源漏极金属61、数据线、源极62和漏极63之后,还继续刻蚀掉其余暴露在外的过渡层5和有源层4。
由于之前已在GOA区域形成了过孔30,所以源漏极金属61就能够通过过孔30与栅极金属21形成电连接。
该阵列基板的制造方法进一步还包括:
S5:如图3i所示,在衬底基板1上形成像素电极7。
S6:如图3j所示,在衬底基板1上形成保护层8。
本发明实施例所提供的阵列基板为ADS型阵列基板,因此该阵列基板的制造方法还包括:
S7:在衬底基板1上形成公共电极9,即可形成本发明实施例所提供的阵列基板,如图2所示。
上述步骤S5至S7均可通过常规方法实现,不再进行详细说明。
本发明实施例提供的阵列基板的制造方法中,通过在有源层上增设过渡层,并且过渡层的刻蚀速率大于有源层的刻蚀速率,从而在过孔刻蚀完毕之后,在过渡层和有源层的边缘形成向上开口的正角,提高了GOA区域中源漏极金属与栅极金属之间电连接的稳定性。
本发明还提供一种显示装置,可以是液晶面板、电子纸、OLED面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。该显示装置中包括上述本发明实施例所提供的阵列基板。
由于本发明实施例所提供的显示装置与上述本发明实施例所提供的阵列基板具有相同的技术特征,所以也能产生相同的技术效果,解决相同的技术问题。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以权利要求的保护范围为准。

Claims (8)

1.一种阵列基板,包括显示区域和GOA区域,其特征在于:在所述GOA区域,从下至上依次形成有栅极金属、栅绝缘层、有源层、过渡层、源漏极金属,且开设有贯穿所述过渡层、所述有源层和所述栅绝缘层的过孔,所述源漏极金属通过所述过孔与所述栅极金属电连接;
其中,所述过渡层的刻蚀速率大于所述有源层的刻蚀速率,所述过孔在所述过渡层和所述有源层的边缘具有向上开口的正角。
2.根据权利要求1所述的阵列基板,其特征在于:所述过渡层的材料为氮化硅。
3.根据权利要求1或2所述的阵列基板,其特征在于:所述显示区域中的薄膜晶体管区域,从下至上依次包括栅极、栅绝缘层、有源层、源极和漏极;
所述源极和所述漏极分别位于所述有源层的两侧,并与所述有源层连接。
4.一种阵列基板的制造方法,其特征在于,包括:
在衬底基板上形成GOA区域的栅极金属和显示区域的栅线和栅极;
在所述衬底基板上依次沉积栅绝缘层、有源层、过渡层,所述过渡层的刻蚀速率大于所述有源层的刻蚀速率;
刻蚀掉所述GOA区域的过渡层、有源层、栅绝缘层,以及所述显示区域中的薄膜晶体管区域的过渡层和部分有源层,使所述GOA区域形成过孔;
在所述GOA区域形成源漏极金属,同时在所述显示区域形成数据线、源极和漏极,其中,所述源漏极金属通过所述过孔与所述栅极金属电连接。
5.根据权利要求4所述的制造方法,其特征在于:所述刻蚀掉所述GOA区域的过渡层、有源层、栅绝缘层,以及所述显示区域中的薄膜晶体管区域的过渡层和部分有源层,在所述GOA区域形成过孔,具体为:
在所述衬底基板上涂覆一层光刻胶,并通过灰色调掩膜工艺和灰化工艺,使所述光刻胶形成完全去除区域、部分保留区域和完全保留区域,其中,所述完全去除区域对应所述栅极金属所在的区域,所述部分保留区域对应所述显示区域中的薄膜晶体管区域,所述完全保留区域对应其余的区域;
刻蚀掉所述完全去除区域的过渡层、有源层、栅绝缘层,在所述GOA区域形成过孔;
通过灰化工艺,去除所述部分保留区域的光刻胶;
刻蚀掉所述部分保留区域的过渡层和部分有源层;
通过灰化工艺,去除所述完全保留区域的光刻胶。
6.根据权利要求4所述的制造方法,其特征在于:在所述GOA区域形成源漏极金属,同时在所述显示区域形成数据线、源极和漏极之后,还包括:
在衬底基板上形成像素电极;
在所述衬底基板上形成保护层。
7.根据权利要求6所述的制造方法,其特征在于:在所述衬底基板上形成保护层之后还包括:
在所述衬底基板上形成公共电极。
8.一种显示装置,其特征在于:包括权利要求1至3任一项所述的阵列基板。
CN201310310000.7A 2013-07-23 2013-07-23 阵列基板及其制造方法、显示装置 Active CN103413811B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201310310000.7A CN103413811B (zh) 2013-07-23 2013-07-23 阵列基板及其制造方法、显示装置
US14/405,008 US10204936B2 (en) 2013-07-23 2013-11-20 Array substrate and method for manufacturing the same, display device
PCT/CN2013/087524 WO2015010397A1 (zh) 2013-07-23 2013-11-20 阵列基板及其制造方法、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310310000.7A CN103413811B (zh) 2013-07-23 2013-07-23 阵列基板及其制造方法、显示装置

Publications (2)

Publication Number Publication Date
CN103413811A CN103413811A (zh) 2013-11-27
CN103413811B true CN103413811B (zh) 2016-04-13

Family

ID=49606809

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310310000.7A Active CN103413811B (zh) 2013-07-23 2013-07-23 阵列基板及其制造方法、显示装置

Country Status (3)

Country Link
US (1) US10204936B2 (zh)
CN (1) CN103413811B (zh)
WO (1) WO2015010397A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103730473B (zh) * 2013-12-25 2016-02-10 北京京东方光电科技有限公司 阵列基板及其制造方法、显示装置
CN104576659A (zh) * 2015-02-09 2015-04-29 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN105093751B (zh) * 2015-08-18 2018-09-11 京东方科技集团股份有限公司 预防esd的goa布局设计
CN105280648B (zh) * 2015-09-16 2018-06-15 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板和显示装置
CN105206567B (zh) * 2015-10-10 2018-04-10 深圳市华星光电技术有限公司 一种阵列基板及其制作方法
CN106449667B (zh) * 2016-12-21 2017-12-22 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN107170757B (zh) * 2017-05-25 2019-09-24 深圳市华星光电技术有限公司 一种阵列基板及其制作方法
CN110137154B (zh) * 2019-04-04 2021-01-08 惠科股份有限公司 一种测试结构、基板及其制造方法
CN210110300U (zh) * 2019-08-16 2020-02-21 北京京东方技术开发有限公司 像素驱动电路、阵列基板和显示装置
CN111952250B (zh) * 2020-08-10 2023-08-29 昆山龙腾光电股份有限公司 阵列基板的制作方法及阵列基板

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101030560A (zh) * 2007-03-28 2007-09-05 友达光电股份有限公司 薄膜晶体管基板的制造方法
CN101656232A (zh) * 2008-08-19 2010-02-24 北京京东方光电科技有限公司 薄膜晶体管阵列基板制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4960719A (en) * 1988-02-04 1990-10-02 Seikosha Co., Ltd. Method for producing amorphous silicon thin film transistor array substrate
JPH0783018B2 (ja) * 1993-03-17 1995-09-06 日本電気株式会社 エッチング方法
US6528357B2 (en) * 1998-03-13 2003-03-04 Kabushiki Kaisha Toshiba Method of manufacturing array substrate
US6448579B1 (en) * 2000-12-06 2002-09-10 L.G.Philips Lcd Co., Ltd. Thin film transistor array substrate for liquid crystal display and a method for fabricating the same
KR101353269B1 (ko) * 2006-12-11 2014-01-20 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 이의 제조 방법
JP4925314B2 (ja) * 2007-05-30 2012-04-25 カシオ計算機株式会社 窒化シリコン膜のドライエッチング方法および薄膜トランジスタの製造方法
US20110122054A1 (en) * 2008-08-11 2011-05-26 Sharp Kabushiki Kaisha Liquid crystal display device
KR101159399B1 (ko) * 2009-02-18 2012-06-28 엘지디스플레이 주식회사 박막트랜지스터 어레이기판 및 그의 제조방법
RU2503085C1 (ru) * 2009-12-09 2013-12-27 Шарп Кабусики Кайся Полупроводниковое устройство и способ его изготовления
KR101108176B1 (ko) * 2010-07-07 2012-01-31 삼성모바일디스플레이주식회사 더블 게이트형 박막 트랜지스터 및 이를 구비한 유기 발광 표시 장치
CN203367271U (zh) * 2013-07-23 2013-12-25 北京京东方光电科技有限公司 阵列基板及显示装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101030560A (zh) * 2007-03-28 2007-09-05 友达光电股份有限公司 薄膜晶体管基板的制造方法
CN101656232A (zh) * 2008-08-19 2010-02-24 北京京东方光电科技有限公司 薄膜晶体管阵列基板制造方法

Also Published As

Publication number Publication date
WO2015010397A1 (zh) 2015-01-29
US10204936B2 (en) 2019-02-12
CN103413811A (zh) 2013-11-27
US20150318313A1 (en) 2015-11-05

Similar Documents

Publication Publication Date Title
CN103413811B (zh) 阵列基板及其制造方法、显示装置
CN104538352A (zh) 阵列基板及其制造方法、显示装置
CN103489922A (zh) 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置
CN104614910A (zh) 阵列基板及其制作方法、显示装置
CN104393000A (zh) 一种阵列基板及其制作方法、显示装置
CN102655156A (zh) 一种阵列基板及其制造方法
CN102646634A (zh) Tft-lcd阵列基板制造方法
CN102929060B (zh) 阵列基板及其制作方法、显示装置
CN103383945A (zh) 一种阵列基板、显示装置及阵列基板的制造方法
CN103354206A (zh) 过孔制作方法、显示面板制作方法及显示面板
CN102709241A (zh) 一种薄膜晶体管阵列基板及制作方法和显示装置
CN103474437A (zh) 一种阵列基板及其制备方法与显示装置
CN103928400A (zh) 阵列基板及其制作方法、显示装置
CN100456089C (zh) 一种液晶显示器阵列基板的像素结构及其制造方法
CN104409514A (zh) 一种薄膜晶体管结构、其制作方法及相关装置
CN103730511B (zh) 薄膜晶体管及其制造方法、阵列基板、显示装置
CN104409462A (zh) 阵列基板及其制造方法、显示装置
CN103424925B (zh) 一种阵列基板及其制造方法、显示装置
CN101236932A (zh) 薄膜晶体管阵列基板的制造方法
CN104538413A (zh) 阵列基板及其制作方法、显示装置
CN104409510A (zh) 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
CN104393002A (zh) 一种显示基板及其制作方法、显示装置
CN103730473B (zh) 阵列基板及其制造方法、显示装置
CN104409483A (zh) 阵列基板及其制造方法、显示装置
CN103413813A (zh) 一种阵列基板及其制作方法、显示装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant