CN103391495A - Automatic earphone adaptation circuit and adaptation method thereof - Google Patents
Automatic earphone adaptation circuit and adaptation method thereof Download PDFInfo
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- CN103391495A CN103391495A CN2013102730466A CN201310273046A CN103391495A CN 103391495 A CN103391495 A CN 103391495A CN 2013102730466 A CN2013102730466 A CN 2013102730466A CN 201310273046 A CN201310273046 A CN 201310273046A CN 103391495 A CN103391495 A CN 103391495A
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Abstract
The invention discloses an automatic earphone adaptation circuit and an adaptation method thereof. The automatic earphone adaptation circuit comprises a baseband chip and an earphone socket connector circuit and is characterized by further comprising an MIC processing circuit in circuit connection with the baseband chip and a switch switching circuit connected between the earphone socket connector circuit and the MIC processing circuit for switching the connection state of the earphone socket connector circuit and the MIC processing circuit according to instructions of the baseband chip. By means of the automatic earphone adaptation circuit and the adaptation method, variety of earphones can be automatically detected, the circuit can be automatically adjusted to the state matched with earphone sockets, a mobile terminal which the circuit is installed on can be matched with the earphone sockets with different standards in the market, and users can randomly chooses the earphones they like.
Description
Technical field
The present invention relates to electronic communication field, relate in particular to circuit and the adaptation method of the electronic equipments such as computer with the earphone adaptable interface, mobile terminal, panel computer, player.
Background technology
General headset plug on market, as shown in Figure 1, comprise four terminals,, according to the order of the end by described plug to root, is followed successively by the first terminal 111, the second terminal 112, the 3rd terminal 113 and the 4th terminal 114.General headset plug on market, its terminal is defined according to following two kinds of earphone interface standards:
The first earphone interface standard: the first terminal 111 receives terminal for left channel audio signal; The second terminal 112 receives terminal for right channel audio signal; The 3rd terminal 113 is transmitter for audio signal output end, MIC+; The 4th terminal 114 is earth terminal.
The second earphone interface standard: the first terminal 111 receives terminal for left channel audio signal; The second terminal 112 receives terminal for right channel audio signal; The 3rd terminal 113 is earth terminal; The 4th terminal 114 is transmitter for audio signal output end, MIC+.
Earphone socket of the prior art, as shown in Figure 1, be provided with five decks corresponding with headset plug, is respectively the first deck 121, the second deck 122, the 3rd deck 123, the 4th deck 124 and the 5th deck 125; When headset plug was inserted in earphone socket, the first terminal 111 was stuck in described the first deck 121 and with its circuit and is connected; The second terminal 112 is stuck in described the second deck 122 and with its circuit and is connected; The 3rd terminal 113 is stuck in described the 3rd deck 123 and with its circuit and is connected; The 4th terminal 114 is stuck in described the 4th deck 124 and realizes that the circuit of the 4th terminal 114, the first deck 121 and the 4th deck 124 connects.
A kind of electronic equipment of the prior art, the 3rd deck 123 of its earphone socket is connected with the audio signal input end mouth of baseband chip, its 4th deck 124 ground connection, this electronic equipment only can be complementary with the headset plug that meets the first earphone interface standard; Another kind of electronic equipment of the prior art, the 3rd deck 123 ground connection of its earphone socket, its the 4th deck 124 is connected with the audio signal input end mouth of baseband chip, and this electronic equipment only can be complementary with the headset plug that meets the second earphone interface standard.
Therefore in prior art, electronic equipment only is complementary with a kind of headset plug, the headset plug of another kind of earphone interface standard can't use with this electronic equipment coupling, the limitation that this has just caused earphone to use, the consumer need to upgrade corresponding earphone when replacing new terminal equipment, cause the wasting of resources.
Summary of the invention
The purpose of this invention is to provide a kind of earphone automatic adaptation circuit and adaptation method thereof.
Earphone automatic adaptation circuit provided by the present invention, comprise baseband chip and earphone socket interface circuit; And the MIC treatment circuit that is connected with described baseband chip circuitry phase and be connected to described earphone socket interface circuit and described MIC treatment circuit between be used for switch switching circuit according to the connection status of the instruction described earphone socket interface circuit of switching of baseband chip and described MIC treatment circuit.
The method of automatic adaptation headset plug provided by the present invention, comprise the steps:
The described earphone socket interface circuit of S1 is set up circuit with headset plug and is connected, and to described baseband chip, sends interrupt signal;
The described baseband chip of S2 enters the magnitude of voltage that interrupts and detect its identification signal input port;
S3 controls the conducting state of described switch switching circuit according to described magnitude of voltage.
Institute of the present invention earphone automatic adaptation circuit and adaptation method thereof, can automatically detect the kind of access earphone and the state that automatically the regulation of electrical circuit is complementary as for this headset plug, can make the earphone socket of the various criterion on the compatible adaptive market of the mobile terminal that is provided with this circuit, the earphone that the user can arrange in pairs or groups arbitrarily and oneself like.
Description of drawings
Fig. 1 is the structural representation of the headset plug described in background technology and earphone socket;
The earphone automatic adaptation circuit module schematic diagram that Fig. 2 provides for the embodiment of the present invention one;
Fig. 3 is the port schematic diagram of the described baseband chip of Fig. 2;
Fig. 4 is the electrical block diagram of the described MIC treatment circuit of Fig. 2;
Fig. 5 is the electrical block diagram of the described switch switching circuit of Fig. 2;
Fig. 6 is the electrical block diagram of the described earphone socket interface circuit of Fig. 2;
Fig. 7 is the schematic flow sheet of the method for the described automatic adaptation headset plug of embodiment two.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making under the creative work prerequisite the every other embodiment that obtains, belong to the scope of protection of the invention.
as shown in Figure 2, the present embodiment provides a kind of earphone automatic adaptation circuit, comprise the baseband chip 2100 that is provided with the audio signal input end mouth and the earphone socket interface circuit 2400 that is provided with the 3rd deck 2403 and the 4th deck 2404, it is characterized in that: also comprise the MIC treatment circuit 2200 that is connected with described baseband chip 2100 circuitry phases and be connected to described earphone socket interface circuit 2400 and described MIC treatment circuit 2200 between be used for according to the described earphone socket interface circuit 2400 of instruction switching of baseband chip 2100 and the switch switching circuit 2300 of the connection status of described MIC treatment circuit 2200.It will be understood by those skilled in the art that when headset plug is inserted in earphone socket, the 3rd terminal 113 of headset plug is stuck in described the 3rd deck 2403 and with its circuit and is connected; The 4th terminal 114 of headset plug is stuck in described the 4th deck 2404 and with its circuit and is connected.Described earphone socket interface circuit 2400 comprises that with the connection status of described MIC treatment circuit 2200 the 3rd deck 2403 is connected with described MIC treatment circuit 2200 and the first state of the 4th deck 2404 ground connection; And the 3rd the second state of being connected with described MIC treatment circuit 2200 of deck 2403 ground connection and the 4th deck 2404.Described switch switching circuit 2300 is switched between described the first state and the second state according to the described earphone automatic adaptation of the instruction control the present embodiment circuit of baseband chip 2100, can be complementary with the earphone socket of the first earphone interface standard described in background technology when the described earphone automatic adaptation of the present embodiment circuit switches to the first state; When switching to the second state, the described earphone automatic adaptation of the present embodiment circuit can be complementary with the earphone socket of the second earphone interface standard described in background technology.Like this, can be the automatically compatible adaptive above-mentioned two kinds of earphone sockets of electronic equipment of the described earphone automatic adaptation of the present embodiment circuit have been configured, the earphone that the user can arrange in pairs or groups arbitrarily and oneself like.
As shown in Figure 5, described switch switching circuit 2300 comprises the first simulation single-pole double-throw switch (SPDT) U1 and the second simulation single-pole double-throw switch (SPDT) U2; Described the first simulation single-pole double-throw switch (SPDT) U1 is equipped with the first high level triggering and conducting port B11, the first low level triggering and conducting port B01, the second deck connectivity port A2 and the first control port S1; Described the second simulation single-pole double-throw switch (SPDT) U2 is equipped with the second high level triggering and conducting port B12, the second low level triggering and conducting port B02, the second deck connectivity port A2 and the second control port S2; Described the first high level triggering and conducting port B11 all is connected with described MIC treatment circuit 2200 with described the second low level triggering and conducting port B02; Described the second deck connectivity port A2 connects the 4th deck 2404; Described the second deck connectivity port A2 connects the 3rd deck 2403; Described the first control port S1 and described the second control port S2 all are connected with described baseband chip 2100; Described the first low level triggering and conducting port B01 and the second equal ground connection of high level triggering and conducting port B12.It will be appreciated by those skilled in the art that, described the first simulation single-pole double-throw switch (SPDT) U1 receives by described the first control port (S1) control signal that described baseband chip 2100 is sent, and according to described the second deck connectivity port A2 and described the first high level triggering and conducting port B11 is conducted or and described the first low level triggering and conducting port B01 switch between one of being conducted both; Described the second simulation single-pole double-throw switch (SPDT) U2 receives by described the second control port (S2) control signal that described baseband chip 2100 is sent, and according to described the second deck connectivity port A2 and described the second high level triggering and conducting port B12 is conducted or and described the second low level triggering and conducting port B02 one of be conducted both between switching, realize being complementary with the headset plug of current access.As when as described in the first simulation single-pole double-throw switch (SPDT) U1 be in as described in the second deck connectivity port A2 and as described in the state that is conducted of the first high level triggering and conducting port B11, simultaneously, when described the second simulation single-pole double-throw switch (SPDT) U2 is in the state that described the second deck connectivity port A2 and described the second high level triggering and conducting port B12 be conducted, described the 4th deck 2404 is connected with described MIC treatment circuit 2200, described the 3rd deck 2403 ground connection, this moment, described earphone socket met the second earphone interface standard; Opposite, when described the first simulation single-pole double-throw switch (SPDT) U1 is in the state that described the second deck connectivity port A2 and described the first low level triggering and conducting port B01 are conducted, simultaneously, when described the second simulation single-pole double-throw switch (SPDT) U2 is in the state that described the second deck connectivity port A2 and described the second low level triggering and conducting port B02 be conducted, described the 3rd deck 2403 ground connection and described the 4th deck 2404 are connected with described MIC treatment circuit 2200, and this moment, described earphone socket met the first earphone interface standard.
As shown in Figure 5, described switch switching circuit 2300 also comprises the first inductance B1; Described the first inductance B1 one end ground connection and the other end are connected with described the first low level triggering and conducting port B01 and the second high level triggering and conducting port B12 respectively.It will be understood by those skilled in the art that described the first inductance B1 can effectively suppress High-frequency Interference, guarantee the audio quality of electronic equipment, and promote the antistatic effect of described switch switching circuit 2300.
Preferably, the first inductance B1 is a magnetic bead, can better suppress High-frequency Interference, guarantees audio quality.
As shown in Figure 5, described the first simulation single-pole double-throw switch (SPDT) U1 and described the second simulation single-pole double-throw switch (SPDT) U2 all also comprise the power port VCC that connects battery, are used for access and meet the power supply of the operating voltage of described switch switching circuit 2300.
Concrete, as Fig. 3 and shown in Figure 5, described baseband chip 2100 is provided with the first control signal output port ENABLE1 of being connected with described the first control port S1 and with described the second control port S2, is connected.It will be understood by those skilled in the art that described the first control port S1 receives baseband chip 2100 and switches its state by the control signal that the first control signal output port ENABLE1 sends; In like manner, described the second control port (S2) reception baseband chip 2100 switches its state by the control signal that the second control signal output port ENABLE2 sends.
As shown in Figure 4, described MIC treatment circuit 2200 comprises identification module 2210, filtration module 2220 and every straight module 2230; Described identification module 2210 is connected with an end of described the first high level triggering and conducting port B11 and described the second low level triggering and conducting port B02, described baseband chip 2100 and described filtration module 2220 respectively; Describedly every straight module 2,230 one ends, be connected with the other end of described filtration module 2220 and the other end is connected with described baseband chip 2100.
Concrete, as shown in Figures 3 and 4, described baseband chip 2100 is provided with the first audio signal input end mouth MICN1, the second audio signal input end mouth MICP1, identification signal input port ADC_DET and bias voltage input port EARBIAS; Described identification module 2210 is connected with baseband chip 2100 by described bias voltage input port EARBIAS and described identification signal input port ADC_DET respectively; Describedly every straight module 2230, be connected with described baseband chip 2100 with the second audio signal input end mouth MICP1 by described the first audio signal input end mouth MICN1 respectively.Described baseband chip 2100 produces control signal according to the size of the level signal that the identification signal input port receives, by described the first control signal output port ENABLE1 and the second control signal output port ENABLE2, control signal is sent to respectively the first simulation single-pole double-throw switch (SPDT) U1 and the second simulation single-pole double-throw switch (SPDT) U2 again, the first simulation single-pole double-throw switch (SPDT) U1 and the second simulation single-pole double-throw switch (SPDT) U2 carry out the state of switch conducting according to its control signal of receiving, thereby realize automatically from the headset plug of different earphone interface standards, being complementary.
Further, as shown in Figure 4, described identification module 2210 comprises the first capacitor C 1, the second capacitor C 2, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3 and the second inductance B2; Described bias voltage input port EARBIAS, the first resistance R 1, the second resistance (R2), the 3rd resistance (R3) and described identification signal input port ADC_DET connect successively; Described the first capacitor C 1 one ends connect described bias voltage input port EARBIAS and other end ground connection; Described the second capacitor C 2 one ends are connected between described the first resistance R 1 and other end ground connection; Described the second inductance B2 one end is connected between described the second resistance R 2 and the 3rd resistance R 3 and the other end is connected respectively with described the first high level triggering and conducting port B11 and described the second low level triggering and conducting port B02 respectively.The operation principle of this identification module 2210 that the present embodiment provides is as follows: after electronic equipment has accessed earphone, i.e. and each deck of each terminal of headset plug and earphone socket after circuit is connected respectively, the working impedance R of earphone
MICCan carry out dividing potential drop to the output signal of described bias voltage input port EARBIAS in the mode of connecting with the first resistance R 1, the second resistance R 2, like this, the magnitude of voltage V of described identification signal input port ADC_DET signal
ADC_DETFor V
EARBIAS* R
MIC/ R1+R2+R
MIC.Further, described the second inductance B2 is a magnetic bead, and described magnetic bead B2 can play better inhibition High-frequency Interference, guarantees the quality of audio frequency input.
Further, as shown in Figure 4, describedly every straight module 2230, comprise the 3rd capacitor C 3 and the 4th capacitor C 4; Described the first audio signal input end mouth MICN1 and the other end that described the 3rd capacitor C 3 one ends connect baseband chip 2100 connect described filtration module 2220; Described the second audio signal input end mouth MICP1 and the other end that described the 4th capacitor C 4 one ends connect baseband chip 2100 connect described filtration module 2220.It will be appreciated by those skilled in the art that, described the 3rd capacitor C 3 and the 4th capacitor C 4 are used for the direct voltage of isolation audio signal, be used for guaranteeing that the first audio signal input end mouth MICN1 and the second audio signal input end mouth MICP1 of baseband chip input without direct current signal, guarantee the normal operation of the first audio signal input end mouth MICN1 and the second audio signal input end mouth MICP1.
In a nearlyer step, as shown in Figure 4, described filtration module 2220 comprises the 5th capacitor C 5, the 6th capacitor C 6 and the 7th electric capacity (C7); Described the 5th electric capacity two ends are connected with the 4th capacitor C 4 with described the 3rd capacitor C 3 respectively; Described the 6th capacitor C 6 one ends connect described the 4th capacitor C 4 and other end ground connection; Described the 7th capacitor C 7 one ends connect described the 3rd capacitor C 3 and other end ground connection.It will be appreciated by those skilled in the art that, but the common mode disturbances between described the 5th capacitor C 5 filtering the first audio signal input end mouth MICN1 and the second audio signal input end mouth MICP1, described the 6th capacitor C 6 and the 7th capacitor C 7 can be distinguished the differential mode interference of filtering the first audio signal input end mouth MICP1 and the second audio signal input end mouth MICN1, to guarantee the quality of two-way audio input signal.As shown in Figure 3, described baseband chip 2100 also is provided with interrupt signal input port EINT_HP, interrupt signal power port VDD18.As shown in Figure 6, the earphone automatic adaptation circuit that the present embodiment provides, also comprise the 6th resistance R 6, the 7th resistance R 7 and the 3rd inductance B3; Described earphone socket also comprises the 5th deck 2405.Described interrupt signal input port EINT_HP, described the 6th resistance R 6, described the 3rd inductance B3 and described the 5th deck 2405 circuit successively connect; Described the 7th resistance R 7 one ends connect described interrupt signal power port VDD18 and the other end is connected between described the 6th resistance R 6 and described the 3rd inductance B3.
It will be appreciated by those skilled in the art that, when headset plug not during the plugged earphone socket, provide high level signal to described interrupt signal input port EINT_HP together with the described interrupt signal power port VDD18 of described the 5th deck 2405 and baseband chip 2100, this moment, baseband chip 2100 was controlled described the first control signal output port ENABLE1 output low level control signals and described the second control signal output port ENABLE2 output high-level control signal.when described the first simulation single-pole double-throw switch (SPDT) U1 receives described low level control signal by its first control port S1, described the first simulation single-pole double-throw switch (SPDT) U1 switches to the state that described the second deck connectivity port A2 and described the first low level triggering and conducting port B01 are conducted, this moment, described the 4th deck 2404 was by ground connection after described the first inductance B1, simultaneously, when described the second simulation single-pole double-throw switch (SPDT) U2 receives described high-level control signal by its second control port S2, described the second single-pole double-throw switch (SPDT) switches to the state that its described second deck connectivity port A2 and described the second high level triggering and conducting port B12 are conducted, this moment, described the 3rd deck 2403 was by ground connection after described the first inductance B1, therefore described earphone socket is in the standby IDLE state of described the 3rd deck 2403 and the 4th deck 2404 equal ground connection.
It will be appreciated by those skilled in the art that, when headset plug plugged earphone socket, the 5th deck 2405 and the first deck 2401 are conducted, namely the 5th deck 2405 is connected with the first port 111 of headset plug, and described the first port D.C. resistance over the ground is negligible 32 ohm, and therefore this moment, the 5th deck 2405 was equivalent to ground connection; Thus, this moment, the 5th deck 2405 provided ground signalling to described interrupt signal input port EINT_HP together with described the 7th resistance R 7, this moment, baseband chip 2100 triggering low levels were interrupted, and baseband chip 2100 detects the magnitude of voltage V of described identification signal input port ADC_DET signals
ADC_DET.
Magnitude of voltage V when described identification signal input port ADC_DET signal
ADC_DETWhile being greater than or equal to 0.9V, described baseband chip 2100 is controlled described the first control signal output port ENABLE1 and the second equal output low level signal of control signal output port ENABLE2.This moment, described the first simulation single-pole double-throw switch (SPDT) U1 received described low level control signal by its first control port S1, described the first simulation single-pole double-throw switch (SPDT) U1 switches to the state that described the second deck connectivity port A2 and described the first low level triggering and conducting port B01 are conducted, and this moment, described the 4th deck 2404 passed through ground connection after described the first inductance B1; Simultaneously, when described the second simulation single-pole double-throw switch (SPDT) U2 receives described low level control signal by its second control port S2, described the second single-pole double-throw switch (SPDT) switches to the state that its described second deck connectivity port A2 and described the second low level triggering and conducting port B02 are conducted, this moment, described the 3rd deck 2403 was conducted with described MIC treatment circuit 2200, therefore, the earphone socket of this moment meets the first earphone interface standard.
Magnitude of voltage V when described identification signal input port ADC_DET signal
ADC_DETDuring less than 0.9V, described baseband chip 2100 controls described the first control signal output port ENABLE1 and the second control signal output port ENABLE2 all exports high level signal.This moment, described the first simulation single-pole double-throw switch (SPDT) U1 received described high-level control signal by its first control port S1, described the first simulation single-pole double-throw switch (SPDT) U1 switches to the state that described the second deck connectivity port A2 and described the first high level triggering and conducting port B11 are conducted, and this moment, described the 4th deck 2404 and described MIC treatment circuit 2200 were conducted; Simultaneously, when described the second simulation single-pole double-throw switch (SPDT) U2 receives described high-level control signal by its second control port S2, described the second single-pole double-throw switch (SPDT) switches to the state that its described second deck connectivity port A2 and described the second high level triggering and conducting port B12 are conducted, this moment, described the 3rd deck 2403 was by ground connection after described the first inductance B1, therefore, the earphone socket of this moment meets the first earphone interface standard.
Further, as shown in Figure 3, described baseband chip 2100 also is provided with left channel audio signal output port (LEFT_AUDIO) and right channel audio signal output port (RIGHT_AUDIO); As shown in Figure 6, earphone socket also is provided with the first deck 2401 and the second deck 2402; Described the first deck 2401 access described left channel audio signal output ports (LEFT_AUDIO); Described the second deck 2402 access described right channel audio signal output ports (RIGHT_AUDIO).It will be appreciated by those skilled in the art that, in the time of in headset plug is inserted into earphone socket, the first terminal 111 of headset plug is connected with described the first deck 2401 circuit, the second terminal 112 of headset plug is connected with described the second deck 2402 circuit, baseband chip 2100 by described left channel audio signal output port (LEFT_AUDIO) and described right channel audio signal output port (RIGHT_AUDIO) to the earphone output audio signal.
Need to prove; the first simulation single-pole double-throw switch (SPDT) U1 that described switch switching circuit 2300 is included and the second simulation single-pole double-throw switch (SPDT) U2 are single channel simulation single-pole double-throw switch (SPDT); also can be equal to and substitute this two functions that single channel simulation single-pole double-throw switch (SPDT) is realized with a two-way simulation single-pole double-throw switch (SPDT), this implementation method also should belong to protection scope of the present invention.
Embodiment two
As shown in Figure 7, the present embodiment provides a kind of method of automatic adaptation headset plug, comprises the steps:
The described earphone socket interface circuit of S1 is set up circuit with headset plug and is connected, and to described baseband chip, sends interrupt signal;
The described baseband chip of S2 enters the magnitude of voltage V that interrupts and detect its identification signal input port ADC_DET
ADC_DET
S3 is according to described magnitude of voltage V
ADC_DETControl the conducting state of described switch switching circuit.It will be appreciated by those skilled in the art that, when the headset plug of various criterion is connected with earphone socket interface circuit circuitry phase, the magnitude of voltage of the identification signal of described MIC treatment circuit 2200 outputs is different, described baseband chip is by detecting the size of this magnitude of voltage, what can pick out current plugged earphone socket is the headset plug of which standard, thus the conducting state that the switching of control switch commutation circuit is complementary as for this standard.
Described S3 is according to described magnitude of voltage V
ADC_DETControl the conducting state of described switch switching circuit, specifically comprise:
S31 judges described magnitude of voltage V
ADC_DETWhether less than 0.9V;
As described magnitude of voltage V
ADC_DETWhile being greater than or equal to 0.9V, carry out S311; If magnitude of voltage during less than 0.9V, is carried out S312;
Described S311 comprises:
The described baseband chip 2100 of S3111 is controlled described the first control signal output port ENABLE1 and the second equal output low level signal of control signal output port ENABLE2;
Described the first simulation single-pole double-throw switch (SPDT) U1 of S3112 switches to the state that described the second deck 2402 connectivity port A1 and described the first low level triggering and conducting port B01 are conducted, and described the second single-pole double-throw switch (SPDT) switches to the state that its described second deck connectivity port A2 and described the second low level triggering and conducting port B02 are conducted.This moment, described the 3rd deck 2403 was conducted with described MIC treatment circuit 2200, and earphone socket meets the first earphone interface standard.
Described S312 comprises:
The described baseband chip 2100 of S3121 controls described the first control signal output port ENABLE1 and the second control signal output port ENABLE2 all exports high level signal.
Described the first simulation single-pole double-throw switch (SPDT) U1 of S3122 switches to the state that described the second deck connectivity port A2 and described the first high level triggering and conducting port B11 are conducted; When described the second simulation single-pole double-throw switch (SPDT) U2 received described high-level control signal by its second control port S2, described the second single-pole double-throw switch (SPDT) switched to the state that its described second deck connectivity port A2 and described the second high level triggering and conducting port B12 are conducted.This moment, described the 4th deck 2403 was conducted with described MIC treatment circuit 2200, and earphone socket meets the second earphone interface standard.
It should be noted that finally: above embodiment only, in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment, the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (12)
1. earphone automatic adaptation circuit, comprise baseband chip (2100) and earphone socket interface circuit (2400), it is characterized in that: also comprise the MIC treatment circuit (2200) that is connected with described baseband chip (2100) circuitry phase and be connected to described earphone socket interface circuit (2400) and described MIC treatment circuit (2200) between be used for according to the instruction described earphone socket interface circuit of switching (2400) of baseband chip (2100) and the switch switching circuit (2300) of the connection status of described MIC treatment circuit (2200).
2. earphone automatic adaptation circuit as claimed in claim 1 is characterized in that: described switch switching circuit (2300) comprises that the first simulation single-pole double-throw switch (SPDT) (U1) and second simulates single-pole double-throw switch (SPDT) (U2); Described the first simulation single-pole double-throw switch (SPDT) (U1) is equipped with the first high level triggering and conducting port (B11), the first low level triggering and conducting port (B01), the second deck (2402) connectivity port (A1) and the first control port (S1); Described the second simulation single-pole double-throw switch (SPDT) (U2) is equipped with the second high level triggering and conducting port (B12), the second low level triggering and conducting port (B02), the second deck connectivity port (A2) and the second control port (S2); Described the first high level triggering and conducting port (B11) all is connected with described MIC treatment circuit (2200) with described the second low level triggering and conducting port (B02); Described the second deck (2402) connectivity port (A1) connects the 4th deck (2404); Described the second deck connectivity port (A2) connects the 3rd deck (2403); Described the first control port (S1) and described the second control port (S2) all are connected with described baseband chip (2100); Described the first low level triggering and conducting port (B01) and the second high level triggering and conducting port (B12) be ground connection all.
3. earphone automatic adaptation circuit as claimed in claim 2, is characterized in that: also comprise the first inductance (B1); Described the first inductance (B1) end ground connection and the other end are connected with described the first low level triggering and conducting port (B01) and the second high level triggering and conducting port (B12) respectively.
4. earphone automatic adaptation circuit as claimed in claim 2 is characterized in that: described MIC treatment circuit (2200) comprises identification module (2210), filtration module (2220) and every straight module (2230); Described identification module (2210) is connected with an end of described the first high level triggering and conducting port (B11) and described the second low level triggering and conducting port (B02), described baseband chip (2100) and described filtration module (2220) respectively; Describedly every straight module (2230) one ends, be connected with the other end of described filtration module (2220) and the other end is connected with described baseband chip (2100).
5. earphone automatic adaptation circuit as claimed in claim 4, it is characterized in that: described baseband chip (2100) is provided with the first audio signal input end mouth (MICN1), the second audio signal input end mouth (MICP1), identification signal input port (ADC_DET) and bias voltage input port (EARBIAS); Described identification module (2210) is connected with baseband chip (2100) by described bias voltage input port (EARBIAS) and described identification signal input port (ADC_DET) respectively; Describedly every straight module (2230), be connected with described baseband chip (2100) with the second audio signal input end mouth (MICP1) by described the first audio signal input end mouth (MICN1) respectively.
6. earphone automatic adaptation circuit as claimed in claim 5, it is characterized in that: described identification module (2210) comprises the first electric capacity (C1), the second electric capacity (C2), the first resistance (R1), the second resistance (R2), the 3rd resistance (R3) and the second inductance (B2); Described bias voltage input port (EARBIAS), the first resistance (R1), the second resistance (R2), the 3rd resistance (R3) and described identification signal input port (ADC_DET) are connected successively; Described the first electric capacity (C1) end connects described bias voltage input port (EARBIAS) and other end ground connection; Described the second electric capacity (C2) end is connected between described the first resistance (R1) and other end ground connection; Described the second inductance (B2) end is connected between described the second resistance (R2) and the 3rd resistance (R3) and the other end is connected respectively with described the first high level triggering and conducting port (B11) and described the second low level triggering and conducting port (B02) respectively.
7. earphone automatic adaptation circuit as claimed in claim 4 is characterized in that: describedly every straight module (2230), comprise the 3rd electric capacity (C3) and the 4th electric capacity (C4); Described the first audio signal input end mouth (MICN1) and the other end that described the 3rd electric capacity (C3) end connects baseband chip (2100) connect described filtration module (2220); Described the second audio signal input end mouth (MICP1) and the other end that described the 4th electric capacity (C4) end connects baseband chip (2100) connect described filtration module (2220).
8. earphone automatic adaptation circuit as claimed in claim 4, it is characterized in that: described filtration module (2220) comprises the 5th electric capacity (C5), the 6th electric capacity (C6) and the 7th electric capacity (C7); Described the 5th electric capacity two ends are connected with the 4th electric capacity (C4) with described the 3rd electric capacity (C3) respectively; Described the 6th electric capacity (C6) end connects described the 4th electric capacity (C4) and other end ground connection; Described the 7th electric capacity (C7) end connects described the 3rd electric capacity (C3) and other end ground connection.
9. earphone automatic adaptation circuit as claimed in claim 2, it is characterized in that: described baseband chip (2100) is provided with the first control signal output port (ENABLE1) that is connected with described the first control port (S1) and the second control signal output port (ENABLE2) that is connected with described the second control port (S2).
10. earphone automatic adaptation circuit as claimed in claim 2, it is characterized in that: described baseband chip (2100) also is provided with interrupt signal input port (EINT_HP), interrupt signal power port (VDD18); Described earphone socket interface circuit (2400) also comprises the 6th resistance (R6), the 7th resistance (R7) and the 3rd inductance (B3) and the 5th deck (2405); Described interrupt signal input port (EINT_HP), described the 6th resistance (R6), described the 3rd inductance (B3) and described the 5th deck (2405) circuit successively connect; Described the 7th resistance (R7) end connects described interrupt signal power port (VDD18) and the other end is connected between described the 6th resistance (R6) and described the 3rd inductance (B3).
11. the method for an automatic adaptation headset plug, comprise the steps:
The described earphone socket interface circuit of S1 is set up circuit with headset plug and is connected, and to described baseband chip, sends interrupt signal;
The described baseband chip of S2 enters the magnitude of voltage (V that interrupts and detect its identification signal input port (ADC_DET)
ADC_DET);
S3 is according to described magnitude of voltage (V
ADC_DET) control the conducting state of described switch switching circuit.
12. method as claimed in claim 11 is characterized in that: described S3 comprises:
S31 judges described magnitude of voltage (V
ADC_DET) whether less than 0.9V; As described magnitude of voltage (V
ADC_DET) while being greater than or equal to 0.9V, carry out S311; If magnitude of voltage during less than 0.9V, is carried out S312;
Described S311 comprises:
The described baseband chip of S3111 (2100) is controlled described the first control signal output port (ENABLE1) and the equal output low level signal of the second control signal output port (ENABLE2);
Described the first simulation single-pole double-throw switch (SPDT) (U1) of S3112 switches to the state that described the second deck (2402) connectivity port (A1) and described the first low level triggering and conducting port (B01) are conducted, and described the second single-pole double-throw switch (SPDT) switches to the state that its described second deck connectivity port (A2) and described the second low level triggering and conducting port (B02) are conducted;
Described S312 comprises:
The described baseband chip of S3121 (2100) is controlled described the first control signal output port (ENABLE1) and the second control signal output port (ENABLE2) is all exported high level signal.
Described the first simulation single-pole double-throw switch (SPDT) (U1) of S3122 switches to the state that described the second deck connectivity port (A2) and described the first high level triggering and conducting port (B11) are conducted; By its second control port (S2) while receiving described high-level control signal, described the second single-pole double-throw switch (SPDT) switches to the state that its described second deck connectivity port (A2) and described the second high level triggering and conducting port (B12) are conducted when described the second simulation single-pole double-throw switch (SPDT) (U2).
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CN105959845A (en) * | 2014-01-09 | 2016-09-21 | 北京奇虎科技有限公司 | External equipment identification circuit, method, device and system based on earphone socket |
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Application publication date: 20131113 |