CN103390560B - Formation method and the semiconductor devices of semiconductor devices - Google Patents
Formation method and the semiconductor devices of semiconductor devices Download PDFInfo
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- CN103390560B CN103390560B CN201310317724.4A CN201310317724A CN103390560B CN 103390560 B CN103390560 B CN 103390560B CN 201310317724 A CN201310317724 A CN 201310317724A CN 103390560 B CN103390560 B CN 103390560B
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Abstract
The invention provides a kind of formation method and semiconductor devices of semiconductor devices, wherein the formation method of semiconductor devices comprises provides substrate, form at least two grids that are arranged in parallel at described substrate surface, each described grid comprises multistage, between adjacent two grids, have multistage groove, the depth-to-width ratio of at least one section of groove is more than or equal to 1; Around described grid, form side wall; In the substrate of described side wall both sides, form source electrode and drain electrode; After forming described source electrode and drain electrode, form interlayer dielectric layer at described substrate surface and gate surface. Adopt formation method of the present invention can reduce the parasitic capacitance between grid and source electrode, grid and drain electrode, improved the performance of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of semiconductor devices and halfConductor device.
Background technology
In semiconductor devices, conventionally between grid and source electrode, grid and drain electrode, form parasitic capacitance. ShouldParasitic capacitance can affect the performance of semiconductor devices, for example, can affect the speed of service of semiconductor devices.Therefore,, in semiconductor devices, wish the parasitic capacitance forming between grid and source electrode, grid and drain electrodeThe smaller the better. And for some semiconductor device application when the radio circuit, to grid and source electrode, gridAnd drain electrode between parasitic capacitance require harsher.
The formation method of semiconductor devices of the prior art, comprising:
With reference to reference to figure 1 and Fig. 2, substrate 100 is provided, on substrate 100, form at least two grids 101,Formation side wall 102 around grid 101 forms source electrode and drain electrode (figure in the substrate of side wall 102 both sidesDo not show).
Afterwards, form silicon dioxide layer 103, cover substrate 100 with and the structure of upper formation, then rightSilicon dioxide layer 103 carries out graphically, forming contact hole (contact) in silicon dioxide layer 103, is connecingTouching filled conductive material formation gate contact connector 105, source electrode contact plunger 104 and drain electrode in hole contacts slottingPlug 106, is electrically connected with grid 101, source electrode and drain electrode respectively.
But in prior art, between the grid in the semiconductor devices of formation and source electrode, grid and drain electrodeParasitic capacitance larger.
More formation methods about semiconductor devices please refer to U.S. that publication number is US2011/0018091A1State's patent.
Summary of the invention
The problem that the present invention solves is grid and the source electrode, grid in the semiconductor devices that forms of prior artAnd drain electrode between parasitic capacitance larger.
For addressing the above problem, the invention provides a kind of formation method of semiconductor devices, comprising: carryFor substrate, form at least two grids that are arranged in parallel at described substrate surface, each described grid comprisesMultistage, has multistage groove between adjacent two grids, and the depth-to-width ratio of at least one section of groove is more than or equal to 1;
Around described grid, form side wall;
In the substrate of described side wall both sides, form source electrode and drain electrode;
After forming described source electrode and drain electrode, form interlayer dielectric layer at described substrate surface and gate surface.
Optionally, form in the technique of at least two grids at described substrate surface, also form extremely describedThe line of few two grids electrical connection, the material of described line is identical with the material of described grid.
Optionally, the depth-to-width ratio of at least one section of groove is less than 1, and described source electrode or drain electrode are little in described depth-to-width ratioIn 1 beneath trenches.
Optionally, the material of described interlayer dielectric layer is SiO2, the formation method of described interlayer dielectric layer isPlasma strengthens ethyl orthosilicate deposition.
Optionally, described side wall comprises silicon nitride side wall, after forming the step of described source electrode and drain electrode,Before the step of described substrate surface and gate surface formation interlayer dielectric layer, also comprise step:
Remove described silicon nitride side wall.
Optionally, described semiconductor devices is to refer to gate transistor more.
The present invention also provides a kind of semiconductor devices, comprising:
Substrate, is positioned at least two grids that are arranged in parallel of described substrate surface, each described grid bagDraw together multistage, between adjacent two grids, have multistage groove, the depth-to-width ratio of at least one section of groove is more than or equal to 1;
Be positioned at described grid side wall around, source electrode and drain electrode in the substrate of described side wall both sides;
Fill described multistage groove, cover the interlayer dielectric layer of described substrate and described gate surface, described inIn interlayer dielectric layer, there is space.
Optionally, described grid is electrically connected by line, and the material of described line is identical with the material of grid.
Optionally, the depth-to-width ratio of at least one section of groove is less than 1, and described source electrode or drain electrode are little in described depth-to-width ratioIn 1 beneath trenches.
Optionally, described semiconductor devices is to refer to gate transistor more.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the technical program, form at least two grids that are arranged in parallel, each grid at described substrate surfaceThe utmost point comprises multistage, between adjacent two grids, has multistage groove, and the depth-to-width ratio of at least one section of groove is greater than etc.In 1, form interlayer dielectric layer at described substrate surface and gate surface, in the interlayer dielectric layer in this grooveCan form larger air-gap, make the dielectric constant of the material between grid and source electrode, grid and drain electrodeObviously reduce, thereby reduced the parasitic capacitance between grid and source electrode, grid and drain electrode, after having improvedThe performance of the continuous whole semiconductor devices forming. In the time that this semiconductor device application is in radio circuit, canObviously to reduce the parasitic capacitance between grid and source electrode, grid and drain electrode.
Brief description of the drawings
Fig. 1 is the planar structure schematic diagram of the semiconductor devices of prior art;
Fig. 2 is the local amplification profile structural representation of Fig. 1 along AA direction;
Fig. 3 is the planar structure schematic diagram of the grid of the specific embodiment of the invention;
Fig. 4 is the part section structural representation of the oval delineation of Fig. 3 region along BB direction;
Fig. 5 is the part section structural representation of the oval delineation of Fig. 3 region along CC direction;
Fig. 6 is the grid of the specific embodiment of the invention and the planar structure schematic diagram of side wall;
Fig. 7 is the part section structural representation of Fig. 6 along BB direction;
Fig. 8 is the planar structure schematic diagram of the semiconductor devices of the specific embodiment of the invention;
Fig. 9 is the part section structural representation of Fig. 8 along BB direction;
Figure 10 is the part section structural representation of Fig. 8 along CC direction.
Detailed description of the invention
Cause larger former of parasitic capacitance between grid and source electrode, grid and the drain electrode in semiconductor devicesBecause:
The parasitic capacitance forming between grid and source electrode, grid and drain electrode comprises sidewall capacitance and overlap capacitance.Wherein, gate bottom and source electrode, gate bottom and drain electrode have overlapping region, the electric capacity of this overlapping regionFor overlap capacitance. In gate lateral wall direction, the electric capacity between grid and source electrode, grid and drain electrode is sidewallElectric capacity. With reference to figure 2, the pole plate of sidewall capacitance is grid 101 and source electrode, or is grid 101 and drain electrode.Material between this pole plate is mainly silicon dioxide layer 103 and side wall 102. In prior art, silicaLayer 103 is very fine and close, and the dielectric constant of fine and close silicon dioxide layer 103 is than fine and close not silicon dioxide layerDielectric constant large, thereby make the dielectric constant K of material between pole plate larger, and then make grid and sourceSidewall capacitance C between the utmost point, grid and drain electrodeSidewallLarger, in the situation that overlap capacitance is constant, grid andParasitic capacitance between source electrode, grid and drain electrode is also larger, affects transistorized performance.
Inventor, through creative work, obtains a kind of formation method of semiconductor devices.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawingThe specific embodiment of the present invention is described in detail. In the time that the embodiment of the present invention is described in detail in detail, for ease of sayingBright, schematic diagram can be disobeyed general ratio and be done local amplification, and described schematic diagram is example, and it is at thisShould not limit the scope of the invention.
With reference to figure 3 and Fig. 4, Fig. 5, substrate 200 is provided, form at least two on described substrate 200 surfaces and put downThe grid 201 that row is arranged, each described grid 201 comprises multistage, between adjacent two grids, has multistage ditchGroove, the depth-to-width ratio of at least one section of groove is more than or equal to 1.
In specific embodiment, the material of described substrate 200 can be monocrystalline silicon (Si), monocrystalline germanium (Ge),Or SiGe (GeSi), carborundum (SiC); Also can be silicon-on-insulator (SOI), on insulatorGermanium (GOI); Or can also be III-V compounds of group such as other material, such as GaAs.
With reference to figure 3, to Fig. 5, substrate 200 surfaces form at least two grids that are arranged in parallel 201, every gridThe utmost point 201 comprises five sections, be respectively first paragraph grid 2011, second segment grid 2012, the 3rd section of grid 2013,The 4th section of grid 2014 and the 5th section of grid 2015. Between adjacent grid 201, have multistage groove, these are manyIn section groove, have at least the depth-to-width ratio of one section of groove to be more than or equal to 1, in the present embodiment, adjacent grid 201The 3rd section of grid 2013 between the depth-to-width ratio of groove 205 that forms be more than or equal to 1(with reference to figure 4). AdjacentGrid 201 between multistage groove in have at least the depth-to-width ratio of one section of groove to be less than 1, in the present embodiment,Between the 5th section of grid 2015 of neighboring gates, form groove 206(with reference to figure 5), the depth-to-width ratio of groove 206Be less than 1. Between the 4th section of grid 2014 of neighboring gates 201, between second segment grid 2012 and first paragraphThe depth-to-width ratio of the groove forming between grid 2011 is also less than 1.
The depth-to-width ratio that has one section of groove 205 at least between neighboring gates 201 is more than or equal to 1, after just guaranteeingContinue and in the interlayer dielectric layer in groove 205, there is the larger and a fairly large number of air-gap of volume. And, systemWhile making semiconductor devices of the present invention, the depth-to-width ratio of the above-mentioned groove 205 between neighboring gates 201 is larger,The volume of the air-gap forming can be larger, and the quantity of air-gap can be more.
It should be noted that, the depth-to-width ratio of the above-mentioned groove 205 between neighboring gates 201 is more than or equal at 1 o'clock,Distance between the 3rd section of grid 2013 on these groove 205 both sides is too near, has exceeded photoetching process and has formed and sourceThe accuracy rating of the contact hole that the utmost point 211 or drain electrode 210 connect, cannot be more than or equal in depth-to-width ratio 1 groove205 places form the contact hole of source electrode 211 or drain electrode 210. Therefore, in the present embodiment, with reference to figure 3 and Fig. 5,Between adjacent two grids, at least also comprise one section of groove 206 that depth-to-width ratio is less than 1, the follow-up formation of source electrode 211Below this groove 206. Distance between the 5th section of grid 2015 of the grid 201 of these groove 206 both sidesFar away, can, at the interior formation contact hole of the interlayer dielectric layer 203 at these groove 206 places, then, can connectTouch filled conductive material in hole and form contact plunger (with reference to figure 8 and Figure 10).
In the present embodiment, between grid, be electrically connected by line 207. Acting as of electrical connection: gridBetween the depth-to-width ratio of groove 205 be more than or equal at 1 o'clock, the distance between the 3rd section of grid 2013 of grid is veryLittle, make to produce parasitic capacitance between the 3rd section of grid 2013. In the present embodiment, grid is passed through to line207 be electrically connected after, the current potential of each grid is equated, now, the 3rd of the very little grid of distanceBetween section grid 2013, just parasitic capacitance can not be produced.
In the present embodiment, line 207 is by grid 201 parallel connections, and the semiconductor devices of follow-up formation is to refer to grid moreTransistor (multi-fingertransisitors). That is to say, refer to that gate transistor is by multiple transistors moreBe formed in parallel, be specially: the source electrode of grid one side is carried out to parallel connection, and the drain electrode of grid opposite side is carried out alsoConnection, grid carries out parallel connection by line 207, and many fingers gate transistor of formation can increase drive current.
In other embodiments, within line 207 is connected grid 201 also to belong to the scope of protection of the invention,The semiconductor devices of follow-up formation is the device that multiple transistor series form. Be specially grid one sideSource electrode is connected with the drain electrode of neighboring gates.
In the present embodiment, the method that forms grid 201 and line 207 on substrate 200 surfaces is as follows: at substrate200 surfaces form polysilicon layer. On polysilicon layer, form patterned mask layer, definition grid and companyThe shape of line and distribution, taking described patterned mask layer as mask etching polysilicon layer, at substrate 200Surface forms grid 201, has also formed line 207 simultaneously.
It should be noted that, in the present embodiment, patterned mask layer is preferably photoresist, and reason is as follows:In subsequent technique, have and remove the mask layer of top portions of gates and form metal silicide at the top of gridStep, because metal silicide can reduce the contact resistance of top portions of gates. In the present embodiment, photoresistRemove easily, the processing step of removal is fairly simple, and removal effect is relatively good, is difficult for forming residual.In other embodiments, patterned mask layer can be the hard mask materials such as boron nitride, still, removesThe process of this hard mask is more than the process complexity of removing photoresist, and technology difficulty is larger.
With reference to figure 6 and Fig. 7, around described grid 201, form side wall 202, in described side wall 202 both sidesIn substrate, form source electrode 211 and drain electrode 210.
In the present embodiment, side wall 202 is three-decker (not shown), and nexine is monox lateral wall, centreLayer is silicon nitride side wall, and skin is monox lateral wall.
Then, in the substrate of described side wall 202 both sides, form source electrode 211 and drain electrode 210, wherein form sourceThe method of the utmost point 211 and drain electrode 210, for those skilled in the art know technology, does not repeat them here.
It should be noted that, the silicon nitride side wall in side wall 202 is also grid 201 and source electrode 211, grid 201And the material draining between 210, its dielectric constant is higher than monox lateral wall, also higher than shape in subsequent techniqueThe dielectric constant of the interlayer dielectric layer becoming. Therefore, in the subsequent technique of the present embodiment, when forming source electrode211 and drain electrode 210 steps after, after the mission that is to say side wall 202 completes, in order further to reduce gridSidewall capacitance between the utmost point 201 and source electrode 211, grid 201 and drain electrode 210, can remove silicon nitride side wallRemove, so that the reduced dielectric constant of material between grid 201 and source electrode 211, grid 201 and drain electrode 210.In the present embodiment, the surrounding of silicon nitride side wall also has monox lateral wall, therefore needs first by monox lateral wallRemove, and then remove silicon nitride side wall.
In other embodiments, side wall is single layer structure. The material of side wall is silicon nitride. When making of side wallAfter having ordered, in order further to reduce the sidewall capacitance between grid and source electrode, grid and drain electrode, canDirectly silicon nitride side wall is removed.
In other embodiments, the material of side wall is double-decker. Nexine is silicon nitride side wall, and skin isMonox lateral wall. After the mission of side wall completes, in order further to reduce grid and source electrode, grid and leakageSidewall capacitance between the utmost point, can first remove monox lateral wall, then silicon nitride side wall is removed.
With reference to figure 8, after forming described source electrode 211 and drain electrode 210, at described substrate 200 surfaces and grid201 surfaces form interlayer dielectric layer 203.
Form the method for interlayer dielectric layer 203 and be chemical vapour deposition (CVD) (ChemicalVaporDeposition,CVD). In the present embodiment, the material of interlayer dielectric layer 203 is silica. Interlayer dielectric layer 203Formation method is that plasma strengthens ethyl orthosilicate deposition (PE-TEOS, PlasmaEnhancedThe filling capacity of the interlayer dielectric layer 203 that TEOS), the method forms is bad. Fill when adopting the methodWhen groove 205, because the depth-to-width ratio of groove 205 is more than or equal to 1, therefore, form empty in the interior meeting of groove 205Air gap 204, and air-gap 204 volumes that form are large and quantity is many. Making semiconductor device of the present inventionWhen part, the depth-to-width ratio of the groove between at least one section of grid of neighboring gates is larger, the air-gap of formationVolume can be larger, and the quantity of air-gap can be more. In the present embodiment, due to the dielectric constant minimum of vacuum,Volume air-gap 204 large and that quantity is many can reduce the K value of interlayer dielectric layer 203 greatly, thereby can reduceThe dielectric constant of material between pole plate, and then can reduce sidewall capacitance CSidewall, reduce grid 201 and source electrode,The parasitic capacitance forming between grid 201 and drain electrode. In the time that this semiconductor device application is in radio circuit,Can obviously reduce the parasitic capacitance between grid and source electrode, grid and drain electrode.
It should be noted that, the present invention be not suitable for adopting deposition boron phosphoric acid glass (BPSG,Boro-phospho-sillicate-glass) method and high-density plasma (HDP, highdensityplasma)Method forms interlayer dielectric layer 203, because, the filling of the interlayer dielectric layer 203 that these two kinds of methods formAbility is good, is more than or equal to 1 groove 205 even if fill depth-to-width ratio, also can not form air in groove 205Gap.
In other embodiments, the material of described interlayer dielectric layer can also be low-K dielectric material or ultralow KDielectric material. Described low-K dielectric material is SiOF, SiCOH, SiO, SiCO or SiCON. DescribedUltralow K dielectric material is black diamond.
It should be noted that, if the material of interlayer dielectric layer adopts low-K dielectric material or super low-K dielectric materialMaterial, also can reduce the parasitic capacitance between grid and source electrode, grid and drain electrode, but some low K after allDielectric material, especially ultralow K dielectric material cost is higher, and not universal at present. So thisBright technical scheme, not only can significantly reduce the dielectric of material between grid and source electrode, grid and drain electrodeConstant, can obviously reduce the parasitic capacitance between grid and source electrode, grid and drain electrode accordingly, andCan also reduce production costs greatly. Certainly, in other embodiments, the material of interlayer dielectric layer isLow-K dielectric material, and depth-to-width ratio between two adjacent grids is more than or equal to low in 1 grooveThe technique that forms air-gap in K dielectric material is also applicable to the present invention, although cost is high, reduces gridAnd the effect of parasitic capacitance between source electrode, grid and drain electrode can be better. Those skilled in the art can rootThe technique on border is selected factually.
Need to go on to say, in other embodiments, form after interlayer dielectric layer, also comprise:In described interlayer dielectric layer, form the interconnection structure of described at least two grids electrical connection.
In conjunction with reference to Fig. 8 to Figure 10, the present invention also provides a kind of semiconductor devices, comprising:
Substrate 200, is positioned at least two grids that are arranged in parallel 201 on described substrate 200 surfaces, Mei GesuoState grid 201 and comprise multistage, between adjacent two grids 201, there is multistage groove, at least one section of groove 205(ginsengExamine Fig. 4) depth-to-width ratio be more than or equal to 1.
Be positioned at described grid 201 side wall 202 around, source electrode and leakage in described side wall 202 both sides substratesThe utmost point;
Fill described multistage groove, cover the interlayer dielectric layer on described substrate 200 and described grid 201 surfaces203, in described interlayer dielectric layer 203, there is space 204.
Wherein, described grid 201 is electrically connected by line 207, the material of described line 207 and the material of gridExpect identical.
In the present embodiment, groove 205(is with reference to figure 4) be to be formed by the 3rd section of adjacent grid 2013.
In other embodiments, between the neighboring gates 201 of semiconductor devices of the present invention, also comprise at leastOne section of depth-to-width ratio is less than 1 groove 206(with reference to figure 5), groove 206 is by the 5th section of adjacent grid2015 formation. The beneath trenches that source electrode or drain electrode are less than 1 in described depth-to-width ratio.
In other embodiments, the material of interlayer dielectric layer 203 is low-K dielectric material or super low-K dielectricMaterial.
In other embodiments, the material of described interlayer dielectric layer is SiO2、SiOF、SiCOH、SiO、SiCO, SiCON or black diamond.
In the present embodiment, described semiconductor devices is to refer to gate transistor more.
Although the present invention with preferred embodiment openly as above, it is not for limiting the present invention, appointsWhat those skilled in the art without departing from the spirit and scope of the present invention, can utilize above-mentioned announcementMethod and technology contents are made possible variation and amendment to technical solution of the present invention, therefore, every not de-From the content of technical solution of the present invention, that according to technical spirit of the present invention, above embodiment is done is anySimple modification, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (8)
1. a formation method for semiconductor devices, is characterized in that, comprising:
Substrate is provided, forms at least two grids that are arranged in parallel, each described grid at described substrate surfaceThe utmost point comprises multistage, between adjacent two grids, has multistage groove, and the depth-to-width ratio of at least one section of groove is greater than etc.In 1;
Around described grid, form side wall;
In the substrate of described side wall both sides, form source electrode and drain electrode;
After forming described source electrode and drain electrode, form interlayer dielectric layer at described substrate surface and gate surface;The depth-to-width ratio of at least one section of groove is less than 1, and described source electrode or drain electrode are under described depth-to-width ratio is less than 1 grooveSide.
2. formation method as claimed in claim 1, is characterized in that, forms at least two at described substrate surfaceIn the technique of individual grid, also form the line of described at least two grids electrical connection, the material of described lineExpect identical with the material of described grid.
3. formation method as claimed in claim 1, is characterized in that, the material of described interlayer dielectric layer isSiO2, the formation method of described interlayer dielectric layer is that plasma strengthens ethyl orthosilicate deposition.
4. formation method as claimed in claim 1, is characterized in that, described side wall comprises silicon nitride side wall,After forming the step of described source electrode and drain electrode, form inter-level dielectric at described substrate surface and gate surfaceBefore the step of layer, also comprise step:
Remove described silicon nitride side wall.
5. formation method as claimed in claim 1, is characterized in that, described semiconductor devices is to refer to grid crystalline substance moreBody pipe.
6. a semiconductor devices, is characterized in that, comprising:
Substrate, is positioned at least two grids that are arranged in parallel of described substrate surface, each described grid bagDraw together multistage, between adjacent two grids, have multistage groove, the depth-to-width ratio of at least one section of groove is more than or equal to 1;
Be positioned at described grid side wall around, source electrode and drain electrode in the substrate of described side wall both sides;
Fill described multistage groove, cover the interlayer dielectric layer of described substrate and described gate surface, described inIn interlayer dielectric layer, there is space; The depth-to-width ratio of at least one section of groove is less than 1, and described source electrode or drain electrode are in instituteState the beneath trenches that depth-to-width ratio is less than 1.
7. semiconductor devices as claimed in claim 6, is characterized in that, described grid is electrically connected by line,The material of described line is identical with the material of grid.
8. semiconductor devices as claimed in claim 6, is characterized in that, described semiconductor devices is to refer to grid moreTransistor.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6238987B1 (en) * | 1999-09-13 | 2001-05-29 | United Microelectronics Corp. | Method to reduce parasitic capacitance |
| CN101399222A (en) * | 2007-09-24 | 2009-04-01 | 台湾积体电路制造股份有限公司 | Manufacturing method for semiconductor elements having air gap |
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| US6387797B1 (en) * | 1999-01-20 | 2002-05-14 | Philips Electronics No. America Corp. | Method for reducing the capacitance between interconnects by forming voids in dielectric material |
| US20020127763A1 (en) * | 2000-12-28 | 2002-09-12 | Mohamed Arafa | Sidewall spacers and methods of making same |
| US7045849B2 (en) * | 2003-05-21 | 2006-05-16 | Sandisk Corporation | Use of voids between elements in semiconductor structures for isolation |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6238987B1 (en) * | 1999-09-13 | 2001-05-29 | United Microelectronics Corp. | Method to reduce parasitic capacitance |
| CN101399222A (en) * | 2007-09-24 | 2009-04-01 | 台湾积体电路制造股份有限公司 | Manufacturing method for semiconductor elements having air gap |
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